codegen_mips.h revision 7940e44f4517de5e2634a7e07d58d0fb26160513 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_SRC_DEX_QUICK_CODEGEN_MIPS_CODEGENMIPS_H_
18#define ART_SRC_DEX_QUICK_CODEGEN_MIPS_CODEGENMIPS_H_
19
20#include "dex/compiler_internals.h"
21#include "mips_lir.h"
22
23namespace art {
24
25class MipsMir2Lir : public Mir2Lir {
26  public:
27
28    MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
29
30    // Required for target - codegen utilities.
31    bool SmallLiteralDivide(Instruction::Code dalvik_opcode, RegLocation rl_src,
32                                    RegLocation rl_dest, int lit);
33    int LoadHelper(int offset);
34    LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
35    LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
36                                  int s_reg);
37    LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
38    LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
39                                     int r_dest, int r_dest_hi, OpSize size, int s_reg);
40    LIR* LoadConstantNoClobber(int r_dest, int value);
41    LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
42    LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
43    LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
44    LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
45    LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
46                                      int r_src, int r_src_hi, OpSize size, int s_reg);
47    void MarkGCCard(int val_reg, int tgt_addr_reg);
48
49    // Required for target - register utilities.
50    bool IsFpReg(int reg);
51    bool SameRegType(int reg1, int reg2);
52    int AllocTypedTemp(bool fp_hint, int reg_class);
53    int AllocTypedTempPair(bool fp_hint, int reg_class);
54    int S2d(int low_reg, int high_reg);
55    int TargetReg(SpecialTargetRegister reg);
56    RegisterInfo* GetRegInfo(int reg);
57    RegLocation GetReturnAlt();
58    RegLocation GetReturnWideAlt();
59    RegLocation LocCReturn();
60    RegLocation LocCReturnDouble();
61    RegLocation LocCReturnFloat();
62    RegLocation LocCReturnWide();
63    uint32_t FpRegMask();
64    uint64_t GetRegMaskCommon(int reg);
65    void AdjustSpillMask();
66    void ClobberCalleeSave();
67    void FlushReg(int reg);
68    void FlushRegWide(int reg1, int reg2);
69    void FreeCallTemps();
70    void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
71    void LockCallTemps();
72    void MarkPreservedSingle(int v_reg, int reg);
73    void CompilerInitializeRegAlloc();
74
75    // Required for target - miscellaneous.
76    AssemblerStatus AssembleInstructions(uintptr_t start_addr);
77    void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
78    void SetupTargetResourceMasks(LIR* lir);
79    const char* GetTargetInstFmt(int opcode);
80    const char* GetTargetInstName(int opcode);
81    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
82    uint64_t GetPCUseDefEncoding();
83    uint64_t GetTargetInstFlags(int opcode);
84    int GetInsnSize(LIR* lir);
85    bool IsUnconditionalBranch(LIR* lir);
86
87    // Required for target - Dalvik-level generators.
88    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
89                                   RegLocation rl_src1, RegLocation rl_src2);
90    void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index,
91                                RegLocation rl_src, int scale);
92    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
93                             RegLocation rl_index, RegLocation rl_dest, int scale);
94    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
95                             RegLocation rl_index, RegLocation rl_src, int scale);
96    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
97                                   RegLocation rl_src1, RegLocation rl_shift);
98    void GenMulLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
99    void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
100    void GenAndLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
101    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
102                                  RegLocation rl_src1, RegLocation rl_src2);
103    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
104                                 RegLocation rl_src1, RegLocation rl_src2);
105    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
106                          RegLocation rl_src2);
107    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
108    bool GenInlinedCas32(CallInfo* info, bool need_write_barrier);
109    bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
110    bool GenInlinedSqrt(CallInfo* info);
111    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
112    void GenOrLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
113    void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
114    void GenXorLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
115    LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
116                                ThrowKind kind);
117    RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
118    RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
119    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
120    void GenDivZeroCheck(int reg_lo, int reg_hi);
121    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
122    void GenExitSequence();
123    void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
124    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
125    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
126    void GenSelect(BasicBlock* bb, MIR* mir);
127    void GenMemBarrier(MemBarrierKind barrier_kind);
128    void GenMonitorEnter(int opt_flags, RegLocation rl_src);
129    void GenMonitorExit(int opt_flags, RegLocation rl_src);
130    void GenMoveException(RegLocation rl_dest);
131    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
132                                               int first_bit, int second_bit);
133    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
134    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
135    void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
136    void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
137    void GenSpecialCase(BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case);
138
139    // Required for target - single operation generators.
140    LIR* OpUnconditionalBranch(LIR* target);
141    LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
142    LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
143    LIR* OpCondBranch(ConditionCode cc, LIR* target);
144    LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
145    LIR* OpFpRegCopy(int r_dest, int r_src);
146    LIR* OpIT(ConditionCode cond, const char* guide);
147    LIR* OpMem(OpKind op, int rBase, int disp);
148    LIR* OpPcRelLoad(int reg, LIR* target);
149    LIR* OpReg(OpKind op, int r_dest_src);
150    LIR* OpRegCopy(int r_dest, int r_src);
151    LIR* OpRegCopyNoInsert(int r_dest, int r_src);
152    LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
153    LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
154    LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
155    LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
156    LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
157    LIR* OpTestSuspend(LIR* target);
158    LIR* OpThreadMem(OpKind op, int thread_offset);
159    LIR* OpVldm(int rBase, int count);
160    LIR* OpVstm(int rBase, int count);
161    void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
162    void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
163    void OpTlsCmp(int offset, int val);
164
165    LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
166                          int s_reg);
167    LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
168    void SpillCoreRegs();
169    void UnSpillCoreRegs();
170    static const MipsEncodingMap EncodingMap[kMipsLast];
171    bool InexpensiveConstantInt(int32_t value);
172    bool InexpensiveConstantFloat(int32_t value);
173    bool InexpensiveConstantLong(int64_t value);
174    bool InexpensiveConstantDouble(int64_t value);
175
176  private:
177    void ConvertShortToLongBranch(LIR* lir);
178
179};
180
181}  // namespace art
182
183#endif  // ART_SRC_DEX_QUICK_CODEGEN_MIPS_CODEGENMIPS_H_
184