codegen_mips.h revision bf535be514570fc33fc0a6347a87dcd9097d9bfd 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
18#define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
19
20#include "dex/compiler_internals.h"
21#include "dex/quick/mir_to_lir.h"
22#include "mips_lir.h"
23
24namespace art {
25
26class MipsMir2Lir FINAL : public Mir2Lir {
27  public:
28    MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
29
30    // Required for target - codegen utilities.
31    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
32                            RegLocation rl_dest, int lit);
33    bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
34    void GenMultiplyByConstantFloat(RegLocation rl_dest, RegLocation rl_src1,
35                                    int32_t constant) OVERRIDE;
36    void GenMultiplyByConstantDouble(RegLocation rl_dest, RegLocation rl_src1,
37                                     int64_t constant) OVERRIDE;
38    LIR* CheckSuspendUsingLoad() OVERRIDE;
39    RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
40    LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
41                      OpSize size, VolatileKind is_volatile) OVERRIDE;
42    LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
43                         OpSize size) OVERRIDE;
44    LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
45    LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
46    LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
47                       OpSize size, VolatileKind is_volatile) OVERRIDE;
48    LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
49                          OpSize size) OVERRIDE;
50    LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest);
51    LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src);
52
53    /// @copydoc Mir2Lir::UnconditionallyMarkGCCard(RegStorage)
54    void UnconditionallyMarkGCCard(RegStorage tgt_addr_reg) OVERRIDE;
55
56    // Required for target - register utilities.
57    RegStorage Solo64ToPair64(RegStorage reg);
58    RegStorage TargetReg(SpecialTargetRegister reg);
59    RegStorage GetArgMappingToPhysicalReg(int arg_num);
60    RegLocation GetReturnAlt();
61    RegLocation GetReturnWideAlt();
62    RegLocation LocCReturn();
63    RegLocation LocCReturnRef();
64    RegLocation LocCReturnDouble();
65    RegLocation LocCReturnFloat();
66    RegLocation LocCReturnWide();
67    ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
68    void AdjustSpillMask();
69    void ClobberCallerSave();
70    void FreeCallTemps();
71    void LockCallTemps();
72    void CompilerInitializeRegAlloc();
73
74    // Required for target - miscellaneous.
75    void AssembleLIR();
76    int AssignInsnOffsets();
77    void AssignOffsets();
78    AssemblerStatus AssembleInstructions(CodeOffset start_addr);
79    void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
80    void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
81                                  ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
82    const char* GetTargetInstFmt(int opcode);
83    const char* GetTargetInstName(int opcode);
84    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
85    ResourceMask GetPCUseDefEncoding() const OVERRIDE;
86    uint64_t GetTargetInstFlags(int opcode);
87    size_t GetInsnSize(LIR* lir) OVERRIDE;
88    bool IsUnconditionalBranch(LIR* lir);
89
90    // Get the register class for load/store of a field.
91    RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
92
93    // Required for target - Dalvik-level generators.
94    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
95                           RegLocation rl_src1, RegLocation rl_src2, int flags);
96    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
97                     RegLocation rl_index, RegLocation rl_dest, int scale);
98    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
99                     RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark);
100    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
101                           RegLocation rl_shift, int flags);
102    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
103                          RegLocation rl_src2);
104    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105                         RegLocation rl_src2);
106    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
107                  RegLocation rl_src2);
108    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
109    bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE;
110    bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE;
111    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
112    bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long);
113    bool GenInlinedSqrt(CallInfo* info);
114    bool GenInlinedPeek(CallInfo* info, OpSize size);
115    bool GenInlinedPoke(CallInfo* info, OpSize size);
116    void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
117                        RegLocation rl_src2, int flags) OVERRIDE;
118    RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
119    RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
120    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
121    void GenDivZeroCheckWide(RegStorage reg);
122    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
123    void GenExitSequence();
124    void GenSpecialExitSequence();
125    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
126    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
127    void GenSelect(BasicBlock* bb, MIR* mir);
128    void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
129                          int32_t true_val, int32_t false_val, RegStorage rs_dest,
130                          RegisterClass dest_reg_class) OVERRIDE;
131    bool GenMemBarrier(MemBarrierKind barrier_kind);
132    void GenMoveException(RegLocation rl_dest);
133    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
134                                       int first_bit, int second_bit);
135    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
136    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
137    void GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
138    void GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
139    bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special);
140
141    // Required for target - single operation generators.
142    LIR* OpUnconditionalBranch(LIR* target);
143    LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
144    LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
145    LIR* OpCondBranch(ConditionCode cc, LIR* target);
146    LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
147    LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
148    LIR* OpIT(ConditionCode cond, const char* guide);
149    void OpEndIT(LIR* it);
150    LIR* OpMem(OpKind op, RegStorage r_base, int disp);
151    LIR* OpPcRelLoad(RegStorage reg, LIR* target);
152    LIR* OpReg(OpKind op, RegStorage r_dest_src);
153    void OpRegCopy(RegStorage r_dest, RegStorage r_src);
154    LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
155    LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
156    LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
157    LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
158    LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
159    LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
160    LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
161    LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
162    LIR* OpTestSuspend(LIR* target);
163    LIR* OpVldm(RegStorage r_base, int count);
164    LIR* OpVstm(RegStorage r_base, int count);
165    void OpRegCopyWide(RegStorage dest, RegStorage src);
166
167    // TODO: collapse r_dest.
168    LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
169                          OpSize size);
170    // TODO: collapse r_src.
171    LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
172                           OpSize size);
173    void SpillCoreRegs();
174    void UnSpillCoreRegs();
175    static const MipsEncodingMap EncodingMap[kMipsLast];
176    bool InexpensiveConstantInt(int32_t value);
177    bool InexpensiveConstantFloat(int32_t value);
178    bool InexpensiveConstantLong(int64_t value);
179    bool InexpensiveConstantDouble(int64_t value);
180
181    bool WideGPRsAreAliases() const OVERRIDE {
182      return false;  // Wide GPRs are formed by pairing.
183    }
184    bool WideFPRsAreAliases() const OVERRIDE {
185      return false;  // Wide FPRs are formed by pairing.
186    }
187
188    LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
189
190  private:
191    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
192    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
193                    RegLocation rl_src2);
194    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
195                    RegLocation rl_src2);
196
197    void ConvertShortToLongBranch(LIR* lir);
198    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
199                          RegLocation rl_src2, bool is_div, int flags) OVERRIDE;
200    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) OVERRIDE;
201};
202
203}  // namespace art
204
205#endif  // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
206