codegen_x86.h revision 49161cef10a308aedada18e9aa742498d6e6c8c7 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
19
20#include "dex/compiler_internals.h"
21#include "x86_lir.h"
22
23namespace art {
24
25class X86Mir2Lir : public Mir2Lir {
26  public:
27    X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen helpers.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                                    RegLocation rl_dest, int lit);
32    int LoadHelper(ThreadOffset offset);
33    LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34    LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
35                                  int s_reg);
36    LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37    LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
38                                     int r_dest, int r_dest_hi, OpSize size, int s_reg);
39    LIR* LoadConstantNoClobber(int r_dest, int value);
40    LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
41    LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42    LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
43    LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44    LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
45                                      int r_src, int r_src_hi, OpSize size, int s_reg);
46    void MarkGCCard(int val_reg, int tgt_addr_reg);
47
48    // Required for target - register utilities.
49    bool IsFpReg(int reg);
50    bool SameRegType(int reg1, int reg2);
51    // TODO: for consistency, make this return a RegStorage as well?
52    int AllocTypedTemp(bool fp_hint, int reg_class);
53    RegStorage AllocTypedTempWide(bool fp_hint, int reg_class);
54    int S2d(int low_reg, int high_reg);
55    int TargetReg(SpecialTargetRegister reg);
56    int GetArgMappingToPhysicalReg(int arg_num);
57    RegLocation GetReturnAlt();
58    RegLocation GetReturnWideAlt();
59    RegLocation LocCReturn();
60    RegLocation LocCReturnDouble();
61    RegLocation LocCReturnFloat();
62    RegLocation LocCReturnWide();
63    uint32_t FpRegMask();
64    uint64_t GetRegMaskCommon(int reg);
65    void AdjustSpillMask();
66    void ClobberCallerSave();
67    void FlushReg(int reg);
68    void FlushRegWide(int reg1, int reg2);
69    void FreeCallTemps();
70    void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
71    void LockCallTemps();
72    void MarkPreservedSingle(int v_reg, int reg);
73    void CompilerInitializeRegAlloc();
74
75    // Required for target - miscellaneous.
76    void AssembleLIR();
77    int AssignInsnOffsets();
78    void AssignOffsets();
79    AssemblerStatus AssembleInstructions(CodeOffset start_addr);
80    void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
81    void SetupTargetResourceMasks(LIR* lir, uint64_t flags);
82    const char* GetTargetInstFmt(int opcode);
83    const char* GetTargetInstName(int opcode);
84    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
85    uint64_t GetPCUseDefEncoding();
86    uint64_t GetTargetInstFlags(int opcode);
87    int GetInsnSize(LIR* lir);
88    bool IsUnconditionalBranch(LIR* lir);
89
90    // Required for target - Dalvik-level generators.
91    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
92                                   RegLocation rl_src1, RegLocation rl_src2);
93    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
94                             RegLocation rl_index, RegLocation rl_dest, int scale);
95    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
96                     RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark);
97    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
98                           RegLocation rl_src1, RegLocation rl_shift);
99    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
100    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
101    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
102    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
103                                  RegLocation rl_src1, RegLocation rl_src2);
104    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
105                                 RegLocation rl_src1, RegLocation rl_src2);
106    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
107                          RegLocation rl_src2);
108    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
109    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
110    bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
111    bool GenInlinedSqrt(CallInfo* info);
112    bool GenInlinedPeek(CallInfo* info, OpSize size);
113    bool GenInlinedPoke(CallInfo* info, OpSize size);
114    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
115    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
116    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
117    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
118    LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
119                                ThrowKind kind);
120    LIR* GenMemImmedCheck(ConditionCode c_code, int base, int offset, int check_value,
121                          ThrowKind kind);
122    RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
123    RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
124    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
125    void GenDivZeroCheck(int reg_lo, int reg_hi);
126    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
127    void GenExitSequence();
128    void GenSpecialExitSequence();
129    void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);
130    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
131    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
132    void GenSelect(BasicBlock* bb, MIR* mir);
133    void GenMemBarrier(MemBarrierKind barrier_kind);
134    void GenMoveException(RegLocation rl_dest);
135    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result,
136                                               int lit, int first_bit, int second_bit);
137    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
138    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
139    void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
140    void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
141
142    /*
143     * @brief Generate a two address long operation with a constant value
144     * @param rl_dest location of result
145     * @param rl_src constant source operand
146     * @param op Opcode to be generated
147     */
148    void GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
149    /*
150     * @brief Generate a three address long operation with a constant value
151     * @param rl_dest location of result
152     * @param rl_src1 source operand
153     * @param rl_src2 constant source operand
154     * @param op Opcode to be generated
155     */
156    void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1,
157                        RegLocation rl_src2, Instruction::Code op);
158
159    /**
160      * @brief Generate a long arithmetic operation.
161      * @param rl_dest The destination.
162      * @param rl_src1 First operand.
163      * @param rl_src2 Second operand.
164      * @param op The DEX opcode for the operation.
165      * @param is_commutative The sources can be swapped if needed.
166      */
167    void GenLongArith(RegLocation rl_dest, RegLocation rl_src1,
168                      RegLocation rl_src2, Instruction::Code op, bool is_commutative);
169
170    /**
171      * @brief Generate a two operand long arithmetic operation.
172      * @param rl_dest The destination.
173      * @param rl_src Second operand.
174      * @param op The DEX opcode for the operation.
175      */
176    void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
177
178    /**
179      * @brief Generate a long operation.
180      * @param rl_dest The destination.  Must be in a register
181      * @param rl_src The other operand.  May be in a register or in memory.
182      * @param op The DEX opcode for the operation.
183      */
184    void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
185
186    /**
187     * @brief Implement instanceof a final class with x86 specific code.
188     * @param use_declaring_class 'true' if we can use the class itself.
189     * @param type_idx Type index to use if use_declaring_class is 'false'.
190     * @param rl_dest Result to be set to 0 or 1.
191     * @param rl_src Object to be tested.
192     */
193    void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx,
194                            RegLocation rl_dest, RegLocation rl_src);
195    /*
196     *
197     * @brief Implement Set up instanceof a class with x86 specific code.
198     * @param needs_access_check 'true' if we must check the access.
199     * @param type_known_final 'true' if the type is known to be a final class.
200     * @param type_known_abstract 'true' if the type is known to be an abstract class.
201     * @param use_declaring_class 'true' if the type can be loaded off the current Method*.
202     * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache.
203     * @param type_idx Type index to use if use_declaring_class is 'false'.
204     * @param rl_dest Result to be set to 0 or 1.
205     * @param rl_src Object to be tested.
206     */
207    void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final,
208                                    bool type_known_abstract, bool use_declaring_class,
209                                    bool can_assume_type_is_in_dex_cache,
210                                    uint32_t type_idx, RegLocation rl_dest,
211                                    RegLocation rl_src);
212
213    // Single operation generators.
214    LIR* OpUnconditionalBranch(LIR* target);
215    LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
216    LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
217    LIR* OpCondBranch(ConditionCode cc, LIR* target);
218    LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
219    LIR* OpFpRegCopy(int r_dest, int r_src);
220    LIR* OpIT(ConditionCode cond, const char* guide);
221    LIR* OpMem(OpKind op, int rBase, int disp);
222    LIR* OpPcRelLoad(int reg, LIR* target);
223    LIR* OpReg(OpKind op, int r_dest_src);
224    LIR* OpRegCopy(int r_dest, int r_src);
225    LIR* OpRegCopyNoInsert(int r_dest, int r_src);
226    LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
227    LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
228    LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value);
229    LIR* OpRegMem(OpKind op, int r_dest, RegLocation value);
230    LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
231    LIR* OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type);
232    LIR* OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type);
233    LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src);
234    LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
235    LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
236    LIR* OpTestSuspend(LIR* target);
237    LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
238    LIR* OpVldm(int rBase, int count);
239    LIR* OpVstm(int rBase, int count);
240    void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
241    void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
242    void OpTlsCmp(ThreadOffset offset, int val);
243
244    void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset);
245    void SpillCoreRegs();
246    void UnSpillCoreRegs();
247    static const X86EncodingMap EncodingMap[kX86Last];
248    bool InexpensiveConstantInt(int32_t value);
249    bool InexpensiveConstantFloat(int32_t value);
250    bool InexpensiveConstantLong(int64_t value);
251    bool InexpensiveConstantDouble(int64_t value);
252
253    RegLocation UpdateLocWide(RegLocation loc);
254    RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update);
255    RegLocation EvalLoc(RegLocation loc, int reg_class, bool update);
256    int AllocTempDouble();
257    void ResetDefLocWide(RegLocation rl);
258
259    /*
260     * @brief x86 specific codegen for int operations.
261     * @param opcode Operation to perform.
262     * @param rl_dest Destination for the result.
263     * @param rl_lhs Left hand operand.
264     * @param rl_rhs Right hand operand.
265     */
266    void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
267                       RegLocation rl_lhs, RegLocation rl_rhs);
268
269    /*
270     * @brief Dump a RegLocation using printf
271     * @param loc Register location to dump
272     */
273    static void DumpRegLocation(RegLocation loc);
274
275    /*
276     * @brief Load the Method* of a dex method into the register.
277     * @param target_method The MethodReference of the method to be invoked.
278     * @param type How the method will be invoked.
279     * @param register that will contain the code address.
280     * @note register will be passed to TargetReg to get physical register.
281     */
282    void LoadMethodAddress(const MethodReference& target_method, InvokeType type,
283                           SpecialTargetRegister symbolic_reg);
284
285    /*
286     * @brief Load the Class* of a Dex Class type into the register.
287     * @param type How the method will be invoked.
288     * @param register that will contain the code address.
289     * @note register will be passed to TargetReg to get physical register.
290     */
291    void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg);
292
293    /*
294     * @brief Generate a relative call to the method that will be patched at link time.
295     * @param target_method The MethodReference of the method to be invoked.
296     * @param type How the method will be invoked.
297     * @returns Call instruction
298     */
299    LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type);
300
301    /*
302     * @brief Handle x86 specific literals
303     */
304    void InstallLiteralPools();
305
306    /*
307     * @brief Generate the debug_frame CFI information.
308     * @returns pointer to vector containing CFE information
309     */
310    static std::vector<uint8_t>* ReturnCommonCallFrameInformation();
311
312    /*
313     * @brief Generate the debug_frame FDE information.
314     * @returns pointer to vector containing CFE information
315     */
316    std::vector<uint8_t>* ReturnCallFrameInformation();
317
318  private:
319    void EmitPrefix(const X86EncodingMap* entry);
320    void EmitOpcode(const X86EncodingMap* entry);
321    void EmitPrefixAndOpcode(const X86EncodingMap* entry);
322    void EmitDisp(uint8_t base, int disp);
323    void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp);
324    void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int disp);
325    void EmitImm(const X86EncodingMap* entry, int imm);
326    void EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg);
327    void EmitOpReg(const X86EncodingMap* entry, uint8_t reg);
328    void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp);
329    void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,
330                     int scale, int disp);
331    void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg);
332    void EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm);
333    void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp);
334    void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,
335                      int scale, int disp);
336    void EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,
337                      uint8_t reg);
338    void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp);
339    void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2);
340    void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm);
341    void EmitRegRegImmRev(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm);
342    void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp, int32_t imm);
343    void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
344    void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm);
345    void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
346    void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
347    void EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t cl);
348    void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl);
349    void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition);
350
351    /**
352     * @brief Used for encoding conditional register to register operation.
353     * @param entry The entry in the encoding map for the opcode.
354     * @param reg1 The first physical register.
355     * @param reg2 The second physical register.
356     * @param condition The condition code for operation.
357     */
358    void EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition);
359
360    void EmitJmp(const X86EncodingMap* entry, int rel);
361    void EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc);
362    void EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp);
363    void EmitCallImmediate(const X86EncodingMap* entry, int disp);
364    void EmitCallThread(const X86EncodingMap* entry, int disp);
365    void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index,
366                   int scale, int table_or_disp);
367    void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset);
368    void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir);
369    void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1,
370                                  int64_t val, ConditionCode ccode);
371    void OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg);
372    void GenConstWide(RegLocation rl_dest, int64_t value);
373
374    /*
375     * @brief generate inline code for fast case of Strng.indexOf.
376     * @param info Call parameters
377     * @param zero_based 'true' if the index into the string is 0.
378     * @returns 'true' if the call was inlined, 'false' if a regular call needs to be
379     * generated.
380     */
381    bool GenInlinedIndexOf(CallInfo* info, bool zero_based);
382
383    /*
384     * @brief Return the correct x86 opcode for the Dex operation
385     * @param op Dex opcode for the operation
386     * @param loc Register location of the operand
387     * @param is_high_op 'true' if this is an operation on the high word
388     * @param value Immediate value for the operation.  Used for byte variants
389     * @returns the correct x86 opcode to perform the operation
390     */
391    X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value);
392
393    /*
394     * @brief Return the correct x86 opcode for the Dex operation
395     * @param op Dex opcode for the operation
396     * @param dest location of the destination.  May be register or memory.
397     * @param rhs Location for the rhs of the operation.  May be in register or memory.
398     * @param is_high_op 'true' if this is an operation on the high word
399     * @returns the correct x86 opcode to perform the operation
400     * @note at most one location may refer to memory
401     */
402    X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs,
403                        bool is_high_op);
404
405    /*
406     * @brief Is this operation a no-op for this opcode and value
407     * @param op Dex opcode for the operation
408     * @param value Immediate value for the operation.
409     * @returns 'true' if the operation will have no effect
410     */
411    bool IsNoOp(Instruction::Code op, int32_t value);
412
413    /**
414     * @brief Calculate magic number and shift for a given divisor
415     * @param divisor divisor number for calculation
416     * @param magic hold calculated magic number
417     * @param shift hold calculated shift
418     */
419    void CalculateMagicAndShift(int divisor, int& magic, int& shift);
420
421    /*
422     * @brief Generate an integer div or rem operation.
423     * @param rl_dest Destination Location.
424     * @param rl_src1 Numerator Location.
425     * @param rl_src2 Divisor Location.
426     * @param is_div 'true' if this is a division, 'false' for a remainder.
427     * @param check_zero 'true' if an exception should be generated if the divisor is 0.
428     */
429    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
430                                  RegLocation rl_src2, bool is_div, bool check_zero);
431
432    /*
433     * @brief Generate an integer div or rem operation by a literal.
434     * @param rl_dest Destination Location.
435     * @param rl_src Numerator Location.
436     * @param lit Divisor.
437     * @param is_div 'true' if this is a division, 'false' for a remainder.
438     */
439    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div);
440
441    /*
442     * Generate code to implement long shift operations.
443     * @param opcode The DEX opcode to specify the shift type.
444     * @param rl_dest The destination.
445     * @param rl_src The value to be shifted.
446     * @param shift_amount How much to shift.
447     * @returns the RegLocation of the result.
448     */
449    RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
450                                  RegLocation rl_src, int shift_amount);
451    /*
452     * Generate an imul of a register by a constant or a better sequence.
453     * @param dest Destination Register.
454     * @param src Source Register.
455     * @param val Constant multiplier.
456     */
457    void GenImulRegImm(int dest, int src, int val);
458
459    /*
460     * Generate an imul of a memory location by a constant or a better sequence.
461     * @param dest Destination Register.
462     * @param sreg Symbolic register.
463     * @param displacement Displacement on stack of Symbolic Register.
464     * @param val Constant multiplier.
465     */
466    void GenImulMemImm(int dest, int sreg, int displacement, int val);
467
468    /*
469     * @brief Compare memory to immediate, and branch if condition true.
470     * @param cond The condition code that when true will branch to the target.
471     * @param temp_reg A temporary register that can be used if compare memory is not
472     * supported by the architecture.
473     * @param base_reg The register holding the base address.
474     * @param offset The offset from the base.
475     * @param check_value The immediate to compare to.
476     */
477    LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg,
478                           int offset, int check_value, LIR* target);
479
480    /*
481     * Can this operation be using core registers without temporaries?
482     * @param rl_lhs Left hand operand.
483     * @param rl_rhs Right hand operand.
484     * @returns 'true' if the operation can proceed without needing temporary regs.
485     */
486    bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs);
487
488    /**
489     * @brief Generates inline code for conversion of long to FP by using x87/
490     * @param rl_dest The destination of the FP.
491     * @param rl_src The source of the long.
492     * @param is_double 'true' if dealing with double, 'false' for float.
493     */
494    void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double);
495
496    /*
497     * @brief Perform MIR analysis before compiling method.
498     * @note Invokes Mir2LiR::Materialize after analysis.
499     */
500    void Materialize();
501
502    /*
503     * @brief Analyze MIR before generating code, to prepare for the code generation.
504     */
505    void AnalyzeMIR();
506
507    /*
508     * @brief Analyze one basic block.
509     * @param bb Basic block to analyze.
510     */
511    void AnalyzeBB(BasicBlock * bb);
512
513    /*
514     * @brief Analyze one extended MIR instruction
515     * @param opcode MIR instruction opcode.
516     * @param bb Basic block containing instruction.
517     * @param mir Extended instruction to analyze.
518     */
519    void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir);
520
521    /*
522     * @brief Analyze one MIR instruction
523     * @param opcode MIR instruction opcode.
524     * @param bb Basic block containing instruction.
525     * @param mir Instruction to analyze.
526     */
527    void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir);
528
529    /*
530     * @brief Analyze one MIR float/double instruction
531     * @param opcode MIR instruction opcode.
532     * @param bb Basic block containing instruction.
533     * @param mir Instruction to analyze.
534     */
535    void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir);
536
537    /*
538     * @brief Analyze one use of a double operand.
539     * @param rl_use Double RegLocation for the operand.
540     */
541    void AnalyzeDoubleUse(RegLocation rl_use);
542
543    // Information derived from analysis of MIR
544
545    // The compiler temporary for the code address of the method.
546    CompilerTemp *base_of_code_;
547
548    // Have we decided to compute a ptr to code and store in temporary VR?
549    bool store_method_addr_;
550
551    // Have we used the stored method address?
552    bool store_method_addr_used_;
553
554    // Instructions to remove if we didn't use the stored method address.
555    LIR* setup_method_address_[2];
556
557    // Instructions needing patching with Method* values.
558    GrowableArray<LIR*> method_address_insns_;
559
560    // Instructions needing patching with Class Type* values.
561    GrowableArray<LIR*> class_type_address_insns_;
562
563    // Instructions needing patching with PC relative code addresses.
564    GrowableArray<LIR*> call_method_insns_;
565
566    // Prologue decrement of stack pointer.
567    LIR* stack_decrement_;
568
569    // Epilogue increment of stack pointer.
570    LIR* stack_increment_;
571};
572
573}  // namespace art
574
575#endif  // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
576