target_x86.cc revision e19c91fdb88ff6fd4e88bc5984772dcfb1e86f80
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include <string> 18#include <inttypes.h> 19 20#include "codegen_x86.h" 21#include "dex/compiler_internals.h" 22#include "dex/quick/mir_to_lir-inl.h" 23#include "mirror/array.h" 24#include "mirror/string.h" 25#include "x86_lir.h" 26 27namespace art { 28 29// FIXME: restore "static" when usage uncovered 30/*static*/ int core_regs[] = { 31 rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI 32#ifdef TARGET_REX_SUPPORT 33 r8, r9, r10, r11, r12, r13, r14, 15 34#endif 35}; 36/*static*/ int ReservedRegs[] = {rX86_SP}; 37/*static*/ int core_temps[] = {rAX, rCX, rDX, rBX}; 38/*static*/ int FpRegs[] = { 39 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 40#ifdef TARGET_REX_SUPPORT 41 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 42#endif 43}; 44/*static*/ int fp_temps[] = { 45 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, 46#ifdef TARGET_REX_SUPPORT 47 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 48#endif 49}; 50 51RegLocation X86Mir2Lir::LocCReturn() { 52 RegLocation res = X86_LOC_C_RETURN; 53 return res; 54} 55 56RegLocation X86Mir2Lir::LocCReturnWide() { 57 RegLocation res = X86_LOC_C_RETURN_WIDE; 58 return res; 59} 60 61RegLocation X86Mir2Lir::LocCReturnFloat() { 62 RegLocation res = X86_LOC_C_RETURN_FLOAT; 63 return res; 64} 65 66RegLocation X86Mir2Lir::LocCReturnDouble() { 67 RegLocation res = X86_LOC_C_RETURN_DOUBLE; 68 return res; 69} 70 71// Return a target-dependent special register. 72int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { 73 int res = INVALID_REG; 74 switch (reg) { 75 case kSelf: res = rX86_SELF; break; 76 case kSuspend: res = rX86_SUSPEND; break; 77 case kLr: res = rX86_LR; break; 78 case kPc: res = rX86_PC; break; 79 case kSp: res = rX86_SP; break; 80 case kArg0: res = rX86_ARG0; break; 81 case kArg1: res = rX86_ARG1; break; 82 case kArg2: res = rX86_ARG2; break; 83 case kArg3: res = rX86_ARG3; break; 84 case kFArg0: res = rX86_FARG0; break; 85 case kFArg1: res = rX86_FARG1; break; 86 case kFArg2: res = rX86_FARG2; break; 87 case kFArg3: res = rX86_FARG3; break; 88 case kRet0: res = rX86_RET0; break; 89 case kRet1: res = rX86_RET1; break; 90 case kInvokeTgt: res = rX86_INVOKE_TGT; break; 91 case kHiddenArg: res = rAX; break; 92 case kHiddenFpArg: res = fr0; break; 93 case kCount: res = rX86_COUNT; break; 94 } 95 return res; 96} 97 98int X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 99 // For the 32-bit internal ABI, the first 3 arguments are passed in registers. 100 // TODO: This is not 64-bit compliant and depends on new internal ABI. 101 switch (arg_num) { 102 case 0: 103 return rX86_ARG1; 104 case 1: 105 return rX86_ARG2; 106 case 2: 107 return rX86_ARG3; 108 default: 109 return INVALID_REG; 110 } 111} 112 113// Create a double from a pair of singles. 114int X86Mir2Lir::S2d(int low_reg, int high_reg) { 115 return X86_S2D(low_reg, high_reg); 116} 117 118// Return mask to strip off fp reg flags and bias. 119uint32_t X86Mir2Lir::FpRegMask() { 120 return X86_FP_REG_MASK; 121} 122 123// True if both regs single, both core or both double. 124bool X86Mir2Lir::SameRegType(int reg1, int reg2) { 125 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2)); 126} 127 128/* 129 * Decode the register id. 130 */ 131uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { 132 uint64_t seed; 133 int shift; 134 int reg_id; 135 136 reg_id = reg & 0xf; 137 /* Double registers in x86 are just a single FP register */ 138 seed = 1; 139 /* FP register starts at bit position 16 */ 140 shift = X86_FPREG(reg) ? kX86FPReg0 : 0; 141 /* Expand the double register id into single offset */ 142 shift += reg_id; 143 return (seed << shift); 144} 145 146uint64_t X86Mir2Lir::GetPCUseDefEncoding() { 147 /* 148 * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be 149 * able to clean up some of the x86/Arm_Mips differences 150 */ 151 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; 152 return 0ULL; 153} 154 155void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { 156 DCHECK_EQ(cu_->instruction_set, kX86); 157 DCHECK(!lir->flags.use_def_invalid); 158 159 // X86-specific resource map setup here. 160 if (flags & REG_USE_SP) { 161 lir->u.m.use_mask |= ENCODE_X86_REG_SP; 162 } 163 164 if (flags & REG_DEF_SP) { 165 lir->u.m.def_mask |= ENCODE_X86_REG_SP; 166 } 167 168 if (flags & REG_DEFA) { 169 SetupRegMask(&lir->u.m.def_mask, rAX); 170 } 171 172 if (flags & REG_DEFD) { 173 SetupRegMask(&lir->u.m.def_mask, rDX); 174 } 175 if (flags & REG_USEA) { 176 SetupRegMask(&lir->u.m.use_mask, rAX); 177 } 178 179 if (flags & REG_USEC) { 180 SetupRegMask(&lir->u.m.use_mask, rCX); 181 } 182 183 if (flags & REG_USED) { 184 SetupRegMask(&lir->u.m.use_mask, rDX); 185 } 186 187 if (flags & REG_USEB) { 188 SetupRegMask(&lir->u.m.use_mask, rBX); 189 } 190 191 // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. 192 if (lir->opcode == kX86RepneScasw) { 193 SetupRegMask(&lir->u.m.use_mask, rAX); 194 SetupRegMask(&lir->u.m.use_mask, rCX); 195 SetupRegMask(&lir->u.m.use_mask, rDI); 196 SetupRegMask(&lir->u.m.def_mask, rDI); 197 } 198} 199 200/* For dumping instructions */ 201static const char* x86RegName[] = { 202 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 203 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 204}; 205 206static const char* x86CondName[] = { 207 "O", 208 "NO", 209 "B/NAE/C", 210 "NB/AE/NC", 211 "Z/EQ", 212 "NZ/NE", 213 "BE/NA", 214 "NBE/A", 215 "S", 216 "NS", 217 "P/PE", 218 "NP/PO", 219 "L/NGE", 220 "NL/GE", 221 "LE/NG", 222 "NLE/G" 223}; 224 225/* 226 * Interpret a format string and build a string no longer than size 227 * See format key in Assemble.cc. 228 */ 229std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { 230 std::string buf; 231 size_t i = 0; 232 size_t fmt_len = strlen(fmt); 233 while (i < fmt_len) { 234 if (fmt[i] != '!') { 235 buf += fmt[i]; 236 i++; 237 } else { 238 i++; 239 DCHECK_LT(i, fmt_len); 240 char operand_number_ch = fmt[i]; 241 i++; 242 if (operand_number_ch == '!') { 243 buf += "!"; 244 } else { 245 int operand_number = operand_number_ch - '0'; 246 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. 247 DCHECK_LT(i, fmt_len); 248 int operand = lir->operands[operand_number]; 249 switch (fmt[i]) { 250 case 'c': 251 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); 252 buf += x86CondName[operand]; 253 break; 254 case 'd': 255 buf += StringPrintf("%d", operand); 256 break; 257 case 'p': { 258 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); 259 buf += StringPrintf("0x%08x", tab_rec->offset); 260 break; 261 } 262 case 'r': 263 if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) { 264 int fp_reg = operand & X86_FP_REG_MASK; 265 buf += StringPrintf("xmm%d", fp_reg); 266 } else { 267 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName)); 268 buf += x86RegName[operand]; 269 } 270 break; 271 case 't': 272 buf += StringPrintf("0x%08" PRIxPTR " (L%p)", 273 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, 274 lir->target); 275 break; 276 default: 277 buf += StringPrintf("DecodeError '%c'", fmt[i]); 278 break; 279 } 280 i++; 281 } 282 } 283 } 284 return buf; 285} 286 287void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { 288 char buf[256]; 289 buf[0] = 0; 290 291 if (mask == ENCODE_ALL) { 292 strcpy(buf, "all"); 293 } else { 294 char num[8]; 295 int i; 296 297 for (i = 0; i < kX86RegEnd; i++) { 298 if (mask & (1ULL << i)) { 299 snprintf(num, arraysize(num), "%d ", i); 300 strcat(buf, num); 301 } 302 } 303 304 if (mask & ENCODE_CCODE) { 305 strcat(buf, "cc "); 306 } 307 /* Memory bits */ 308 if (x86LIR && (mask & ENCODE_DALVIK_REG)) { 309 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 310 DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), 311 (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); 312 } 313 if (mask & ENCODE_LITERAL) { 314 strcat(buf, "lit "); 315 } 316 317 if (mask & ENCODE_HEAP_REF) { 318 strcat(buf, "heap "); 319 } 320 if (mask & ENCODE_MUST_NOT_ALIAS) { 321 strcat(buf, "noalias "); 322 } 323 } 324 if (buf[0]) { 325 LOG(INFO) << prefix << ": " << buf; 326 } 327} 328 329void X86Mir2Lir::AdjustSpillMask() { 330 // Adjustment for LR spilling, x86 has no LR so nothing to do here 331 core_spill_mask_ |= (1 << rRET); 332 num_core_spills_++; 333} 334 335/* 336 * Mark a callee-save fp register as promoted. Note that 337 * vpush/vpop uses contiguous register lists so we must 338 * include any holes in the mask. Associate holes with 339 * Dalvik register INVALID_VREG (0xFFFFU). 340 */ 341void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { 342 UNIMPLEMENTED(WARNING) << "MarkPreservedSingle"; 343#if 0 344 LOG(FATAL) << "No support yet for promoted FP regs"; 345#endif 346} 347 348void X86Mir2Lir::FlushRegWide(int reg1, int reg2) { 349 RegisterInfo* info1 = GetRegInfo(reg1); 350 RegisterInfo* info2 = GetRegInfo(reg2); 351 DCHECK(info1 && info2 && info1->pair && info2->pair && 352 (info1->partner == info2->reg) && 353 (info2->partner == info1->reg)); 354 if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { 355 if (!(info1->is_temp && info2->is_temp)) { 356 /* Should not happen. If it does, there's a problem in eval_loc */ 357 LOG(FATAL) << "Long half-temp, half-promoted"; 358 } 359 360 info1->dirty = false; 361 info2->dirty = false; 362 if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg)) 363 info1 = info2; 364 int v_reg = mir_graph_->SRegToVReg(info1->s_reg); 365 StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner); 366 } 367} 368 369void X86Mir2Lir::FlushReg(int reg) { 370 RegisterInfo* info = GetRegInfo(reg); 371 if (info->live && info->dirty) { 372 info->dirty = false; 373 int v_reg = mir_graph_->SRegToVReg(info->s_reg); 374 StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord); 375 } 376} 377 378/* Give access to the target-dependent FP register encoding to common code */ 379bool X86Mir2Lir::IsFpReg(int reg) { 380 return X86_FPREG(reg); 381} 382 383/* Clobber all regs that might be used by an external C call */ 384void X86Mir2Lir::ClobberCallerSave() { 385 Clobber(rAX); 386 Clobber(rCX); 387 Clobber(rDX); 388 Clobber(rBX); 389} 390 391RegLocation X86Mir2Lir::GetReturnWideAlt() { 392 RegLocation res = LocCReturnWide(); 393 CHECK(res.low_reg == rAX); 394 CHECK(res.high_reg == rDX); 395 Clobber(rAX); 396 Clobber(rDX); 397 MarkInUse(rAX); 398 MarkInUse(rDX); 399 MarkPair(res.low_reg, res.high_reg); 400 return res; 401} 402 403RegLocation X86Mir2Lir::GetReturnAlt() { 404 RegLocation res = LocCReturn(); 405 res.low_reg = rDX; 406 Clobber(rDX); 407 MarkInUse(rDX); 408 return res; 409} 410 411/* To be used when explicitly managing register use */ 412void X86Mir2Lir::LockCallTemps() { 413 LockTemp(rX86_ARG0); 414 LockTemp(rX86_ARG1); 415 LockTemp(rX86_ARG2); 416 LockTemp(rX86_ARG3); 417} 418 419/* To be used when explicitly managing register use */ 420void X86Mir2Lir::FreeCallTemps() { 421 FreeTemp(rX86_ARG0); 422 FreeTemp(rX86_ARG1); 423 FreeTemp(rX86_ARG2); 424 FreeTemp(rX86_ARG3); 425} 426 427void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { 428#if ANDROID_SMP != 0 429 // TODO: optimize fences 430 NewLIR0(kX86Mfence); 431#endif 432} 433/* 434 * Alloc a pair of core registers, or a double. Low reg in low byte, 435 * high reg in next byte. 436 */ 437int X86Mir2Lir::AllocTypedTempPair(bool fp_hint, 438 int reg_class) { 439 int high_reg; 440 int low_reg; 441 int res = 0; 442 443 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 444 low_reg = AllocTempDouble(); 445 high_reg = low_reg; // only one allocated! 446 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); 447 return res; 448 } 449 450 low_reg = AllocTemp(); 451 high_reg = AllocTemp(); 452 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); 453 return res; 454} 455 456int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { 457 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 458 return AllocTempFloat(); 459 } 460 return AllocTemp(); 461} 462 463void X86Mir2Lir::CompilerInitializeRegAlloc() { 464 int num_regs = sizeof(core_regs)/sizeof(*core_regs); 465 int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); 466 int num_temps = sizeof(core_temps)/sizeof(*core_temps); 467 int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); 468 int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); 469 reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), 470 ArenaAllocator::kAllocRegAlloc)); 471 reg_pool_->num_core_regs = num_regs; 472 reg_pool_->core_regs = 473 static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), 474 ArenaAllocator::kAllocRegAlloc)); 475 reg_pool_->num_fp_regs = num_fp_regs; 476 reg_pool_->FPRegs = 477 static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), 478 ArenaAllocator::kAllocRegAlloc)); 479 CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); 480 CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); 481 // Keep special registers from being allocated 482 for (int i = 0; i < num_reserved; i++) { 483 MarkInUse(ReservedRegs[i]); 484 } 485 // Mark temp regs - all others not in use can be used for promotion 486 for (int i = 0; i < num_temps; i++) { 487 MarkTemp(core_temps[i]); 488 } 489 for (int i = 0; i < num_fp_temps; i++) { 490 MarkTemp(fp_temps[i]); 491 } 492} 493 494void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, 495 RegLocation rl_free) { 496 if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) && 497 (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) { 498 // No overlap, free both 499 FreeTemp(rl_free.low_reg); 500 FreeTemp(rl_free.high_reg); 501 } 502} 503 504void X86Mir2Lir::SpillCoreRegs() { 505 if (num_core_spills_ == 0) { 506 return; 507 } 508 // Spill mask not including fake return address register 509 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 510 int offset = frame_size_ - (4 * num_core_spills_); 511 for (int reg = 0; mask; mask >>= 1, reg++) { 512 if (mask & 0x1) { 513 StoreWordDisp(rX86_SP, offset, reg); 514 offset += 4; 515 } 516 } 517} 518 519void X86Mir2Lir::UnSpillCoreRegs() { 520 if (num_core_spills_ == 0) { 521 return; 522 } 523 // Spill mask not including fake return address register 524 uint32_t mask = core_spill_mask_ & ~(1 << rRET); 525 int offset = frame_size_ - (4 * num_core_spills_); 526 for (int reg = 0; mask; mask >>= 1, reg++) { 527 if (mask & 0x1) { 528 LoadWordDisp(rX86_SP, offset, reg); 529 offset += 4; 530 } 531 } 532} 533 534bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { 535 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); 536} 537 538X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 539 : Mir2Lir(cu, mir_graph, arena), 540 method_address_insns_(arena, 100, kGrowableArrayMisc), 541 class_type_address_insns_(arena, 100, kGrowableArrayMisc), 542 call_method_insns_(arena, 100, kGrowableArrayMisc) { 543 store_method_addr_used_ = false; 544 for (int i = 0; i < kX86Last; i++) { 545 if (X86Mir2Lir::EncodingMap[i].opcode != i) { 546 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name 547 << " is wrong: expecting " << i << ", seeing " 548 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); 549 } 550 } 551} 552 553Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 554 ArenaAllocator* const arena) { 555 return new X86Mir2Lir(cu, mir_graph, arena); 556} 557 558// Not used in x86 559int X86Mir2Lir::LoadHelper(ThreadOffset offset) { 560 LOG(FATAL) << "Unexpected use of LoadHelper in x86"; 561 return INVALID_REG; 562} 563 564uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { 565 DCHECK(!IsPseudoLirOp(opcode)); 566 return X86Mir2Lir::EncodingMap[opcode].flags; 567} 568 569const char* X86Mir2Lir::GetTargetInstName(int opcode) { 570 DCHECK(!IsPseudoLirOp(opcode)); 571 return X86Mir2Lir::EncodingMap[opcode].name; 572} 573 574const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { 575 DCHECK(!IsPseudoLirOp(opcode)); 576 return X86Mir2Lir::EncodingMap[opcode].fmt; 577} 578 579/* 580 * Return an updated location record with current in-register status. 581 * If the value lives in live temps, reflect that fact. No code 582 * is generated. If the live value is part of an older pair, 583 * clobber both low and high. 584 */ 585// TODO: Reunify with common code after 'pair mess' has been fixed 586RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) { 587 DCHECK(loc.wide); 588 DCHECK(CheckCorePoolSanity()); 589 if (loc.location != kLocPhysReg) { 590 DCHECK((loc.location == kLocDalvikFrame) || 591 (loc.location == kLocCompilerTemp)); 592 // Are the dalvik regs already live in physical registers? 593 RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); 594 595 // Handle FP registers specially on x86. 596 if (info_lo && IsFpReg(info_lo->reg)) { 597 bool match = true; 598 599 // We can't match a FP register with a pair of Core registers. 600 match = match && (info_lo->pair == 0); 601 602 if (match) { 603 // We can reuse;update the register usage info. 604 loc.low_reg = info_lo->reg; 605 loc.high_reg = info_lo->reg; // Play nice with existing code. 606 loc.location = kLocPhysReg; 607 loc.vec_len = kVectorLength8; 608 DCHECK(IsFpReg(loc.low_reg)); 609 return loc; 610 } 611 // We can't easily reuse; clobber and free any overlaps. 612 if (info_lo) { 613 Clobber(info_lo->reg); 614 FreeTemp(info_lo->reg); 615 if (info_lo->pair) 616 Clobber(info_lo->partner); 617 } 618 } else { 619 RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); 620 bool match = true; 621 match = match && (info_lo != NULL); 622 match = match && (info_hi != NULL); 623 // Are they both core or both FP? 624 match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); 625 // If a pair of floating point singles, are they properly aligned? 626 if (match && IsFpReg(info_lo->reg)) { 627 match &= ((info_lo->reg & 0x1) == 0); 628 match &= ((info_hi->reg - info_lo->reg) == 1); 629 } 630 // If previously used as a pair, it is the same pair? 631 if (match && (info_lo->pair || info_hi->pair)) { 632 match = (info_lo->pair == info_hi->pair); 633 match &= ((info_lo->reg == info_hi->partner) && 634 (info_hi->reg == info_lo->partner)); 635 } 636 if (match) { 637 // Can reuse - update the register usage info 638 loc.low_reg = info_lo->reg; 639 loc.high_reg = info_hi->reg; 640 loc.location = kLocPhysReg; 641 MarkPair(loc.low_reg, loc.high_reg); 642 DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); 643 return loc; 644 } 645 // Can't easily reuse - clobber and free any overlaps 646 if (info_lo) { 647 Clobber(info_lo->reg); 648 FreeTemp(info_lo->reg); 649 if (info_lo->pair) 650 Clobber(info_lo->partner); 651 } 652 if (info_hi) { 653 Clobber(info_hi->reg); 654 FreeTemp(info_hi->reg); 655 if (info_hi->pair) 656 Clobber(info_hi->partner); 657 } 658 } 659 } 660 return loc; 661} 662 663// TODO: Reunify with common code after 'pair mess' has been fixed 664RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { 665 DCHECK(loc.wide); 666 int32_t new_regs; 667 int32_t low_reg; 668 int32_t high_reg; 669 670 loc = UpdateLocWide(loc); 671 672 /* If it is already in a register, we can assume proper form. Is it the right reg class? */ 673 if (loc.location == kLocPhysReg) { 674 DCHECK_EQ(IsFpReg(loc.low_reg), loc.IsVectorScalar()); 675 if (!RegClassMatches(reg_class, loc.low_reg)) { 676 /* It is the wrong register class. Reallocate and copy. */ 677 if (!IsFpReg(loc.low_reg)) { 678 // We want this in a FP reg, and it is in core registers. 679 DCHECK(reg_class != kCoreReg); 680 // Allocate this into any FP reg, and mark it with the right size. 681 low_reg = AllocTypedTemp(true, reg_class); 682 OpVectorRegCopyWide(low_reg, loc.low_reg, loc.high_reg); 683 CopyRegInfo(low_reg, loc.low_reg); 684 Clobber(loc.low_reg); 685 Clobber(loc.high_reg); 686 loc.low_reg = low_reg; 687 loc.high_reg = low_reg; // Play nice with existing code. 688 loc.vec_len = kVectorLength8; 689 } else { 690 // The value is in a FP register, and we want it in a pair of core registers. 691 DCHECK_EQ(reg_class, kCoreReg); 692 DCHECK_EQ(loc.low_reg, loc.high_reg); 693 new_regs = AllocTypedTempPair(false, kCoreReg); // Force to core registers. 694 low_reg = new_regs & 0xff; 695 high_reg = (new_regs >> 8) & 0xff; 696 DCHECK_NE(low_reg, high_reg); 697 OpRegCopyWide(low_reg, high_reg, loc.low_reg, loc.high_reg); 698 CopyRegInfo(low_reg, loc.low_reg); 699 CopyRegInfo(high_reg, loc.high_reg); 700 Clobber(loc.low_reg); 701 Clobber(loc.high_reg); 702 loc.low_reg = low_reg; 703 loc.high_reg = high_reg; 704 MarkPair(loc.low_reg, loc.high_reg); 705 DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); 706 } 707 } 708 return loc; 709 } 710 711 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 712 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); 713 714 new_regs = AllocTypedTempPair(loc.fp, reg_class); 715 loc.low_reg = new_regs & 0xff; 716 loc.high_reg = (new_regs >> 8) & 0xff; 717 718 if (loc.low_reg == loc.high_reg) { 719 DCHECK(IsFpReg(loc.low_reg)); 720 loc.vec_len = kVectorLength8; 721 } else { 722 MarkPair(loc.low_reg, loc.high_reg); 723 } 724 if (update) { 725 loc.location = kLocPhysReg; 726 MarkLive(loc.low_reg, loc.s_reg_low); 727 if (loc.low_reg != loc.high_reg) { 728 MarkLive(loc.high_reg, GetSRegHi(loc.s_reg_low)); 729 } 730 } 731 return loc; 732} 733 734// TODO: Reunify with common code after 'pair mess' has been fixed 735RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { 736 int new_reg; 737 738 if (loc.wide) 739 return EvalLocWide(loc, reg_class, update); 740 741 loc = UpdateLoc(loc); 742 743 if (loc.location == kLocPhysReg) { 744 if (!RegClassMatches(reg_class, loc.low_reg)) { 745 /* Wrong register class. Realloc, copy and transfer ownership. */ 746 new_reg = AllocTypedTemp(loc.fp, reg_class); 747 OpRegCopy(new_reg, loc.low_reg); 748 CopyRegInfo(new_reg, loc.low_reg); 749 Clobber(loc.low_reg); 750 loc.low_reg = new_reg; 751 if (IsFpReg(loc.low_reg) && reg_class != kCoreReg) 752 loc.vec_len = kVectorLength4; 753 } 754 return loc; 755 } 756 757 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 758 759 new_reg = AllocTypedTemp(loc.fp, reg_class); 760 loc.low_reg = new_reg; 761 if (IsFpReg(loc.low_reg) && reg_class != kCoreReg) 762 loc.vec_len = kVectorLength4; 763 764 if (update) { 765 loc.location = kLocPhysReg; 766 MarkLive(loc.low_reg, loc.s_reg_low); 767 } 768 return loc; 769} 770 771int X86Mir2Lir::AllocTempDouble() { 772 // We really don't need a pair of registers. 773 return AllocTempFloat(); 774} 775 776// TODO: Reunify with common code after 'pair mess' has been fixed 777void X86Mir2Lir::ResetDefLocWide(RegLocation rl) { 778 DCHECK(rl.wide); 779 RegisterInfo* p_low = IsTemp(rl.low_reg); 780 if (IsFpReg(rl.low_reg)) { 781 // We are using only the low register. 782 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 783 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 784 } 785 ResetDef(rl.low_reg); 786 } else { 787 RegisterInfo* p_high = IsTemp(rl.high_reg); 788 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 789 DCHECK(p_low->pair); 790 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 791 } 792 if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { 793 DCHECK(p_high->pair); 794 } 795 ResetDef(rl.low_reg); 796 ResetDef(rl.high_reg); 797 } 798} 799 800void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 801 // Can we do this directly to memory? 802 rl_dest = UpdateLocWide(rl_dest); 803 if ((rl_dest.location == kLocDalvikFrame) || 804 (rl_dest.location == kLocCompilerTemp)) { 805 int32_t val_lo = Low32Bits(value); 806 int32_t val_hi = High32Bits(value); 807 int rBase = TargetReg(kSp); 808 int displacement = SRegOffset(rl_dest.s_reg_low); 809 810 LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo); 811 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, 812 false /* is_load */, true /* is64bit */); 813 store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi); 814 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, 815 false /* is_load */, true /* is64bit */); 816 return; 817 } 818 819 // Just use the standard code to do the generation. 820 Mir2Lir::GenConstWide(rl_dest, value); 821} 822 823// TODO: Merge with existing RegLocation dumper in vreg_analysis.cc 824void X86Mir2Lir::DumpRegLocation(RegLocation loc) { 825 LOG(INFO) << "location: " << loc.location << ',' 826 << (loc.wide ? " w" : " ") 827 << (loc.defined ? " D" : " ") 828 << (loc.is_const ? " c" : " ") 829 << (loc.fp ? " F" : " ") 830 << (loc.core ? " C" : " ") 831 << (loc.ref ? " r" : " ") 832 << (loc.high_word ? " h" : " ") 833 << (loc.home ? " H" : " ") 834 << " vec_len: " << loc.vec_len 835 << ", low: " << static_cast<int>(loc.low_reg) 836 << ", high: " << static_cast<int>(loc.high_reg) 837 << ", s_reg: " << loc.s_reg_low 838 << ", orig: " << loc.orig_sreg; 839} 840 841void X86Mir2Lir::Materialize() { 842 // A good place to put the analysis before starting. 843 AnalyzeMIR(); 844 845 // Now continue with regular code generation. 846 Mir2Lir::Materialize(); 847} 848 849void X86Mir2Lir::LoadMethodAddress(int dex_method_index, InvokeType type, 850 SpecialTargetRegister symbolic_reg) { 851 /* 852 * For x86, just generate a 32 bit move immediate instruction, that will be filled 853 * in at 'link time'. For now, put a unique value based on target to ensure that 854 * code deduplication works. 855 */ 856 const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index); 857 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 858 859 // Generate the move instruction with the unique pointer and save index and type. 860 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg), 861 static_cast<int>(ptr), dex_method_index, type); 862 AppendLIR(move); 863 method_address_insns_.Insert(move); 864} 865 866void X86Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { 867 /* 868 * For x86, just generate a 32 bit move immediate instruction, that will be filled 869 * in at 'link time'. For now, put a unique value based on target to ensure that 870 * code deduplication works. 871 */ 872 const DexFile::TypeId& id = cu_->dex_file->GetTypeId(type_idx); 873 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 874 875 // Generate the move instruction with the unique pointer and save index and type. 876 LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, TargetReg(symbolic_reg), 877 static_cast<int>(ptr), type_idx); 878 AppendLIR(move); 879 class_type_address_insns_.Insert(move); 880} 881 882LIR *X86Mir2Lir::CallWithLinkerFixup(int dex_method_index, InvokeType type) { 883 /* 884 * For x86, just generate a 32 bit call relative instruction, that will be filled 885 * in at 'link time'. For now, put a unique value based on target to ensure that 886 * code deduplication works. 887 */ 888 const DexFile::MethodId& id = cu_->dex_file->GetMethodId(dex_method_index); 889 uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); 890 891 // Generate the call instruction with the unique pointer and save index and type. 892 LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(ptr), dex_method_index, 893 type); 894 AppendLIR(call); 895 call_method_insns_.Insert(call); 896 return call; 897} 898 899void X86Mir2Lir::InstallLiteralPools() { 900 // These are handled differently for x86. 901 DCHECK(code_literal_list_ == nullptr); 902 DCHECK(method_literal_list_ == nullptr); 903 DCHECK(class_literal_list_ == nullptr); 904 905 // Handle the fixups for methods. 906 for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { 907 LIR* p = method_address_insns_.Get(i); 908 DCHECK_EQ(p->opcode, kX86Mov32RI); 909 uint32_t target = p->operands[2]; 910 911 // The offset to patch is the last 4 bytes of the instruction. 912 int patch_offset = p->offset + p->flags.size - 4; 913 cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, 914 cu_->method_idx, cu_->invoke_type, 915 target, static_cast<InvokeType>(p->operands[3]), 916 patch_offset); 917 } 918 919 // Handle the fixups for class types. 920 for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { 921 LIR* p = class_type_address_insns_.Get(i); 922 DCHECK_EQ(p->opcode, kX86Mov32RI); 923 uint32_t target = p->operands[2]; 924 925 // The offset to patch is the last 4 bytes of the instruction. 926 int patch_offset = p->offset + p->flags.size - 4; 927 cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, 928 cu_->method_idx, target, patch_offset); 929 } 930 931 // And now the PC-relative calls to methods. 932 for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { 933 LIR* p = call_method_insns_.Get(i); 934 DCHECK_EQ(p->opcode, kX86CallI); 935 uint32_t target = p->operands[1]; 936 937 // The offset to patch is the last 4 bytes of the instruction. 938 int patch_offset = p->offset + p->flags.size - 4; 939 cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, 940 cu_->method_idx, cu_->invoke_type, target, 941 static_cast<InvokeType>(p->operands[2]), 942 patch_offset, -4 /* offset */); 943 } 944 945 // And do the normal processing. 946 Mir2Lir::InstallLiteralPools(); 947} 948 949/* 950 * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, 951 * otherwise bails to standard library code. 952 */ 953bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 954 ClobberCallerSave(); 955 LockCallTemps(); // Using fixed registers 956 957 // EAX: 16 bit character being searched. 958 // ECX: count: number of words to be searched. 959 // EDI: String being searched. 960 // EDX: temporary during execution. 961 // EBX: temporary during execution. 962 963 RegLocation rl_obj = info->args[0]; 964 RegLocation rl_char = info->args[1]; 965 RegLocation rl_start = info->args[2]; 966 967 uint32_t char_value = 968 rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; 969 970 if (char_value > 0xFFFF) { 971 // We have to punt to the real String.indexOf. 972 return false; 973 } 974 975 // Okay, we are commited to inlining this. 976 RegLocation rl_return = GetReturn(false); 977 RegLocation rl_dest = InlineTarget(info); 978 979 // Is the string non-NULL? 980 LoadValueDirectFixed(rl_obj, rDX); 981 GenNullCheck(rl_obj.s_reg_low, rDX, info->opt_flags); 982 983 // Record that we have inlined & null checked the object. 984 info->opt_flags |= (MIR_INLINED | MIR_IGNORE_NULL_CHECK); 985 986 // Does the character fit in 16 bits? 987 LIR* launch_pad = nullptr; 988 if (rl_char.is_const) { 989 // We need the value in EAX. 990 LoadConstantNoClobber(rAX, char_value); 991 } else { 992 // Character is not a constant; compare at runtime. 993 LoadValueDirectFixed(rl_char, rAX); 994 launch_pad = RawLIR(0, kPseudoIntrinsicRetry, WrapPointer(info)); 995 intrinsic_launchpads_.Insert(launch_pad); 996 OpCmpImmBranch(kCondGt, rAX, 0xFFFF, launch_pad); 997 } 998 999 // From here down, we know that we are looking for a char that fits in 16 bits. 1000 // Location of reference to data array within the String object. 1001 int value_offset = mirror::String::ValueOffset().Int32Value(); 1002 // Location of count within the String object. 1003 int count_offset = mirror::String::CountOffset().Int32Value(); 1004 // Starting offset within data array. 1005 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 1006 // Start of char data with array_. 1007 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 1008 1009 // Character is in EAX. 1010 // Object pointer is in EDX. 1011 1012 // We need to preserve EDI, but have no spare registers, so push it on the stack. 1013 // We have to remember that all stack addresses after this are offset by sizeof(EDI). 1014 NewLIR1(kX86Push32R, rDI); 1015 1016 // Compute the number of words to search in to rCX. 1017 LoadWordDisp(rDX, count_offset, rCX); 1018 LIR *length_compare = nullptr; 1019 int start_value = 0; 1020 if (zero_based) { 1021 // We have to handle an empty string. Use special instruction JECXZ. 1022 length_compare = NewLIR0(kX86Jecxz8); 1023 } else { 1024 // We have to offset by the start index. 1025 if (rl_start.is_const) { 1026 start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); 1027 start_value = std::max(start_value, 0); 1028 1029 // Is the start > count? 1030 length_compare = OpCmpImmBranch(kCondLe, rCX, start_value, nullptr); 1031 1032 if (start_value != 0) { 1033 OpRegImm(kOpSub, rCX, start_value); 1034 } 1035 } else { 1036 // Runtime start index. 1037 rl_start = UpdateLoc(rl_start); 1038 if (rl_start.location == kLocPhysReg) { 1039 length_compare = OpCmpBranch(kCondLe, rCX, rl_start.low_reg, nullptr); 1040 OpRegReg(kOpSub, rCX, rl_start.low_reg); 1041 } else { 1042 // Compare to memory to avoid a register load. Handle pushed EDI. 1043 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1044 OpRegMem(kOpCmp, rDX, rX86_SP, displacement); 1045 length_compare = NewLIR2(kX86Jcc8, 0, kX86CondLe); 1046 OpRegMem(kOpSub, rCX, rX86_SP, displacement); 1047 } 1048 } 1049 } 1050 DCHECK(length_compare != nullptr); 1051 1052 // ECX now contains the count in words to be searched. 1053 1054 // Load the address of the string into EBX. 1055 // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. 1056 LoadWordDisp(rDX, value_offset, rDI); 1057 LoadWordDisp(rDX, offset_offset, rBX); 1058 OpLea(rBX, rDI, rBX, 1, data_offset); 1059 1060 // Now compute into EDI where the search will start. 1061 if (zero_based || rl_start.is_const) { 1062 if (start_value == 0) { 1063 OpRegCopy(rDI, rBX); 1064 } else { 1065 NewLIR3(kX86Lea32RM, rDI, rBX, 2 * start_value); 1066 } 1067 } else { 1068 if (rl_start.location == kLocPhysReg) { 1069 if (rl_start.low_reg == rDI) { 1070 // We have a slight problem here. We are already using RDI! 1071 // Grab the value from the stack. 1072 LoadWordDisp(rX86_SP, 0, rDX); 1073 OpLea(rDI, rBX, rDX, 1, 0); 1074 } else { 1075 OpLea(rDI, rBX, rl_start.low_reg, 1, 0); 1076 } 1077 } else { 1078 OpRegCopy(rDI, rBX); 1079 // Load the start index from stack, remembering that we pushed EDI. 1080 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); 1081 LoadWordDisp(rX86_SP, displacement, rDX); 1082 OpLea(rDI, rBX, rDX, 1, 0); 1083 } 1084 } 1085 1086 // EDI now contains the start of the string to be searched. 1087 // We are all prepared to do the search for the character. 1088 NewLIR0(kX86RepneScasw); 1089 1090 // Did we find a match? 1091 LIR* failed_branch = OpCondBranch(kCondNe, nullptr); 1092 1093 // yes, we matched. Compute the index of the result. 1094 // index = ((curr_ptr - orig_ptr) / 2) - 1. 1095 OpRegReg(kOpSub, rDI, rBX); 1096 OpRegImm(kOpAsr, rDI, 1); 1097 NewLIR3(kX86Lea32RM, rl_return.low_reg, rDI, -1); 1098 LIR *all_done = NewLIR1(kX86Jmp8, 0); 1099 1100 // Failed to match; return -1. 1101 LIR *not_found = NewLIR0(kPseudoTargetLabel); 1102 length_compare->target = not_found; 1103 failed_branch->target = not_found; 1104 LoadConstantNoClobber(rl_return.low_reg, -1); 1105 1106 // And join up at the end. 1107 all_done->target = NewLIR0(kPseudoTargetLabel); 1108 // Restore EDI from the stack. 1109 NewLIR1(kX86Pop32R, rDI); 1110 1111 // Out of line code returns here. 1112 if (launch_pad != nullptr) { 1113 LIR *return_point = NewLIR0(kPseudoTargetLabel); 1114 launch_pad->operands[2] = WrapPointer(return_point); 1115 } 1116 1117 StoreValue(rl_dest, rl_return); 1118 return true; 1119} 1120 1121} // namespace art 1122