assembler_arm.cc revision dc51b79e65abcdad094ccd5e5a2caf5153433d49
1a5d5cfda6239d8876937e75eba43222f639d2447Carl Shapiro// Copyright 2011 Google Inc. All Rights Reserved. 2a5d5cfda6239d8876937e75eba43222f639d2447Carl Shapiro 32c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers#include "assembler_arm.h" 42c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers 5578bbdc684db8ed68e9fedbc678669d27fa68b6eBrian Carlstrom#include "logging.h" 6578bbdc684db8ed68e9fedbc678669d27fa68b6eBrian Carlstrom#include "offsets.h" 7e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro#include "thread.h" 8578bbdc684db8ed68e9fedbc678669d27fa68b6eBrian Carlstrom#include "utils.h" 9a5d5cfda6239d8876937e75eba43222f639d2447Carl Shapiro 106b6b5f0e67ce03f38223a525612955663bc1799bCarl Shapironamespace art { 112c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersnamespace arm { 12a5d5cfda6239d8876937e75eba43222f639d2447Carl Shapiro 13a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro// Instruction encoding bits. 14a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiroenum { 15a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro H = 1 << 5, // halfword (or byte) 16a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro L = 1 << 20, // load (or store) 17a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro S = 1 << 20, // set condition code (or leave unchanged) 18a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro W = 1 << 21, // writeback base register (or leave unchanged) 19a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro A = 1 << 21, // accumulate in multiply instruction (or not) 20a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B = 1 << 22, // unsigned byte (or word) 21a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro N = 1 << 22, // long (or short) 22a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro U = 1 << 23, // positive (or negative) offset/index 23a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro P = 1 << 24, // offset/pre-indexed addressing (or post-indexed addressing) 24a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro I = 1 << 25, // immediate shifter operand (or not) 25a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 26a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B0 = 1, 27a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B1 = 1 << 1, 28a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B2 = 1 << 2, 29a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B3 = 1 << 3, 30a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B4 = 1 << 4, 31a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B5 = 1 << 5, 32a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B6 = 1 << 6, 33a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B7 = 1 << 7, 34a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B8 = 1 << 8, 35a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B9 = 1 << 9, 36a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B10 = 1 << 10, 37a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B11 = 1 << 11, 38a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B12 = 1 << 12, 39a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B16 = 1 << 16, 40a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B17 = 1 << 17, 41a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B18 = 1 << 18, 42a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B19 = 1 << 19, 43a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B20 = 1 << 20, 44a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B21 = 1 << 21, 45a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B22 = 1 << 22, 46a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B23 = 1 << 23, 47a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B24 = 1 << 24, 48a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B25 = 1 << 25, 49a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B26 = 1 << 26, 50a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 = 1 << 27, 51a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 52a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // Instruction bit masks. 53a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro RdMask = 15 << 12, // in str instruction 54a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CondMask = 15 << 28, 55a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CoprocessorMask = 15 << 8, 56a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro OpCodeMask = 15 << 21, // in data-processing instructions 57a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Imm24Mask = (1 << 24) - 1, 58a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Off12Mask = (1 << 12) - 1, 59a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 60a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // ldrex/strex register field encodings. 61a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro kLdExRnShift = 16, 62a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro kLdExRtShift = 12, 63a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro kStrExRnShift = 16, 64a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro kStrExRdShift = 12, 65a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro kStrExRtShift = 0, 66a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro}; 67a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 68a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 691f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughesstatic const char* kRegisterNames[] = { 701f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 711f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes "fp", "ip", "sp", "lr", "pc" 721f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes}; 731f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughesstd::ostream& operator<<(std::ostream& os, const Register& rhs) { 741f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes if (rhs >= R0 && rhs <= PC) { 751f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes os << kRegisterNames[rhs]; 761f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes } else { 77b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers os << "Register[" << static_cast<int>(rhs) << "]"; 781f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes } 791f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes return os; 801f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes} 811f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes 821f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes 831f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughesstd::ostream& operator<<(std::ostream& os, const SRegister& rhs) { 841f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes if (rhs >= S0 && rhs < kNumberOfSRegisters) { 85b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers os << "s" << static_cast<int>(rhs); 861f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes } else { 87b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers os << "SRegister[" << static_cast<int>(rhs) << "]"; 881f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes } 891f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes return os; 901f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes} 911f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes 921f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes 931f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughesstd::ostream& operator<<(std::ostream& os, const DRegister& rhs) { 941f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes if (rhs >= D0 && rhs < kNumberOfDRegisters) { 95b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers os << "d" << static_cast<int>(rhs); 961f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes } else { 97b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers os << "DRegister[" << static_cast<int>(rhs) << "]"; 981f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes } 991f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes return os; 1001f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes} 1011f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes 1021f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes 1031f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughesstatic const char* kConditionNames[] = { 104b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", 105b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers "LE", "AL", 1061f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes}; 1071f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughesstd::ostream& operator<<(std::ostream& os, const Condition& rhs) { 1081f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes if (rhs >= EQ && rhs <= AL) { 1091f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes os << kConditionNames[rhs]; 1101f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes } else { 111b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers os << "Condition[" << static_cast<int>(rhs) << "]"; 1121f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes } 1131f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes return os; 1141f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes} 1151f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes 1162c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Emit(int32_t value) { 117a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro AssemblerBuffer::EnsureCapacity ensured(&buffer_); 118a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro buffer_.Emit<int32_t>(value); 119a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 120a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 121a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1222c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitType01(Condition cond, 1232c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers int type, 1242c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Opcode opcode, 1252c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers int set_cc, 1262c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rn, 1272c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rd, 1282c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ShifterOperand so) { 129a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rd, kNoRegister); 130a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 131a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 132a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro type << kTypeShift | 133a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(opcode) << kOpcodeShift | 134a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro set_cc << kSShift | 135a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(rn) << kRnShift | 136a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(rd) << kRdShift | 137a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro so.encoding(); 138a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 139a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 140a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 141a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1422c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitType5(Condition cond, int offset, bool link) { 143a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 144a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 145a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5 << kTypeShift | 146a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (link ? 1 : 0) << kLinkShift; 1472c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Emit(ArmAssembler::EncodeBranchOffset(offset, encoding)); 148a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 149a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 150a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1512c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitMemOp(Condition cond, 1522c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers bool load, 1532c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers bool byte, 1542c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rd, 1552c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Address ad) { 156a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rd, kNoRegister); 157a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 158a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 159a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B26 | 160a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (load ? L : 0) | 161a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (byte ? B : 0) | 162a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rd) << kRdShift) | 163a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ad.encoding(); 164a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 165a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 166a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 167a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1682c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitMemOpAddressMode3(Condition cond, 1692c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers int32_t mode, 1702c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rd, 1712c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Address ad) { 172a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rd, kNoRegister); 173a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 174a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 175a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B22 | 176a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro mode | 177a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rd) << kRdShift) | 178a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ad.encoding3(); 179a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 180a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 181a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 182a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1832c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitMultiMemOp(Condition cond, 1842c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers BlockAddressMode am, 1852c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers bool load, 1862c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register base, 1872c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers RegList regs) { 188a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(base, kNoRegister); 189a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 190a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 191a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | 192a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro am | 193a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (load ? L : 0) | 194a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(base) << kRnShift) | 195a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro regs; 196a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 197a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 198a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 199a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2002c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitShiftImmediate(Condition cond, 2012c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Shift opcode, 2022c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rd, 2032c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rm, 2042c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ShifterOperand so) { 205a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 2061f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes CHECK_EQ(so.type(), 1U); 207a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 208a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(MOV) << kOpcodeShift | 209a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(rd) << kRdShift | 210a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro so.encoding() << kShiftImmShift | 211a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(opcode) << kShiftShift | 212a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(rm); 213a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 214a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 215a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 216a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2172c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitShiftRegister(Condition cond, 2182c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Shift opcode, 2192c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rd, 2202c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rm, 2212c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ShifterOperand so) { 222a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 2231f359b08f5ad33ae72e4073b86a9257fe1ed11e5Elliott Hughes CHECK_EQ(so.type(), 0U); 224a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 225a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(MOV) << kOpcodeShift | 226a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(rd) << kRdShift | 227a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro so.encoding() << kShiftRegisterShift | 228a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(opcode) << kShiftShift | 229a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B4 | 230a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(rm); 231a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 232a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 233a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 234a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2352c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitBranch(Condition cond, Label* label, bool link) { 236a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro if (label->IsBound()) { 237a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType5(cond, label->Position() - buffer_.Size(), link); 238a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro } else { 239a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int position = buffer_.Size(); 240a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // Use the offset field of the branch instruction for linking the sites. 241a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType5(cond, label->position_, link); 242a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro label->LinkTo(position); 243a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro } 244a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 245a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2462c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::and_(Register rd, Register rn, ShifterOperand so, 2472c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 248a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), AND, 0, rn, rd, so); 249a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 250a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 251a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2522c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::eor(Register rd, Register rn, ShifterOperand so, 2532c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 254a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), EOR, 0, rn, rd, so); 255a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 256a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 257a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2582c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::sub(Register rd, Register rn, ShifterOperand so, 2592c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 260a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), SUB, 0, rn, rd, so); 261a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 262a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2632c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::rsb(Register rd, Register rn, ShifterOperand so, 2642c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 265a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), RSB, 0, rn, rd, so); 266a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 267a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2682c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::rsbs(Register rd, Register rn, ShifterOperand so, 2692c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 270a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), RSB, 1, rn, rd, so); 271a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 272a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 273a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2742c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::add(Register rd, Register rn, ShifterOperand so, 2752c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 276a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), ADD, 0, rn, rd, so); 277a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 278a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 279a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2802c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::adds(Register rd, Register rn, ShifterOperand so, 2812c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 282a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), ADD, 1, rn, rd, so); 283a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 284a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 285a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2862c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::subs(Register rd, Register rn, ShifterOperand so, 2872c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 288a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), SUB, 1, rn, rd, so); 289a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 290a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 291a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2922c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::adc(Register rd, Register rn, ShifterOperand so, 2932c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 294a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), ADC, 0, rn, rd, so); 295a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 296a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 297a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 2982c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::sbc(Register rd, Register rn, ShifterOperand so, 2992c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 300a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), SBC, 0, rn, rd, so); 301a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 302a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 303a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3042c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::rsc(Register rd, Register rn, ShifterOperand so, 3052c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 306a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), RSC, 0, rn, rd, so); 307a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 308a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 309a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3102c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::tst(Register rn, ShifterOperand so, Condition cond) { 311a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. 312a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), TST, 1, rn, R0, so); 313a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 314a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 315a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3162c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::teq(Register rn, ShifterOperand so, Condition cond) { 317a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. 318a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), TEQ, 1, rn, R0, so); 319a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 320a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 321a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3222c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::cmp(Register rn, ShifterOperand so, Condition cond) { 323a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), CMP, 1, rn, R0, so); 324a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 325a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 326a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3272c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::cmn(Register rn, ShifterOperand so, Condition cond) { 328a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), CMN, 1, rn, R0, so); 329a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 330a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 331a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3322c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::orr(Register rd, Register rn, 333a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ShifterOperand so, Condition cond) { 334a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), ORR, 0, rn, rd, so); 335a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 336a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 337a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3382c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::orrs(Register rd, Register rn, 3392c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ShifterOperand so, Condition cond) { 340a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), ORR, 1, rn, rd, so); 341a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 342a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 343a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3442c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::mov(Register rd, ShifterOperand so, Condition cond) { 345a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), MOV, 0, R0, rd, so); 346a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 347a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 348a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3492c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::movs(Register rd, ShifterOperand so, Condition cond) { 350a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), MOV, 1, R0, rd, so); 351a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 352a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 353a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3542c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::bic(Register rd, Register rn, ShifterOperand so, 3552c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 356a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), BIC, 0, rn, rd, so); 357a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 358a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 359a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3602c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::mvn(Register rd, ShifterOperand so, Condition cond) { 361a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), MVN, 0, R0, rd, so); 362a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 363a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 364a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3652c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::mvns(Register rd, ShifterOperand so, Condition cond) { 366a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(cond, so.type(), MVN, 1, R0, rd, so); 367a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 368a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 369a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3702c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::clz(Register rd, Register rm, Condition cond) { 371a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rd, kNoRegister); 372a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rm, kNoRegister); 373a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 374a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rd, PC); 375a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rm, PC); 376a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 377a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B24 | B22 | B21 | (0xf << 16) | 378a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rd) << kRdShift) | 379a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (0xf << 8) | B4 | static_cast<int32_t>(rm); 380a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 381a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 382a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 383a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3842c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::movw(Register rd, uint16_t imm16, Condition cond) { 385a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 386a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 387a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B25 | B24 | ((imm16 >> 12) << 16) | 388a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); 389a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 390a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 391a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 392a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 3932c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::movt(Register rd, uint16_t imm16, Condition cond) { 394a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 395a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 396a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B25 | B24 | B22 | ((imm16 >> 12) << 16) | 397a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); 398a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 399a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 400a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 401a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4022c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitMulOp(Condition cond, int32_t opcode, 4032c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rd, Register rn, 4042c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rm, Register rs) { 405a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rd, kNoRegister); 406a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rn, kNoRegister); 407a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rm, kNoRegister); 408a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rs, kNoRegister); 409a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 410a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = opcode | 411a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(cond) << kConditionShift) | 412a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rn) << kRnShift) | 413a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rd) << kRdShift) | 414a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rs) << kRsShift) | 415a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B7 | B4 | 416a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rm) << kRmShift); 417a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 418a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 419a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 420a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4212c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::mul(Register rd, Register rn, Register rm, Condition cond) { 422a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // Assembler registers rd, rn, rm are encoded as rn, rm, rs. 423a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMulOp(cond, 0, R0, rd, rn, rm); 424a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 425a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 426a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4272c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::mla(Register rd, Register rn, Register rm, Register ra, 4282c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 429a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 430a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMulOp(cond, B21, ra, rd, rn, rm); 431a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 432a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 433a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4342c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::mls(Register rd, Register rn, Register rm, Register ra, 4352c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 436a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 437a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMulOp(cond, B22 | B21, ra, rd, rn, rm); 438a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 439a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 440a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4412c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::umull(Register rd_lo, Register rd_hi, Register rn, 4422c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rm, Condition cond) { 443a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 444a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm); 445a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 446a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 447a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4482c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::ldr(Register rd, Address ad, Condition cond) { 449a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOp(cond, true, false, rd, ad); 450a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 451a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 452a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4532c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::str(Register rd, Address ad, Condition cond) { 454a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOp(cond, false, false, rd, ad); 455a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 456a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 457a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4582c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::ldrb(Register rd, Address ad, Condition cond) { 459a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOp(cond, true, true, rd, ad); 460a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 461a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 462a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4632c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::strb(Register rd, Address ad, Condition cond) { 464a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOp(cond, false, true, rd, ad); 465a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 466a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 467a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4682c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::ldrh(Register rd, Address ad, Condition cond) { 469a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad); 470a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 471a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 472a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4732c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::strh(Register rd, Address ad, Condition cond) { 474a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad); 475a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 476a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 477a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4782c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::ldrsb(Register rd, Address ad, Condition cond) { 479a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad); 480a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 481a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 482a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4832c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::ldrsh(Register rd, Address ad, Condition cond) { 484a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad); 485a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 486a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 487a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4882c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::ldrd(Register rd, Address ad, Condition cond) { 489a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_EQ(rd % 2, 0); 490a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad); 491a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 492a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 493a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 4942c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::strd(Register rd, Address ad, Condition cond) { 495a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_EQ(rd % 2, 0); 496a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad); 497a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 498a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 499a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5002c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::ldm(BlockAddressMode am, 5012c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register base, 5022c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers RegList regs, 5032c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 504a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMultiMemOp(cond, am, true, base, regs); 505a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 506a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 507a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5082c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::stm(BlockAddressMode am, 5092c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register base, 5102c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers RegList regs, 5112c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 512a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitMultiMemOp(cond, am, false, base, regs); 513a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 514a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 515a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5162c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::ldrex(Register rt, Register rn, Condition cond) { 517a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rn, kNoRegister); 518a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, kNoRegister); 519a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 520a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 521a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B24 | 522a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B23 | 523a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro L | 524a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rn) << kLdExRnShift) | 525a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt) << kLdExRtShift) | 526a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0; 527a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 528a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 529a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 530a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5312c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::strex(Register rd, 5322c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rt, 5332c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register rn, 5342c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 535a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rn, kNoRegister); 536a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rd, kNoRegister); 537a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, kNoRegister); 538a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 539a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 540a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B24 | 541a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B23 | 542a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rn) << kStrExRnShift) | 543a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rd) << kStrExRdShift) | 544a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B11 | B10 | B9 | B8 | B7 | B4 | 545a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt) << kStrExRtShift); 546a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 547a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 548a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 549a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5502c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::clrex() { 551a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (kSpecialCondition << kConditionShift) | 552a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf; 553a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 554a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 555a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 556a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5572c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::nop(Condition cond) { 558a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 559a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 560a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B25 | B24 | B21 | (0xf << 12); 561a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 562a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 563a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 564a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5652c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmovsr(SRegister sn, Register rt, Condition cond) { 566a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sn, kNoSRegister); 567a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, kNoRegister); 568a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, SP); 569a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, PC); 570a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 571a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 572a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B25 | 573a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sn) >> 1)*B16) | 574a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt)*B12) | B11 | B9 | 575a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sn) & 1)*B7) | B4; 576a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 577a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 578a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 579a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5802c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmovrs(Register rt, SRegister sn, Condition cond) { 581a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sn, kNoSRegister); 582a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, kNoRegister); 583a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, SP); 584a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, PC); 585a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 586a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 587a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B25 | B20 | 588a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sn) >> 1)*B16) | 589a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt)*B12) | B11 | B9 | 590a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sn) & 1)*B7) | B4; 591a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 592a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 593a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 594a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 5952c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmovsrr(SRegister sm, Register rt, Register rt2, 5962c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 597a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sm, kNoSRegister); 598a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sm, S31); 599a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, kNoRegister); 600a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, SP); 601a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, PC); 602a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, kNoRegister); 603a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, SP); 604a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, PC); 605a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 606a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 607a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B22 | 608a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt2)*B16) | 609a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt)*B12) | B11 | B9 | 610a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sm) & 1)*B5) | B4 | 611a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(sm) >> 1); 612a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 613a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 614a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 615a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 6162c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmovrrs(Register rt, Register rt2, SRegister sm, 6172c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 618a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sm, kNoSRegister); 619a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sm, S31); 620a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, kNoRegister); 621a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, SP); 622a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, PC); 623a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, kNoRegister); 624a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, SP); 625a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, PC); 626a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, rt2); 627a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 628a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 629a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B22 | B20 | 630a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt2)*B16) | 631a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt)*B12) | B11 | B9 | 632a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sm) & 1)*B5) | B4 | 633a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(sm) >> 1); 634a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 635a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 636a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 637a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 6382c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmovdrr(DRegister dm, Register rt, Register rt2, 6392c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 640a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(dm, kNoDRegister); 641a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, kNoRegister); 642a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, SP); 643a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, PC); 644a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, kNoRegister); 645a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, SP); 646a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, PC); 647a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 648a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 649a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B22 | 650a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt2)*B16) | 651a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | 652a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | 653a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(dm) & 0xf); 654a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 655a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 656a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 657a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 6582c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmovrrd(Register rt, Register rt2, DRegister dm, 6592c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 660a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(dm, kNoDRegister); 661a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, kNoRegister); 662a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, SP); 663a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, PC); 664a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, kNoRegister); 665a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, SP); 666a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt2, PC); 667a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rt, rt2); 668a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 669a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 670a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B22 | B20 | 671a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt2)*B16) | 672a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | 673a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | 674a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(dm) & 0xf); 675a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 676a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 677a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 678a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 6792c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vldrs(SRegister sd, Address ad, Condition cond) { 680a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sd, kNoSRegister); 681a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 682a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 683a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B24 | B20 | 684a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sd) & 1)*B22) | 685a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sd) >> 1)*B12) | 686a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B11 | B9 | ad.vencoding(); 687a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 688a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 689a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 690a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 6912c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vstrs(SRegister sd, Address ad, Condition cond) { 692a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)), PC); 693a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sd, kNoSRegister); 694a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 695a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 696a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B24 | 697a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sd) & 1)*B22) | 698a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sd) >> 1)*B12) | 699a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B11 | B9 | ad.vencoding(); 700a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 701a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 702a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 703a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 7042c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vldrd(DRegister dd, Address ad, Condition cond) { 705a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(dd, kNoDRegister); 706a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 707a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 708a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B24 | B20 | 709a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dd) >> 4)*B22) | 710a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dd) & 0xf)*B12) | 711a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B11 | B9 | B8 | ad.vencoding(); 712a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 713a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 714a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 715a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 7162c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vstrd(DRegister dd, Address ad, Condition cond) { 717a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)), PC); 718a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(dd, kNoDRegister); 719a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 720a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 721a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B24 | 722a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dd) >> 4)*B22) | 723a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dd) & 0xf)*B12) | 724a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B11 | B9 | B8 | ad.vencoding(); 725a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 726a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 727a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 728a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 7292c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitVFPsss(Condition cond, int32_t opcode, 7302c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers SRegister sd, SRegister sn, SRegister sm) { 731a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sd, kNoSRegister); 732a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sn, kNoSRegister); 733a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sm, kNoSRegister); 734a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 735a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 736a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B25 | B11 | B9 | opcode | 737a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sd) & 1)*B22) | 738a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sn) >> 1)*B16) | 739a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sd) >> 1)*B12) | 740a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sn) & 1)*B7) | 741a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sm) & 1)*B5) | 742a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(sm) >> 1); 743a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 744a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 745a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 746a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 7472c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitVFPddd(Condition cond, int32_t opcode, 7482c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers DRegister dd, DRegister dn, DRegister dm) { 749a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(dd, kNoDRegister); 750a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(dn, kNoDRegister); 751a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(dm, kNoDRegister); 752a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 753a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 754a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B25 | B11 | B9 | B8 | opcode | 755a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dd) >> 4)*B22) | 756a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dn) & 0xf)*B16) | 757a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dd) & 0xf)*B12) | 758a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dn) >> 4)*B7) | 759a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dm) >> 4)*B5) | 760a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(dm) & 0xf); 761a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 762a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 763a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 764a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 7652c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmovs(SRegister sd, SRegister sm, Condition cond) { 766a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm); 767a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 768a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 769a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 7702c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmovd(DRegister dd, DRegister dm, Condition cond) { 771a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm); 772a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 773a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 774a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 7752c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersbool ArmAssembler::vmovs(SRegister sd, float s_imm, Condition cond) { 776a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro uint32_t imm32 = bit_cast<uint32_t, float>(s_imm); 777a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro if (((imm32 & ((1 << 19) - 1)) == 0) && 778a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) || 779a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) -1)))) { 780a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro uint8_t imm8 = ((imm32 >> 31) << 7) | (((imm32 >> 29) & 1) << 6) | 781a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((imm32 >> 19) & ((1 << 6) -1)); 782a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf), 783a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro sd, S0, S0); 784a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro return true; 785a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro } 786a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro return false; 787a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 788a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 789a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 7902c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersbool ArmAssembler::vmovd(DRegister dd, double d_imm, Condition cond) { 791a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro uint64_t imm64 = bit_cast<uint64_t, double>(d_imm); 792a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro if (((imm64 & ((1LL << 48) - 1)) == 0) && 793a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) || 794a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) -1)))) { 795a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro uint8_t imm8 = ((imm64 >> 63) << 7) | (((imm64 >> 61) & 1) << 6) | 796a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((imm64 >> 48) & ((1 << 6) -1)); 797a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf), 798a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro dd, D0, D0); 799a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro return true; 800a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro } 801a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro return false; 802a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 803a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 804a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8052c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vadds(SRegister sd, SRegister sn, SRegister sm, 8062c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 807a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B21 | B20, sd, sn, sm); 808a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 809a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 810a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8112c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vaddd(DRegister dd, DRegister dn, DRegister dm, 8122c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 813a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B21 | B20, dd, dn, dm); 814a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 815a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 816a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8172c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vsubs(SRegister sd, SRegister sn, SRegister sm, 8182c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 819a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm); 820a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 821a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 822a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8232c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vsubd(DRegister dd, DRegister dn, DRegister dm, 8242c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 825a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm); 826a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 827a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 828a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8292c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmuls(SRegister sd, SRegister sn, SRegister sm, 8302c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 831a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B21, sd, sn, sm); 832a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 833a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 834a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8352c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmuld(DRegister dd, DRegister dn, DRegister dm, 8362c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 837a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B21, dd, dn, dm); 838a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 839a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 840a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8412c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmlas(SRegister sd, SRegister sn, SRegister sm, 8422c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 843a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, 0, sd, sn, sm); 844a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 845a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 846a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8472c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmlad(DRegister dd, DRegister dn, DRegister dm, 8482c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 849a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, 0, dd, dn, dm); 850a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 851a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 852a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8532c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmlss(SRegister sd, SRegister sn, SRegister sm, 8542c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 855a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B6, sd, sn, sm); 856a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 857a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 858a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8592c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmlsd(DRegister dd, DRegister dn, DRegister dm, 8602c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 861a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B6, dd, dn, dm); 862a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 863a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 864a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8652c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vdivs(SRegister sd, SRegister sn, SRegister sm, 8662c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 867a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23, sd, sn, sm); 868a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 869a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 870a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8712c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vdivd(DRegister dd, DRegister dn, DRegister dm, 8722c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 873a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B23, dd, dn, dm); 874a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 875a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 876a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8772c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vabss(SRegister sd, SRegister sm, Condition cond) { 878a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm); 879a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 880a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 881a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8822c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vabsd(DRegister dd, DRegister dm, Condition cond) { 883a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm); 884a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 885a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 886a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8872c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vnegs(SRegister sd, SRegister sm, Condition cond) { 888a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm); 889a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 890a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 891a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8922c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vnegd(DRegister dd, DRegister dm, Condition cond) { 893a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm); 894a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 895a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 896a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 8972c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vsqrts(SRegister sd, SRegister sm, Condition cond) { 898a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm); 899a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 900a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9012c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) { 902a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm); 903a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 904a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 905a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9062c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitVFPsd(Condition cond, int32_t opcode, 9072c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers SRegister sd, DRegister dm) { 908a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sd, kNoSRegister); 909a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(dm, kNoDRegister); 910a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 911a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 912a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B25 | B11 | B9 | opcode | 913a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sd) & 1)*B22) | 914a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sd) >> 1)*B12) | 915a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dm) >> 4)*B5) | 916a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(dm) & 0xf); 917a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 918a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 919a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 920a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9212c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EmitVFPds(Condition cond, int32_t opcode, 9222c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers DRegister dd, SRegister sm) { 923a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(dd, kNoDRegister); 924a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(sm, kNoSRegister); 925a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 926a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 927a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B25 | B11 | B9 | opcode | 928a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dd) >> 4)*B22) | 929a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(dd) & 0xf)*B12) | 930a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((static_cast<int32_t>(sm) & 1)*B5) | 931a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(sm) >> 1); 932a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 933a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 934a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 935a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9362c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) { 937a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm); 938a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 939a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 940a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9412c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtds(DRegister dd, SRegister sm, Condition cond) { 942a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm); 943a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 944a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 945a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9462c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtis(SRegister sd, SRegister sm, Condition cond) { 947a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); 948a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 949a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 950a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9512c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtid(SRegister sd, DRegister dm, Condition cond) { 952a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm); 953a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 954a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 955a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9562c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) { 957a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); 958a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 959a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 960a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9612c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) { 962a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm); 963a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 964a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 965a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9662c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtus(SRegister sd, SRegister sm, Condition cond) { 967a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); 968a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 969a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 970a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9712c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtud(SRegister sd, DRegister dm, Condition cond) { 972a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm); 973a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 974a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 975a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9762c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) { 977a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm); 978a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 979a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 980a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9812c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) { 982a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm); 983a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 984a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 985a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9862c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcmps(SRegister sd, SRegister sm, Condition cond) { 987a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm); 988a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 989a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 990a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9912c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcmpd(DRegister dd, DRegister dm, Condition cond) { 992a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm); 993a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 994a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 995a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 9962c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcmpsz(SRegister sd, Condition cond) { 997a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0); 998a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 999a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1000a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10012c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vcmpdz(DRegister dd, Condition cond) { 1002a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0); 1003a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1004a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1005a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10062c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::vmstat(Condition cond) { // VMRS APSR_nzcv, FPSCR 1007a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 1008a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 1009a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | 1010a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(PC)*B12) | 1011a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B11 | B9 | B4; 1012a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 1013a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1014a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1015a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10162c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::svc(uint32_t imm24) { 1017a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK(IsUint(24, imm24)); 1018a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (AL << kConditionShift) | B27 | B26 | B25 | B24 | imm24; 1019a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 1020a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1021a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1022a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10232c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::bkpt(uint16_t imm16) { 1024a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (AL << kConditionShift) | B24 | B21 | 1025a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf); 1026a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 1027a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1028a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1029a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10302c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::b(Label* label, Condition cond) { 1031a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitBranch(cond, label, false); 1032a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1033a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1034a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10352c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::bl(Label* label, Condition cond) { 1036a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitBranch(cond, label, true); 1037a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1038a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1039a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10402c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::blx(Register rm, Condition cond) { 1041a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(rm, kNoRegister); 1042a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK_NE(cond, kNoCondition); 1043a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 1044a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro B24 | B21 | (0xfff << 8) | B5 | B4 | 1045a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro (static_cast<int32_t>(rm) << kRmShift); 1046a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Emit(encoding); 1047a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1048a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1049a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10502c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::MarkExceptionHandler(Label* label) { 1051a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0)); 1052a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Label l; 1053a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro b(&l); 1054a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro EmitBranch(AL, label, false); 1055a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro Bind(&l); 1056a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1057a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1058a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10592c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Bind(Label* label) { 1060a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK(!label->IsBound()); 1061a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int bound_pc = buffer_.Size(); 1062a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro while (label->IsLinked()) { 1063a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t position = label->Position(); 1064a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro int32_t next = buffer_.Load<int32_t>(position); 10652c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers int32_t encoded = ArmAssembler::EncodeBranchOffset(bound_pc - position, next); 1066a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro buffer_.Store<int32_t>(position, encoded); 10672c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers label->position_ = ArmAssembler::DecodeBranchOffset(next); 1068a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro } 1069a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro label->BindTo(bound_pc); 1070a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1071a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1072a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10732c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::EncodeUint32InTstInstructions(uint32_t data) { 1074a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // TODO: Consider using movw ip, <16 bits>. 1075a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro while (!IsUint(8, data)) { 1076a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro tst(R0, ShifterOperand(data & 0xFF), VS); 1077a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro data >>= 8; 1078a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro } 1079a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro tst(R0, ShifterOperand(data), MI); 1080a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1081a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1082b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 10832c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersint32_t ArmAssembler::EncodeBranchOffset(int offset, int32_t inst) { 1084a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // The offset is off by 8 due to the way the ARM CPUs read PC. 1085a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro offset -= 8; 1086a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK(IsAligned(offset, 4)); 1087a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro CHECK(IsInt(CountOneBits(kBranchOffsetMask), offset)); 1088a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1089a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // Properly preserve only the bits supported in the instruction. 1090a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro offset >>= 2; 1091a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro offset &= kBranchOffsetMask; 1092a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro return (inst & ~kBranchOffsetMask) | offset; 1093a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1094a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 1095a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 10962c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersint ArmAssembler::DecodeBranchOffset(int32_t inst) { 1097a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro // Sign-extend, left-shift by 2, then add 8. 1098a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro return ((((inst & kBranchOffsetMask) << 8) >> 6) + 8); 1099a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro} 1100a2e18e1e77fc25c8260aad5daa267ababfcb65f6Carl Shapiro 11012c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::AddConstant(Register rd, int32_t value, Condition cond) { 1102b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers AddConstant(rd, rd, value, cond); 1103b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1104b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1105b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 11062c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::AddConstant(Register rd, Register rn, int32_t value, 11072c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 1108b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (value == 0) { 1109b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (rd != rn) { 1110b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers mov(rd, ShifterOperand(rn), cond); 1111b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1112b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers return; 1113b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1114b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers // We prefer to select the shorter code sequence rather than selecting add for 1115b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers // positive values and sub for negatives ones, which would slightly improve 1116b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers // the readability of generated code for some constants. 1117b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers ShifterOperand shifter_op; 1118b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (ShifterOperand::CanHold(value, &shifter_op)) { 1119b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers add(rd, rn, shifter_op, cond); 1120b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else if (ShifterOperand::CanHold(-value, &shifter_op)) { 1121b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers sub(rd, rn, shifter_op, cond); 1122b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else { 1123b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(rn != IP); 1124b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (ShifterOperand::CanHold(~value, &shifter_op)) { 1125b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers mvn(IP, shifter_op, cond); 1126b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers add(rd, rn, ShifterOperand(IP), cond); 1127b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) { 1128b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers mvn(IP, shifter_op, cond); 1129b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers sub(rd, rn, ShifterOperand(IP), cond); 1130b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else { 1131b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers movw(IP, Low16Bits(value), cond); 1132b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers uint16_t value_high = High16Bits(value); 1133b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (value_high != 0) { 1134b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers movt(IP, value_high, cond); 1135b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1136b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers add(rd, rn, ShifterOperand(IP), cond); 1137b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1138b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1139b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1140b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1141b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 11422c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::AddConstantSetFlags(Register rd, Register rn, int32_t value, 11432c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 1144b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers ShifterOperand shifter_op; 1145b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (ShifterOperand::CanHold(value, &shifter_op)) { 1146b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers adds(rd, rn, shifter_op, cond); 1147b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else if (ShifterOperand::CanHold(-value, &shifter_op)) { 1148b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers subs(rd, rn, shifter_op, cond); 1149b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else { 1150b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(rn != IP); 1151b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (ShifterOperand::CanHold(~value, &shifter_op)) { 1152b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers mvn(IP, shifter_op, cond); 1153b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers adds(rd, rn, ShifterOperand(IP), cond); 1154b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) { 1155b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers mvn(IP, shifter_op, cond); 1156b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers subs(rd, rn, ShifterOperand(IP), cond); 1157b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else { 1158b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers movw(IP, Low16Bits(value), cond); 1159b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers uint16_t value_high = High16Bits(value); 1160b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (value_high != 0) { 1161b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers movt(IP, value_high, cond); 1162b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1163b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers adds(rd, rn, ShifterOperand(IP), cond); 1164b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1165b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1166b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1167b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1168b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 11692c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::LoadImmediate(Register rd, int32_t value, Condition cond) { 1170b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers ShifterOperand shifter_op; 1171b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (ShifterOperand::CanHold(value, &shifter_op)) { 1172b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers mov(rd, shifter_op, cond); 1173b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else if (ShifterOperand::CanHold(~value, &shifter_op)) { 1174b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers mvn(rd, shifter_op, cond); 1175b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else { 1176b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers movw(rd, Low16Bits(value), cond); 1177b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers uint16_t value_high = High16Bits(value); 1178b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (value_high != 0) { 1179b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers movt(rd, value_high, cond); 1180b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1181b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1182b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1183b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1184b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1185b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogersbool Address::CanHoldLoadOffset(LoadOperandType type, int offset) { 1186b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers switch (type) { 1187b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadSignedByte: 1188b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadSignedHalfword: 1189b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadUnsignedHalfword: 1190b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadWordPair: 1191b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers return IsAbsoluteUint(8, offset); // Addressing mode 3. 1192b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadUnsignedByte: 1193b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadWord: 1194b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers return IsAbsoluteUint(12, offset); // Addressing mode 2. 1195b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadSWord: 1196b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadDWord: 1197b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers return IsAbsoluteUint(10, offset); // VFP addressing mode. 1198b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers default: 1199b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LOG(FATAL) << "UNREACHABLE"; 1200b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers return false; 1201b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1202b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1203b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1204b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1205b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogersbool Address::CanHoldStoreOffset(StoreOperandType type, int offset) { 1206b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers switch (type) { 1207b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreHalfword: 1208b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreWordPair: 1209b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers return IsAbsoluteUint(8, offset); // Addressing mode 3. 1210b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreByte: 1211b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreWord: 1212b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers return IsAbsoluteUint(12, offset); // Addressing mode 2. 1213b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreSWord: 1214b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreDWord: 1215b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers return IsAbsoluteUint(10, offset); // VFP addressing mode. 1216b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers default: 1217b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LOG(FATAL) << "UNREACHABLE"; 1218b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers return false; 1219b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1220b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1221b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1222b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1223b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers// Implementation note: this method must emit at most one instruction when 1224b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers// Address::CanHoldLoadOffset. 12252c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::LoadFromOffset(LoadOperandType type, 1226b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers Register reg, 1227b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers Register base, 1228b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers int32_t offset, 1229b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers Condition cond) { 1230b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (!Address::CanHoldLoadOffset(type, offset)) { 1231b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(base != IP); 1232b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadImmediate(IP, offset, cond); 1233b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers add(IP, IP, ShifterOperand(base), cond); 1234b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers base = IP; 1235b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers offset = 0; 1236b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1237b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(Address::CanHoldLoadOffset(type, offset)); 1238b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers switch (type) { 1239b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadSignedByte: 1240b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers ldrsb(reg, Address(base, offset), cond); 1241b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1242b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadUnsignedByte: 1243b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers ldrb(reg, Address(base, offset), cond); 1244b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1245b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadSignedHalfword: 1246b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers ldrsh(reg, Address(base, offset), cond); 1247b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1248b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadUnsignedHalfword: 1249b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers ldrh(reg, Address(base, offset), cond); 1250b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1251b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadWord: 1252b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers ldr(reg, Address(base, offset), cond); 1253b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1254b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kLoadWordPair: 1255b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers ldrd(reg, Address(base, offset), cond); 1256b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1257b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers default: 1258b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LOG(FATAL) << "UNREACHABLE"; 1259b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1260b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1261b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1262e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro// Implementation note: this method must emit at most one instruction when 1263e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro// Address::CanHoldLoadOffset, as expected by JIT::GuardedLoadFromOffset. 12642c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::LoadSFromOffset(SRegister reg, 12652c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register base, 12662c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers int32_t offset, 12672c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 1268e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro if (!Address::CanHoldLoadOffset(kLoadSWord, offset)) { 1269e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK_NE(base, IP); 1270e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadImmediate(IP, offset, cond); 1271e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro add(IP, IP, ShifterOperand(base), cond); 1272e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro base = IP; 1273e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro offset = 0; 1274e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } 1275e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK(Address::CanHoldLoadOffset(kLoadSWord, offset)); 1276e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro vldrs(reg, Address(base, offset), cond); 1277e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro} 1278e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro 1279e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro// Implementation note: this method must emit at most one instruction when 1280e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro// Address::CanHoldLoadOffset, as expected by JIT::GuardedLoadFromOffset. 12812c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::LoadDFromOffset(DRegister reg, 12822c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register base, 12832c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers int32_t offset, 12842c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 1285e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro if (!Address::CanHoldLoadOffset(kLoadDWord, offset)) { 1286e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK_NE(base, IP); 1287e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadImmediate(IP, offset, cond); 1288e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro add(IP, IP, ShifterOperand(base), cond); 1289e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro base = IP; 1290e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro offset = 0; 1291e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } 1292e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK(Address::CanHoldLoadOffset(kLoadDWord, offset)); 1293e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro vldrd(reg, Address(base, offset), cond); 1294e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro} 1295b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1296b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers// Implementation note: this method must emit at most one instruction when 1297b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers// Address::CanHoldStoreOffset. 12982c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreToOffset(StoreOperandType type, 12992c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register reg, 13002c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register base, 13012c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers int32_t offset, 13022c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 1303b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (!Address::CanHoldStoreOffset(type, offset)) { 1304b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(reg != IP); 1305b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(base != IP); 1306b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadImmediate(IP, offset, cond); 1307b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers add(IP, IP, ShifterOperand(base), cond); 1308b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers base = IP; 1309b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers offset = 0; 1310b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1311b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(Address::CanHoldStoreOffset(type, offset)); 1312b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers switch (type) { 1313b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreByte: 1314b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers strb(reg, Address(base, offset), cond); 1315b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1316b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreHalfword: 1317b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers strh(reg, Address(base, offset), cond); 1318b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1319b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreWord: 1320b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers str(reg, Address(base, offset), cond); 1321b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1322b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers case kStoreWordPair: 1323b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers strd(reg, Address(base, offset), cond); 1324b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers break; 1325b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers default: 1326b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LOG(FATAL) << "UNREACHABLE"; 1327b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1328b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1329b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1330e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro// Implementation note: this method must emit at most one instruction when 1331e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro// Address::CanHoldStoreOffset, as expected by JIT::GuardedStoreToOffset. 13322c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreSToOffset(SRegister reg, 13332c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register base, 13342c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers int32_t offset, 13352c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 1336e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro if (!Address::CanHoldStoreOffset(kStoreSWord, offset)) { 1337e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK_NE(base, IP); 1338e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadImmediate(IP, offset, cond); 1339e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro add(IP, IP, ShifterOperand(base), cond); 1340e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro base = IP; 1341e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro offset = 0; 1342e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } 1343e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK(Address::CanHoldStoreOffset(kStoreSWord, offset)); 1344e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro vstrs(reg, Address(base, offset), cond); 1345e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro} 1346e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro 1347e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro// Implementation note: this method must emit at most one instruction when 1348e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro// Address::CanHoldStoreOffset, as expected by JIT::GuardedStoreSToOffset. 13492c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreDToOffset(DRegister reg, 13502c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Register base, 13512c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers int32_t offset, 13522c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 1353e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro if (!Address::CanHoldStoreOffset(kStoreDWord, offset)) { 1354e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK_NE(base, IP); 1355e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadImmediate(IP, offset, cond); 1356e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro add(IP, IP, ShifterOperand(base), cond); 1357e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro base = IP; 1358e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro offset = 0; 1359e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } 1360e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK(Address::CanHoldStoreOffset(kStoreDWord, offset)); 1361e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro vstrd(reg, Address(base, offset), cond); 1362e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro} 1363e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro 13642c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Push(Register rd, Condition cond) { 13659b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond); 13669b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 13679b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 13682c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Pop(Register rd, Condition cond) { 13699b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond); 13709b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 13719b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 13722c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::PushList(RegList regs, Condition cond) { 13739b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro stm(DB_W, SP, regs, cond); 13749b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 13759b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 13762c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::PopList(RegList regs, Condition cond) { 13779b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro ldm(IA_W, SP, regs, cond); 13789b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 13799b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 13802c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Mov(Register rd, Register rm, Condition cond) { 13819b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro if (rd != rm) { 13829b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro mov(rd, ShifterOperand(rm), cond); 13839b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro } 13849b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 13859b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 13862c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Lsl(Register rd, Register rm, uint32_t shift_imm, 13872c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 13889b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro CHECK_NE(shift_imm, 0u); // Do not use Lsl if no shift is wanted. 13899b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro mov(rd, ShifterOperand(rm, LSL, shift_imm), cond); 13909b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 13919b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 13922c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Lsr(Register rd, Register rm, uint32_t shift_imm, 13932c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 13949b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro CHECK_NE(shift_imm, 0u); // Do not use Lsr if no shift is wanted. 13959b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. 13969b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro mov(rd, ShifterOperand(rm, LSR, shift_imm), cond); 13979b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 13989b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 13992c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Asr(Register rd, Register rm, uint32_t shift_imm, 14002c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 14019b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro CHECK_NE(shift_imm, 0u); // Do not use Asr if no shift is wanted. 14029b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. 14039b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro mov(rd, ShifterOperand(rm, ASR, shift_imm), cond); 14049b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 14059b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 14062c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Ror(Register rd, Register rm, uint32_t shift_imm, 14072c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers Condition cond) { 14089b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro CHECK_NE(shift_imm, 0u); // Use Rrx instruction. 14099b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro mov(rd, ShifterOperand(rm, ROR, shift_imm), cond); 14109b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 14119b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 14122c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Rrx(Register rd, Register rm, Condition cond) { 14139b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro mov(rd, ShifterOperand(rm, ROR, 0), cond); 14149b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro} 14159b9ba28b1277b4ddb967c5a968c6d550febce6afCarl Shapiro 14162c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, 1417bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers const std::vector<ManagedRegister>& callee_save_regs) { 14180d666d8769714dcbc2acc4dd5b06f0deffa6e0a1Ian Rogers CHECK(IsAligned(frame_size, kStackAlignment)); 14192c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers CHECK_EQ(R0, method_reg.AsArm().AsCoreRegister()); 1420bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers 1421bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers // Push callee saves and link register 1422bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers RegList push_list = 1 << LR; 1423bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers size_t pushed_values = 1; 1424bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers for (size_t i = 0; i < callee_save_regs.size(); i++) { 1425bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers Register reg = callee_save_regs.at(i).AsArm().AsCoreRegister(); 1426bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers push_list |= 1 << reg; 1427bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers pushed_values++; 14280d666d8769714dcbc2acc4dd5b06f0deffa6e0a1Ian Rogers } 1429bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers PushList(push_list); 1430bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers 1431bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers // Increase frame to required size 1432bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers CHECK_GT(frame_size, pushed_values * kPointerSize); // Must be at least space to push Method* 1433bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers size_t adjust = frame_size - (pushed_values * kPointerSize); 1434bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers IncreaseFrameSize(adjust); 1435bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers 1436bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers // Write out Method* 1437bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers StoreToOffset(kStoreWord, R0, SP, 0); 1438b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1439b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 14402c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::RemoveFrame(size_t frame_size, 1441bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers const std::vector<ManagedRegister>& callee_save_regs) { 14420d666d8769714dcbc2acc4dd5b06f0deffa6e0a1Ian Rogers CHECK(IsAligned(frame_size, kStackAlignment)); 1443bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers // Compute callee saves to pop and PC 1444bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers RegList pop_list = 1 << PC; 1445bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers size_t pop_values = 1; 1446bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers for (size_t i = 0; i < callee_save_regs.size(); i++) { 1447bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers Register reg = callee_save_regs.at(i).AsArm().AsCoreRegister(); 1448bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers pop_list |= 1 << reg; 1449bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers pop_values++; 14500d666d8769714dcbc2acc4dd5b06f0deffa6e0a1Ian Rogers } 1451bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers 1452bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers // Decrease frame to start of callee saves 1453bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers CHECK_GT(frame_size, pop_values * kPointerSize); 1454bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers size_t adjust = frame_size - (pop_values * kPointerSize); 1455bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers DecreaseFrameSize(adjust); 1456bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers 1457bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers // Pop callee saves and PC 1458bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers PopList(pop_list); 14590d666d8769714dcbc2acc4dd5b06f0deffa6e0a1Ian Rogers} 14600d666d8769714dcbc2acc4dd5b06f0deffa6e0a1Ian Rogers 14612c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::IncreaseFrameSize(size_t adjust) { 1462b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers AddConstant(SP, -adjust); 1463b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1464b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 14652c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::DecreaseFrameSize(size_t adjust) { 1466b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers AddConstant(SP, adjust); 1467b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1468b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 14692c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) { 14702c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister src = msrc.AsArm(); 1471e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro if (src.IsNoRegister()) { 1472e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK_EQ(0u, size); 1473e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } else if (src.IsCoreRegister()) { 1474b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK_EQ(4u, size); 1475b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 1476e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } else if (src.IsRegisterPair()) { 1477e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK_EQ(8u, size); 1478e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value()); 1479e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro StoreToOffset(kStoreWord, src.AsRegisterPairHigh(), 1480e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro SP, dest.Int32Value() + 4); 1481e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } else if (src.IsSRegister()) { 1482e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro StoreSToOffset(src.AsSRegister(), SP, dest.Int32Value()); 1483b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else { 1484e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK(src.IsDRegister()); 1485e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro StoreDToOffset(src.AsDRegister(), SP, dest.Int32Value()); 1486b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1487b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1488b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 14892c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreRef(FrameOffset dest, ManagedRegister msrc) { 14902c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister src = msrc.AsArm(); 1491b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(src.IsCoreRegister()); 1492b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 1493b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1494b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 14952c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) { 14962c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister src = msrc.AsArm(); 1497df20fe0c097073f75f22d16e72fd3636a31d3ca1Ian Rogers CHECK(src.IsCoreRegister()); 1498df20fe0c097073f75f22d16e72fd3636a31d3ca1Ian Rogers StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 1499df20fe0c097073f75f22d16e72fd3636a31d3ca1Ian Rogers} 1500df20fe0c097073f75f22d16e72fd3636a31d3ca1Ian Rogers 15012c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreSpanning(FrameOffset dest, ManagedRegister msrc, 15022c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers FrameOffset in_off, ManagedRegister mscratch) { 15032c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister src = msrc.AsArm(); 15042c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 15057a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 15067a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value()); 15077a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4); 15087a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers} 15097a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers 15102c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::CopyRef(FrameOffset dest, FrameOffset src, 15112c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister mscratch) { 15122c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1513b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value()); 1514b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); 1515b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1516b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 15172c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base, 15182c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers MemberOffset offs) { 15192c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister dest = mdest.AsArm(); 1520b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(dest.IsCoreRegister() && dest.IsCoreRegister()); 1521b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadFromOffset(kLoadWord, dest.AsCoreRegister(), 15222c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers base.AsArm().AsCoreRegister(), offs.Int32Value()); 1523b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1524b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 15252c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::LoadRef(ManagedRegister mdest, FrameOffset src) { 15262c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister dest = mdest.AsArm(); 15272c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers CHECK(dest.IsCoreRegister()); 15282c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers LoadFromOffset(kLoadWord, dest.AsCoreRegister(), 15292c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers SP, src.Int32Value()); 15302c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers } 15312c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers 15322c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, 1533a04d397b990ee7d3ce120e317c19fb4409d80d57Ian Rogers Offset offs) { 15342c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister dest = mdest.AsArm(); 1535a04d397b990ee7d3ce120e317c19fb4409d80d57Ian Rogers CHECK(dest.IsCoreRegister() && dest.IsCoreRegister()); 1536a04d397b990ee7d3ce120e317c19fb4409d80d57Ian Rogers LoadFromOffset(kLoadWord, dest.AsCoreRegister(), 15372c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers base.AsArm().AsCoreRegister(), offs.Int32Value()); 1538a04d397b990ee7d3ce120e317c19fb4409d80d57Ian Rogers} 1539a04d397b990ee7d3ce120e317c19fb4409d80d57Ian Rogers 15402c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, 15412c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister mscratch) { 15422c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1543b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(scratch.IsCoreRegister()); 1544b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadImmediate(scratch.AsCoreRegister(), imm); 1545b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); 1546b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1547b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 15482c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm, 15492c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister mscratch) { 15502c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1551b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(scratch.IsCoreRegister()); 1552b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadImmediate(scratch.AsCoreRegister(), imm); 1553b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), TR, dest.Int32Value()); 1554b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1555b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 15562c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) { 15572c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister dest = mdest.AsArm(); 1558e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro if (dest.IsNoRegister()) { 1559e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK_EQ(0u, size); 1560e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } else if (dest.IsCoreRegister()) { 1561b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK_EQ(4u, size); 1562b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadFromOffset(kLoadWord, dest.AsCoreRegister(), SP, src.Int32Value()); 1563e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } else if (dest.IsRegisterPair()) { 1564e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK_EQ(8u, size); 1565e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadFromOffset(kLoadWord, dest.AsRegisterPairLow(), SP, src.Int32Value()); 1566e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadFromOffset(kLoadWord, dest.AsRegisterPairHigh(), 1567e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro SP, src.Int32Value() + 4); 1568e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } else if (dest.IsSRegister()) { 1569e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadSFromOffset(dest.AsSRegister(), SP, src.Int32Value()); 1570b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else { 1571e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK(dest.IsDRegister()); 1572e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadDFromOffset(dest.AsDRegister(), SP, src.Int32Value()); 1573b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1574b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1575b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 15762c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::LoadRawPtrFromThread(ManagedRegister mdest, 15772c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ThreadOffset offs) { 15782c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister dest = mdest.AsArm(); 1579b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(dest.IsCoreRegister()); 1580b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadFromOffset(kLoadWord, dest.AsCoreRegister(), 1581b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers TR, offs.Int32Value()); 1582b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1583b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 15842c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::CopyRawPtrFromThread(FrameOffset fr_offs, 15852c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ThreadOffset thr_offs, 15862c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister mscratch) { 15872c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1588b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(scratch.IsCoreRegister()); 1589b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), 1590b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers TR, thr_offs.Int32Value()); 1591b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), 1592b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers SP, fr_offs.Int32Value()); 1593b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1594b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 15952c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::CopyRawPtrToThread(ThreadOffset thr_offs, 15962c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers FrameOffset fr_offs, 15972c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister mscratch) { 15982c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1599b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(scratch.IsCoreRegister()); 1600b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), 1601b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers SP, fr_offs.Int32Value()); 1602b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), 1603b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers TR, thr_offs.Int32Value()); 1604b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1605b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 16062c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreStackOffsetToThread(ThreadOffset thr_offs, 16072c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers FrameOffset fr_offs, 16082c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister mscratch) { 16092c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1610b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(scratch.IsCoreRegister()); 1611b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers AddConstant(scratch.AsCoreRegister(), SP, fr_offs.Int32Value(), AL); 1612b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), 1613b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers TR, thr_offs.Int32Value()); 1614b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1615b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 16162c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::StoreStackPointerToThread(ThreadOffset thr_offs) { 161745a76cb99104a222d6a9bd768a084893dcb7cf30Ian Rogers StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value()); 161845a76cb99104a222d6a9bd768a084893dcb7cf30Ian Rogers} 161945a76cb99104a222d6a9bd768a084893dcb7cf30Ian Rogers 16202c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Move(ManagedRegister mdest, ManagedRegister msrc) { 16212c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister dest = mdest.AsArm(); 16222c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister src = msrc.AsArm(); 1623e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro if (!dest.Equals(src)) { 1624e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro if (dest.IsCoreRegister()) { 1625e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK(src.IsCoreRegister()); 1626e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro mov(dest.AsCoreRegister(), ShifterOperand(src.AsCoreRegister())); 16277a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers } else if (dest.IsDRegister()) { 16287a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers CHECK(src.IsDRegister()); 16297a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers vmovd(dest.AsDRegister(), src.AsDRegister()); 16307a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers } else if (dest.IsSRegister()) { 16317a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers CHECK(src.IsSRegister()); 16327a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers vmovs(dest.AsSRegister(), src.AsSRegister()); 1633e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } else { 16347a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers CHECK(dest.IsRegisterPair()); 16357a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers CHECK(src.IsRegisterPair()); 16367a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers // Ensure that the first move doesn't clobber the input of the second 16377a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers if (src.AsRegisterPairHigh() != dest.AsRegisterPairLow()) { 16387a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers mov(dest.AsRegisterPairLow(), ShifterOperand(src.AsRegisterPairLow())); 16397a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers mov(dest.AsRegisterPairHigh(), ShifterOperand(src.AsRegisterPairHigh())); 16407a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers } else { 16417a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers mov(dest.AsRegisterPairHigh(), ShifterOperand(src.AsRegisterPairHigh())); 16427a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers mov(dest.AsRegisterPairLow(), ShifterOperand(src.AsRegisterPairLow())); 16437a99c11d220ec68c208b507570e3a78c2c18a7a1Ian Rogers } 1644e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } 1645b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1646b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1647b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1648dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogersvoid ArmAssembler::Copy(FrameOffset dest, FrameOffset src, ManagedRegister mscratch, size_t size) { 16492c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1650b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(scratch.IsCoreRegister()); 16515381cf941d26030199fcdbe61a614ff01e55a27cShih-wei Liao CHECK(size == 4 || size == 8); 1652b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (size == 4) { 1653dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value()); 1654dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); 16555381cf941d26030199fcdbe61a614ff01e55a27cShih-wei Liao } else if (size == 8) { 1656dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value()); 1657dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); 1658dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value() + 4); 1659dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4); 1660b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1661b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1662b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 1663dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogersvoid ArmAssembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, 1664dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers ManagedRegister mscratch, size_t size) { 1665dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers Register scratch = mscratch.AsArm().AsCoreRegister(); 1666dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers CHECK_EQ(size, 4u); 1667dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers LoadFromOffset(kLoadWord, scratch, src_base.AsArm().AsCoreRegister(), src_offset.Int32Value()); 1668dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers StoreToOffset(kStoreWord, scratch, SP, dest.Int32Value()); 1669dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers} 1670dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers 1671dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogersvoid ArmAssembler::Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, 1672dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers ManagedRegister mscratch, size_t size) { 1673dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers UNIMPLEMENTED(FATAL); 1674dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers} 1675dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers 1676dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogersvoid ArmAssembler::Copy(ThreadOffset dest_base, Offset dest_offset, FrameOffset src, 1677dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers ManagedRegister mscratch, ManagedRegister mscratch2, size_t size) { 1678dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers Register scratch = mscratch.AsArm().AsCoreRegister(); 1679dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers Register scratch2 = mscratch2.AsArm().AsCoreRegister(); 1680dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers CHECK_EQ(size, 4u); 1681dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers LoadFromOffset(kLoadWord, scratch, TR, dest_base.Int32Value()); 1682dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers LoadFromOffset(kLoadWord, scratch2, SP, src.Int32Value()); 1683dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers StoreToOffset(kStoreWord, scratch2, scratch, dest_offset.Int32Value()); 1684dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers} 1685dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers 1686dc51b79e65abcdad094ccd5e5a2caf5153433d49Ian Rogers 1687e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogersvoid ArmAssembler::MemoryBarrier(ManagedRegister mscratch) { 1688e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers#if ANDROID_SMP != 0 1689e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers#if defined(__ARM_HAVE_DMB) 1690e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers int32_t encoding = 0xf57ff05f; // dmb 1691e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers Emit(encoding); 1692e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers#elif defined(__ARM_HAVE_LDREX_STREX) 1693e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers CHECK(mscratch.AsArm().AsCoreRegister() == R12); 1694e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers LoadImmediate(R12, 0); 1695e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers int32_t encoding = 0xee07cfba; // mcr p15, 0, r12, c7, c10, 5 1696e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers Emit(encoding); 1697e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers#else 1698e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers CHECK(mscratch.AsArm().AsCoreRegister() == R12); 1699e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers LoadImmediate(R12, 0xffff0fa0); // kuser_memory_barrier 1700e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers blx(R12); 1701e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers#endif 1702e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers#endif 1703e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers} 1704e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers 17052c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::CreateSirtEntry(ManagedRegister mout_reg, 17062c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers FrameOffset sirt_offset, 17072c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister min_reg, bool null_allowed) { 17082c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister out_reg = mout_reg.AsArm(); 17092c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister in_reg = min_reg.AsArm(); 1710e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()); 1711b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(out_reg.IsCoreRegister()); 1712b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (null_allowed) { 1713408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers // Null values get a SIRT entry value of 0. Otherwise, the SIRT entry is 1714408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers // the address in the SIRT holding the reference. 1715b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset) 1716e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro if (in_reg.IsNoRegister()) { 1717e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(), 1718408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers SP, sirt_offset.Int32Value()); 1719e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro in_reg = out_reg; 1720e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro } 1721b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers cmp(in_reg.AsCoreRegister(), ShifterOperand(0)); 1722b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (!out_reg.Equals(in_reg)) { 1723b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadImmediate(out_reg.AsCoreRegister(), 0, EQ); 1724b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1725408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value(), NE); 1726b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else { 1727408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value(), AL); 1728b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1729b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1730b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 17312c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::CreateSirtEntry(FrameOffset out_off, 17322c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers FrameOffset sirt_offset, 17332c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister mscratch, 17342c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers bool null_allowed) { 17352c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1736b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(scratch.IsCoreRegister()); 1737b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (null_allowed) { 1738b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, 1739408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers sirt_offset.Int32Value()); 1740408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers // Null values get a SIRT entry value of 0. Otherwise, the sirt entry is 1741408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers // the address in the SIRT holding the reference. 1742408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers // e.g. scratch = (scratch == 0) ? 0 : (SP+sirt_offset) 1743b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers cmp(scratch.AsCoreRegister(), ShifterOperand(0)); 1744408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value(), NE); 1745b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } else { 1746408f79aeb676251ba35667a64e86c20638d7cb0bIan Rogers AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value(), AL); 1747b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1748b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, out_off.Int32Value()); 1749b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1750b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 17512c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::LoadReferenceFromSirt(ManagedRegister mout_reg, 17522c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister min_reg) { 17532c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister out_reg = mout_reg.AsArm(); 17542c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister in_reg = min_reg.AsArm(); 1755b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(out_reg.IsCoreRegister()); 1756b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(in_reg.IsCoreRegister()); 1757b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers Label null_arg; 1758b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers if (!out_reg.Equals(in_reg)) { 1759b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadImmediate(out_reg.AsCoreRegister(), 0, EQ); 1760b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers } 1761b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers cmp(in_reg.AsCoreRegister(), ShifterOperand(0)); 1762df20fe0c097073f75f22d16e72fd3636a31d3ca1Ian Rogers LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(), 1763df20fe0c097073f75f22d16e72fd3636a31d3ca1Ian Rogers in_reg.AsCoreRegister(), 0, NE); 1764b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1765b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 17662c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::VerifyObject(ManagedRegister src, bool could_be_null) { 1767b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers // TODO: not validating references 1768b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1769b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 17702c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::VerifyObject(FrameOffset src, bool could_be_null) { 1771b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers // TODO: not validating references 1772b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1773b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 17742c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Call(ManagedRegister mbase, Offset offset, 17752c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister mscratch) { 17762c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister base = mbase.AsArm(); 17772c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1778b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(base.IsCoreRegister()); 1779b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers CHECK(scratch.IsCoreRegister()); 1780b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), 1781b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers base.AsCoreRegister(), offset.Int32Value()); 1782b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers blx(scratch.AsCoreRegister()); 1783b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers // TODO: place reference map on call 1784b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers} 1785b033c75ebda80ac75f936366fe78d1edf5cec937Ian Rogers 17862c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::Call(FrameOffset base, Offset offset, 17872c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister mscratch) { 17882c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 1789e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro CHECK(scratch.IsCoreRegister()); 1790e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro // Call *(*(SP + base) + offset) 1791e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), 1792e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro SP, base.Int32Value()); 1793e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), 1794e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro scratch.AsCoreRegister(), offset.Int32Value()); 1795e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro blx(scratch.AsCoreRegister()); 1796e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro // TODO: place reference map on call 1797e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro} 1798e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro 1799bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogersvoid ArmAssembler::Call(ThreadOffset offset, ManagedRegister scratch) { 1800bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers UNIMPLEMENTED(FATAL); 1801bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers} 1802bdb0391258abc54bf77c676e36847d28a783bfe5Ian Rogers 18032c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::GetCurrentThread(ManagedRegister tr) { 18042c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers mov(tr.AsArm().AsCoreRegister(), ShifterOperand(TR)); 1805668512afd0d9b3772a0abc589208b729ee16bc61Shih-wei Liao} 1806668512afd0d9b3772a0abc589208b729ee16bc61Shih-wei Liao 18072c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::GetCurrentThread(FrameOffset offset, 18082c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister scratch) { 1809668512afd0d9b3772a0abc589208b729ee16bc61Shih-wei Liao StoreToOffset(kStoreWord, TR, SP, offset.Int32Value(), AL); 1810668512afd0d9b3772a0abc589208b729ee16bc61Shih-wei Liao} 1811668512afd0d9b3772a0abc589208b729ee16bc61Shih-wei Liao 18122c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::SuspendPoll(ManagedRegister mscratch, 18132c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ManagedRegister return_reg, 18142c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers FrameOffset return_save_location, 18152c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers size_t return_size) { 18162c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 18172c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmSuspendCountSlowPath* slow = 18182c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers new ArmSuspendCountSlowPath(return_reg.AsArm(), return_save_location, 18192c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers return_size); 1820e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro buffer_.EnqueueSlowPath(slow); 1821e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), 1822e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro TR, Thread::SuspendCountOffset().Int32Value()); 1823e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro cmp(scratch.AsCoreRegister(), ShifterOperand(0)); 1824e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro b(slow->Entry(), NE); 1825e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro Bind(slow->Continuation()); 1826e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro} 1827e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro 18282c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmSuspendCountSlowPath::Emit(Assembler* sasm) { 18292c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmAssembler* sp_asm = down_cast<ArmAssembler*>(sasm); 18302c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers#define __ sp_asm-> 18312c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers __ Bind(&entry_); 1832e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro // Save return value 18332c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers __ Store(return_save_location_, return_register_, return_size_); 1834e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers // Pass thread as argument 1835e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers __ mov(R0, ShifterOperand(TR)); 1836e5de95b3f9609e02fefd7cda7b21f30c9412eb4cIan Rogers __ LoadFromOffset(kLoadWord, R12, TR, OFFSETOF_MEMBER(Thread, pCheckSuspendFromCode)); 1837e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro // Note: assume that link register will be spilled/filled on method entry/exit 18382c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers __ blx(R12); 1839e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro // Reload return value 18402c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers __ Load(return_register_, return_save_location_, return_size_); 18412c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers __ b(&continuation_); 18422c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers#undef __ 184345a76cb99104a222d6a9bd768a084893dcb7cf30Ian Rogers} 184445a76cb99104a222d6a9bd768a084893dcb7cf30Ian Rogers 18452c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmAssembler::ExceptionPoll(ManagedRegister mscratch) { 18462c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmManagedRegister scratch = mscratch.AsArm(); 184767375acd9fec74cc2054554fe1ed0a7d213e1e47Ian Rogers ArmExceptionSlowPath* slow = new ArmExceptionSlowPath(scratch); 1848e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro buffer_.EnqueueSlowPath(slow); 1849e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), 1850e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro TR, Thread::ExceptionOffset().Int32Value()); 1851e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro cmp(scratch.AsCoreRegister(), ShifterOperand(0)); 1852e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro b(slow->Entry(), NE); 1853e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro} 1854e2d373e6e09c1df9a47e73a26254048adb31ce82Carl Shapiro 18552c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogersvoid ArmExceptionSlowPath::Emit(Assembler* sasm) { 18562c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers ArmAssembler* sp_asm = down_cast<ArmAssembler*>(sasm); 18572c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers#define __ sp_asm-> 18582c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers __ Bind(&entry_); 185967375acd9fec74cc2054554fe1ed0a7d213e1e47Ian Rogers 186067375acd9fec74cc2054554fe1ed0a7d213e1e47Ian Rogers // Pass exception object as argument 186167375acd9fec74cc2054554fe1ed0a7d213e1e47Ian Rogers // Don't care about preserving R0 as this call won't return 186267375acd9fec74cc2054554fe1ed0a7d213e1e47Ian Rogers __ mov(R0, ShifterOperand(scratch_.AsCoreRegister())); 186367375acd9fec74cc2054554fe1ed0a7d213e1e47Ian Rogers // Set up call to Thread::Current()->pDeliverException 186467375acd9fec74cc2054554fe1ed0a7d213e1e47Ian Rogers __ LoadFromOffset(kLoadWord, R12, TR, OFFSETOF_MEMBER(Thread, pDeliverException)); 18652c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers __ blx(R12); 186667375acd9fec74cc2054554fe1ed0a7d213e1e47Ian Rogers // Call never returns 186767375acd9fec74cc2054554fe1ed0a7d213e1e47Ian Rogers __ bkpt(0); 18682c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers#undef __ 186945a76cb99104a222d6a9bd768a084893dcb7cf30Ian Rogers} 187045a76cb99104a222d6a9bd768a084893dcb7cf30Ian Rogers 18712c8f653c98d658419f464b6147c10e11a664d2e6Ian Rogers} // namespace arm 18726b6b5f0e67ce03f38223a525612955663bc1799bCarl Shapiro} // namespace art 1873