165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison/* 265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * Copyright (C) 2014 The Android Open Source Project 365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * 465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * Licensed under the Apache License, Version 2.0 (the "License"); 565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * you may not use this file except in compliance with the License. 665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * You may obtain a copy of the License at 765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * 865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * http://www.apache.org/licenses/LICENSE-2.0 965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * 1065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * Unless required by applicable law or agreed to in writing, software 1165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * distributed under the License is distributed on an "AS IS" BASIS, 1265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * See the License for the specific language governing permissions and 1465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * limitations under the License. 1565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison */ 1665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 1765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "assembler_arm32.h" 1865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 1941b175aba41c9365a1c53b8a1afbd17129c87c14Vladimir Marko#include "base/bit_utils.h" 2065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "base/logging.h" 2165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "entrypoints/quick/quick_entrypoints.h" 2265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "offsets.h" 2365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "thread.h" 2465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 2565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonnamespace art { 2665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonnamespace arm { 2765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 283bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffraybool Arm32Assembler::ShifterOperandCanHoldArm32(uint32_t immediate, ShifterOperand* shifter_op) { 293bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray // Avoid the more expensive test for frequent small immediate values. 303bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray if (immediate < (1 << kImmed8Bits)) { 313bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray shifter_op->type_ = ShifterOperand::kImmediate; 323bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray shifter_op->is_rotate_ = true; 333bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray shifter_op->rotate_ = 0; 343bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray shifter_op->immed_ = immediate; 353bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray return true; 363bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray } 373bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray // Note that immediate must be unsigned for the test to work correctly. 383bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray for (int rot = 0; rot < 16; rot++) { 393bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray uint32_t imm8 = (immediate << 2*rot) | (immediate >> (32 - 2*rot)); 403bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray if (imm8 < (1 << kImmed8Bits)) { 413bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray shifter_op->type_ = ShifterOperand::kImmediate; 423bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray shifter_op->is_rotate_ = true; 433bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray shifter_op->rotate_ = rot; 443bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray shifter_op->immed_ = imm8; 453bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray return true; 463bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray } 473bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray } 483bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray return false; 493bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray} 503bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray 513bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffraybool Arm32Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED, 523bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray Register rn ATTRIBUTE_UNUSED, 533bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray Opcode opcode ATTRIBUTE_UNUSED, 543bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray uint32_t immediate, 553bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray ShifterOperand* shifter_op) { 563bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray return ShifterOperandCanHoldArm32(immediate, shifter_op); 573bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray} 583bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray 5965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, 6065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 6165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), AND, 0, rn, rd, so); 6265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 6365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 6465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 6565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, 6665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 6765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), EOR, 0, rn, rd, so); 6865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 6965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 7065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 7165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, 7265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 7365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), SUB, 0, rn, rd, so); 7465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 7565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 7665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, 7765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 7865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), RSB, 0, rn, rd, so); 7965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 8065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 8165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so, 8265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 8365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), RSB, 1, rn, rd, so); 8465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 8565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 8665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 8765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::add(Register rd, Register rn, const ShifterOperand& so, 8865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 8965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ADD, 0, rn, rd, so); 9065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 9165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 9265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 9365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::adds(Register rd, Register rn, const ShifterOperand& so, 9465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 9565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ADD, 1, rn, rd, so); 9665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 9765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 9865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 9965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::subs(Register rd, Register rn, const ShifterOperand& so, 10065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 10165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), SUB, 1, rn, rd, so); 10265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 10365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 10465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 10565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::adc(Register rd, Register rn, const ShifterOperand& so, 10665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 10765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ADC, 0, rn, rd, so); 10865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 10965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 11065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 11165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::sbc(Register rd, Register rn, const ShifterOperand& so, 11265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 11365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), SBC, 0, rn, rd, so); 11465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 11565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 11665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 11765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::rsc(Register rd, Register rn, const ShifterOperand& so, 11865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 11965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), RSC, 0, rn, rd, so); 12065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 12165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 12265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 12365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::tst(Register rn, const ShifterOperand& so, Condition cond) { 12465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. 12565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), TST, 1, rn, R0, so); 12665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 12765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 12865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 12965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::teq(Register rn, const ShifterOperand& so, Condition cond) { 13065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. 13165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), TEQ, 1, rn, R0, so); 13265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 13365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 13465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 13565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::cmp(Register rn, const ShifterOperand& so, Condition cond) { 13665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), CMP, 1, rn, R0, so); 13765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 13865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 13965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 14065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::cmn(Register rn, const ShifterOperand& so, Condition cond) { 14165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), CMN, 1, rn, R0, so); 14265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 14365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 14465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 14565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::orr(Register rd, Register rn, 14665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so, Condition cond) { 14765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ORR, 0, rn, rd, so); 14865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 14965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::orrs(Register rd, Register rn, 15265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so, Condition cond) { 15365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ORR, 1, rn, rd, so); 15465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 15565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mov(Register rd, const ShifterOperand& so, Condition cond) { 15865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), MOV, 0, R0, rd, so); 15965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 16065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 16165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 16265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::movs(Register rd, const ShifterOperand& so, Condition cond) { 16365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), MOV, 1, R0, rd, so); 16465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 16565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 16665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 16765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::bic(Register rd, Register rn, const ShifterOperand& so, 16865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 16965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), BIC, 0, rn, rd, so); 17065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 17165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 17265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 17365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mvn(Register rd, const ShifterOperand& so, Condition cond) { 17465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), MVN, 0, R0, rd, so); 17565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 17665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 17765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 17865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mvns(Register rd, const ShifterOperand& so, Condition cond) { 17965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), MVN, 1, R0, rd, so); 18065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 18165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 18265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 18365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { 18465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Assembler registers rd, rn, rm are encoded as rn, rm, rs. 18565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMulOp(cond, 0, R0, rd, rn, rm); 18665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 18765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 18865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 18965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mla(Register rd, Register rn, Register rm, Register ra, 19065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 19165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 19265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMulOp(cond, B21, ra, rd, rn, rm); 19365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 19465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 19565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 19665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mls(Register rd, Register rn, Register rm, Register ra, 19765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 19865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 19965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMulOp(cond, B22 | B21, ra, rd, rn, rm); 20065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 20165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 20265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 20365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::umull(Register rd_lo, Register rd_hi, Register rn, 20465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rm, Condition cond) { 20565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 20665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm); 20765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 20865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 20965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 21065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) { 21165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 21265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 21365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 21465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 21565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = B26 | B25 | B24 | B20 | 21665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B15 | B14 | B13 | B12 | 21765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(cond) << kConditionShift) | 21865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << 0) | 21965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << 16) | 22065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << 8) | 22165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B4; 22265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 22365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 22465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 22565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 22665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) { 22765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 22865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 22965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 23065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 23165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = B26 | B25 | B24 | B21 | B20 | 23265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B15 | B14 | B13 | B12 | 23365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(cond) << kConditionShift) | 23465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << 0) | 23565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << 16) | 23665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << 8) | 23765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B4; 23865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 23965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 24065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 24165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 24251d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillainvoid Arm32Assembler::sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) { 24351d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK_NE(rd, kNoRegister); 24451d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK_NE(rn, kNoRegister); 24551d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK_NE(cond, kNoCondition); 24651d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK_LE(lsb, 31U); 24751d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK(1U <= width && width <= 32U) << width; 24851d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain uint32_t widthminus1 = width - 1; 24951d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain 25051d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 25151d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain B26 | B25 | B24 | B23 | B21 | 25251d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain (widthminus1 << 16) | 25351d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain (static_cast<uint32_t>(rd) << 12) | 25451d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain (lsb << 7) | 25551d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain B6 | B4 | 25651d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain static_cast<uint32_t>(rn); 25751d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain Emit(encoding); 25851d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain} 25951d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain 26051d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain 261981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillainvoid Arm32Assembler::ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) { 262981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK_NE(rd, kNoRegister); 263981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK_NE(rn, kNoRegister); 264981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK_NE(cond, kNoCondition); 265981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK_LE(lsb, 31U); 266981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK(1U <= width && width <= 32U) << width; 267981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain uint32_t widthminus1 = width - 1; 268981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain 269981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 270981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain B26 | B25 | B24 | B23 | B22 | B21 | 271981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain (widthminus1 << 16) | 272981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain (static_cast<uint32_t>(rd) << 12) | 273981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain (lsb << 7) | 274981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain B6 | B4 | 275981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain static_cast<uint32_t>(rn); 276981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain Emit(encoding); 277981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain} 278981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain 279981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain 28065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldr(Register rd, const Address& ad, Condition cond) { 28165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOp(cond, true, false, rd, ad); 28265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 28365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 28465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 28565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::str(Register rd, const Address& ad, Condition cond) { 28665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOp(cond, false, false, rd, ad); 28765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 28865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 28965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 29065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrb(Register rd, const Address& ad, Condition cond) { 29165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOp(cond, true, true, rd, ad); 29265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 29365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 29465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 29565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::strb(Register rd, const Address& ad, Condition cond) { 29665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOp(cond, false, true, rd, ad); 29765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 29865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 29965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 30065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrh(Register rd, const Address& ad, Condition cond) { 30165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad); 30265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 30365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 30465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 30565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::strh(Register rd, const Address& ad, Condition cond) { 30665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad); 30765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 30865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 30965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 31065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrsb(Register rd, const Address& ad, Condition cond) { 31165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad); 31265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 31365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 31465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 31565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrsh(Register rd, const Address& ad, Condition cond) { 31665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad); 31765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 31865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 31965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 32065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrd(Register rd, const Address& ad, Condition cond) { 32165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_EQ(rd % 2, 0); 32265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad); 32365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 32465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 32565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 32665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::strd(Register rd, const Address& ad, Condition cond) { 32765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_EQ(rd % 2, 0); 32865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad); 32965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 33065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 33165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 33265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldm(BlockAddressMode am, 33365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 33465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison RegList regs, 33565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 33665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMultiMemOp(cond, am, true, base, regs); 33765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 33865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 33965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 34065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::stm(BlockAddressMode am, 34165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 34265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison RegList regs, 34365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 34465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMultiMemOp(cond, am, false, base, regs); 34565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 34665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 34765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 34865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovs(SRegister sd, SRegister sm, Condition cond) { 34965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm); 35065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 35165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 35265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 35365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) { 35465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm); 35565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 35665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 35765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 35865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonbool Arm32Assembler::vmovs(SRegister sd, float s_imm, Condition cond) { 35965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint32_t imm32 = bit_cast<uint32_t, float>(s_imm); 36065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (((imm32 & ((1 << 19) - 1)) == 0) && 36165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) || 36265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) -1)))) { 36365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint8_t imm8 = ((imm32 >> 31) << 7) | (((imm32 >> 29) & 1) << 6) | 36465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((imm32 >> 19) & ((1 << 6) -1)); 36565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf), 36665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison sd, S0, S0); 36765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return true; 36865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 36965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return false; 37065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 37165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 37265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 37365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonbool Arm32Assembler::vmovd(DRegister dd, double d_imm, Condition cond) { 37465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint64_t imm64 = bit_cast<uint64_t, double>(d_imm); 37565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (((imm64 & ((1LL << 48) - 1)) == 0) && 37665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) || 37765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) -1)))) { 37865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint8_t imm8 = ((imm64 >> 63) << 7) | (((imm64 >> 61) & 1) << 6) | 37965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((imm64 >> 48) & ((1 << 6) -1)); 38065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf), 38165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison dd, D0, D0); 38265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return true; 38365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 38465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return false; 38565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 38665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 38765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 38865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vadds(SRegister sd, SRegister sn, SRegister sm, 38965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 39065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B21 | B20, sd, sn, sm); 39165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 39265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 39365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 39465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm, 39565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 39665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B21 | B20, dd, dn, dm); 39765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 39865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 39965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 40065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vsubs(SRegister sd, SRegister sn, SRegister sm, 40165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 40265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm); 40365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 40465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 40565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 40665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm, 40765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 40865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm); 40965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 41065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 41165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 41265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmuls(SRegister sd, SRegister sn, SRegister sm, 41365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 41465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B21, sd, sn, sm); 41565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 41665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 41765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 41865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm, 41965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 42065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B21, dd, dn, dm); 42165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 42265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 42365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 42465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmlas(SRegister sd, SRegister sn, SRegister sm, 42565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 42665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, 0, sd, sn, sm); 42765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 42865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 42965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 43065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmlad(DRegister dd, DRegister dn, DRegister dm, 43165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 43265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, 0, dd, dn, dm); 43365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 43465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 43565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 43665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmlss(SRegister sd, SRegister sn, SRegister sm, 43765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 43865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B6, sd, sn, sm); 43965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 44065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 44165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 44265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmlsd(DRegister dd, DRegister dn, DRegister dm, 44365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 44465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B6, dd, dn, dm); 44565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 44665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 44765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 44865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vdivs(SRegister sd, SRegister sn, SRegister sm, 44965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 45065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23, sd, sn, sm); 45165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 45265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 45365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 45465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vdivd(DRegister dd, DRegister dn, DRegister dm, 45565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 45665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23, dd, dn, dm); 45765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 45865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 45965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 46065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vabss(SRegister sd, SRegister sm, Condition cond) { 46165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm); 46265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 46365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 46465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 46565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vabsd(DRegister dd, DRegister dm, Condition cond) { 46665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm); 46765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 46865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 46965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 47065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vnegs(SRegister sd, SRegister sm, Condition cond) { 47165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm); 47265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 47365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 47465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 47565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vnegd(DRegister dd, DRegister dm, Condition cond) { 47665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm); 47765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 47865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 47965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 48065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vsqrts(SRegister sd, SRegister sm, Condition cond) { 48165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm); 48265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 48365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 48465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) { 48565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm); 48665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 48765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 48865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 48965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) { 49065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm); 49165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 49265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 49365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 49465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtds(DRegister dd, SRegister sm, Condition cond) { 49565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm); 49665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 49765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 49865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 49965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtis(SRegister sd, SRegister sm, Condition cond) { 50065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); 50165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 50265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 50365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 50465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtid(SRegister sd, DRegister dm, Condition cond) { 50565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm); 50665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 50765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 50865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 50965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) { 51065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); 51165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 51265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 51365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 51465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) { 51565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm); 51665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 51765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 51865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 51965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtus(SRegister sd, SRegister sm, Condition cond) { 52065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); 52165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 52265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 52365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 52465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtud(SRegister sd, DRegister dm, Condition cond) { 52565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm); 52665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 52765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 52865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 52965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) { 53065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm); 53165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 53265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 53365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 53465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) { 53565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm); 53665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 53765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 53865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 53965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) { 54065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm); 54165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 54265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 54365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 54465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcmpd(DRegister dd, DRegister dm, Condition cond) { 54565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm); 54665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 54765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 54865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 54965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcmpsz(SRegister sd, Condition cond) { 55065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0); 55165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 55265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 55365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 55465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcmpdz(DRegister dd, Condition cond) { 55565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0); 55665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 55765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 55865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::b(Label* label, Condition cond) { 55965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitBranch(cond, label, false); 56065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 56165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 56265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 56365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::bl(Label* label, Condition cond) { 56465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitBranch(cond, label, true); 56565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 56665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 56765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 56865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::MarkExceptionHandler(Label* label) { 56965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0)); 57065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Label l; 57165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison b(&l); 57265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitBranch(AL, label, false); 57365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Bind(&l); 57465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 57565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 57665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 57765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Emit(int32_t value) { 57865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison AssemblerBuffer::EnsureCapacity ensured(&buffer_); 57965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison buffer_.Emit<int32_t>(value); 58065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 58165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 58265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 58365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitType01(Condition cond, 58465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int type, 58565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Opcode opcode, 58665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int set_cc, 58765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rn, 58865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, 58965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so) { 59065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 59165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 59265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 59365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison type << kTypeShift | 59465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(opcode) << kOpcodeShift | 59565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison set_cc << kSShift | 59665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rn) << kRnShift | 59765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | 59865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison so.encodingArm(); 59965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 60065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 60165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 60265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 60365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitType5(Condition cond, int offset, bool link) { 60465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 60565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 60665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 5 << kTypeShift | 60765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (link ? 1 : 0) << kLinkShift; 60865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(Arm32Assembler::EncodeBranchOffset(offset, encoding)); 60965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 61065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 61165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 61265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitMemOp(Condition cond, 61345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool load, 61445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool byte, 61545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison Register rd, 61645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison const Address& ad) { 61765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 61865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 61965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 62065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 62145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison int32_t encoding = 0; 62245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (!ad.IsImmediate() && ad.GetRegisterOffset() == PC) { 62345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison // PC relative LDR(literal) 62445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison int32_t offset = ad.GetOffset(); 62545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison int32_t u = B23; 62645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (offset < 0) { 62745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison offset = -offset; 62845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison u = 0; 62945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 63045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison CHECK_LT(offset, (1 << 12)); 63145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison encoding = (static_cast<int32_t>(cond) << kConditionShift) | 63245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison B26 | B24 | u | B20 | 63345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (load ? L : 0) | 63445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (byte ? B : 0) | 63545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 63645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 0xf << 16 | 63745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (offset & 0xfff); 63845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 63945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 64045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison encoding = (static_cast<int32_t>(cond) << kConditionShift) | 64145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison B26 | 64245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (load ? L : 0) | 64345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (byte ? B : 0) | 64445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 64545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison addr.encodingArm(); 64645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 64765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 64865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 64965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 65065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 65165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitMemOpAddressMode3(Condition cond, 65265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t mode, 65365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, 65465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& ad) { 65565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 65665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 65765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 65865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 65965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B22 | 66065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mode | 66165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 66265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison addr.encoding3(); 66365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 66465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 66565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 66665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 66765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitMultiMemOp(Condition cond, 66865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison BlockAddressMode am, 66965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison bool load, 67065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 67165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison RegList regs) { 67265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, kNoRegister); 67365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 67465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 67565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | 67665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison am | 67765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (load ? L : 0) | 67865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(base) << kRnShift) | 67965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison regs; 68065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 68165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 68265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 68365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 68465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitShiftImmediate(Condition cond, 68565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Shift opcode, 68665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, 68765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rm, 68865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so) { 68965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 69065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(so.IsImmediate()); 69165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 69265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(MOV) << kOpcodeShift | 69365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | 69465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison so.encodingArm() << kShiftImmShift | 69565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(opcode) << kShiftShift | 69665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rm); 69765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 69865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 69965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 70065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 70165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitShiftRegister(Condition cond, 70265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Shift opcode, 70365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, 70465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rm, 70565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so) { 70665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 70765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(so.IsRegister()); 70865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 70965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(MOV) << kOpcodeShift | 71065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | 71165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison so.encodingArm() << kShiftRegisterShift | 71265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(opcode) << kShiftShift | 71365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B4 | 71465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rm); 71565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 71665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 71765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 71865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 71965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitBranch(Condition cond, Label* label, bool link) { 72065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (label->IsBound()) { 72165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType5(cond, label->Position() - buffer_.Size(), link); 72265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 72365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int position = buffer_.Size(); 72465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Use the offset field of the branch instruction for linking the sites. 72565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType5(cond, label->position_, link); 72665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison label->LinkTo(position); 72765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 72865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 72965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 73065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 73165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::clz(Register rd, Register rm, Condition cond) { 73265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 73365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 73465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 73565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, PC); 73665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, PC); 73765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 73865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | B22 | B21 | (0xf << 16) | 73965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 74065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (0xf << 8) | B4 | static_cast<int32_t>(rm); 74165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 74265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 74365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 74465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 74565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::movw(Register rd, uint16_t imm16, Condition cond) { 74665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 74765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 74865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B25 | B24 | ((imm16 >> 12) << 16) | 74965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); 75065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 75165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 75265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 75365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 75465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::movt(Register rd, uint16_t imm16, Condition cond) { 75565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 75665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 75765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B25 | B24 | B22 | ((imm16 >> 12) << 16) | 75865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); 75965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 76065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 76165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 76265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 76365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitMulOp(Condition cond, int32_t opcode, 76465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, Register rn, 76565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rm, Register rs) { 76665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 76765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 76865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 76965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rs, kNoRegister); 77065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 77165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = opcode | 77265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(cond) << kConditionShift) | 77365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << kRnShift) | 77465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 77565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rs) << kRsShift) | 77665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B7 | B4 | 77765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << kRmShift); 77865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 77965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 78065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 78152c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle 78265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrex(Register rt, Register rn, Condition cond) { 78365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 78465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 78565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 78665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 78765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | 78865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B23 | 78965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison L | 79065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << kLdExRnShift) | 79165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt) << kLdExRtShift) | 79265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0; 79365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 79465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 79565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 79665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 79752c489645b6e9ae33623f1ec24143cde5444906eCalin Juravlevoid Arm32Assembler::ldrexd(Register rt, Register rt2, Register rn, Condition cond) { 79852c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rn, kNoRegister); 79952c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rt, kNoRegister); 80052c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rt2, kNoRegister); 80152c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rt, R14); 80252c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_EQ(0u, static_cast<uint32_t>(rt) % 2); 80352c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_EQ(static_cast<uint32_t>(rt) + 1, static_cast<uint32_t>(rt2)); 80452c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(cond, kNoCondition); 80552c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle 80652c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle int32_t encoding = 80752c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle (static_cast<uint32_t>(cond) << kConditionShift) | 80852c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle B24 | B23 | B21 | B20 | 80952c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle static_cast<uint32_t>(rn) << 16 | 81052c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle static_cast<uint32_t>(rt) << 12 | 81152c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0; 81252c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle Emit(encoding); 81352c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle} 81452c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle 81552c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle 81665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::strex(Register rd, 81765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rt, 81865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rn, 81965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 82065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 82165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 82265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 82365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 82465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 82565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | 82665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B23 | 82765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << kStrExRnShift) | 82865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << kStrExRdShift) | 82965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B10 | B9 | B8 | B7 | B4 | 83065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt) << kStrExRtShift); 83165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 83265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 83365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 83452c489645b6e9ae33623f1ec24143cde5444906eCalin Juravlevoid Arm32Assembler::strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) { 83552c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rd, kNoRegister); 83652c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rn, kNoRegister); 83752c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rt, kNoRegister); 83852c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rt2, kNoRegister); 83952c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rt, R14); 84052c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rd, rt); 84152c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(rd, rt2); 84252c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_EQ(0u, static_cast<uint32_t>(rt) % 2); 84352c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_EQ(static_cast<uint32_t>(rt) + 1, static_cast<uint32_t>(rt2)); 84452c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle CHECK_NE(cond, kNoCondition); 84552c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle 84652c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle int32_t encoding = 84752c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle (static_cast<uint32_t>(cond) << kConditionShift) | 84852c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle B24 | B23 | B21 | 84952c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle static_cast<uint32_t>(rn) << 16 | 85052c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle static_cast<uint32_t>(rd) << 12 | 85152c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle B11 | B10 | B9 | B8 | B7 | B4 | 85252c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle static_cast<uint32_t>(rt); 85352c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle Emit(encoding); 85452c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle} 85552c489645b6e9ae33623f1ec24143cde5444906eCalin Juravle 85665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 85765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::clrex(Condition cond) { 85865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_EQ(cond, AL); // This cannot be conditional on ARM. 85965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (kSpecialCondition << kConditionShift) | 86065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf; 86165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 86265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 86365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 86465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 86565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::nop(Condition cond) { 86665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 86765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 86865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B25 | B24 | B21 | (0xf << 12); 86965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 87065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 87165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 87265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 87365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovsr(SRegister sn, Register rt, Condition cond) { 87465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sn, kNoSRegister); 87565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 87665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 87765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 87865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 87965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 88065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | 88165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) >> 1)*B16) | 88265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | 88365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) & 1)*B7) | B4; 88465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 88565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 88665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 88765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 88865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovrs(Register rt, SRegister sn, Condition cond) { 88965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sn, kNoSRegister); 89065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 89165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 89265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 89365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 89465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 89565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B20 | 89665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) >> 1)*B16) | 89765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | 89865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) & 1)*B7) | B4; 89965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 90065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 90165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 90265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 90365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovsrr(SRegister sm, Register rt, Register rt2, 90465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 90565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, kNoSRegister); 90665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, S31); 90765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 90865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 90965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 91065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, kNoRegister); 91165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, SP); 91265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, PC); 91365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 91465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 91565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B22 | 91665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt2)*B16) | 91765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | 91865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sm) & 1)*B5) | B4 | 91965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(sm) >> 1); 92065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 92165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 92265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 92365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 92465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovrrs(Register rt, Register rt2, SRegister sm, 92565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 92665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, kNoSRegister); 92765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, S31); 92865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 92965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 93065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 93165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, kNoRegister); 93265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, SP); 93365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, PC); 93465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, rt2); 93565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 93665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 93765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B22 | B20 | 93865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt2)*B16) | 93965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | 94065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sm) & 1)*B5) | B4 | 94165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(sm) >> 1); 94265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 94365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 94465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 94565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 94665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovdrr(DRegister dm, Register rt, Register rt2, 94765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 94865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dm, kNoDRegister); 94965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 95065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 95165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 95265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, kNoRegister); 95365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, SP); 95465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, PC); 95565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 95665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 95765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B22 | 95865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt2)*B16) | 95965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | 96065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | 96165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(dm) & 0xf); 96265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 96365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 96465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 96565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 96665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovrrd(Register rt, Register rt2, DRegister dm, 96765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 96865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dm, kNoDRegister); 96965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 97065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 97165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 97265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, kNoRegister); 97365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, SP); 97465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, PC); 97565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, rt2); 97665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 97765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 97865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B22 | B20 | 97965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt2)*B16) | 98065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | 98165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | 98265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(dm) & 0xf); 98365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 98465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 98565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 98665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 98765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vldrs(SRegister sd, const Address& ad, Condition cond) { 98865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 98965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sd, kNoSRegister); 99065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 99165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 99265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B24 | B20 | 99365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) & 1)*B22) | 99465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) >> 1)*B12) | 99565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | addr.vencoding(); 99665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 99765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 99865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 99965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 100065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vstrs(SRegister sd, const Address& ad, Condition cond) { 100165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 100265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); 100365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sd, kNoSRegister); 100465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 100565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 100665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B24 | 100765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) & 1)*B22) | 100865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) >> 1)*B12) | 100965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | addr.vencoding(); 101065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 101165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 101265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 101365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 101465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vldrd(DRegister dd, const Address& ad, Condition cond) { 101565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 101665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dd, kNoDRegister); 101765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 101865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 101965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B24 | B20 | 102065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) >> 4)*B22) | 102165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) & 0xf)*B12) | 102265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | B8 | addr.vencoding(); 102365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 102465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 102565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 102665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 102765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vstrd(DRegister dd, const Address& ad, Condition cond) { 102865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 102965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); 103065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dd, kNoDRegister); 103165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 103265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 103365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B24 | 103465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) >> 4)*B22) | 103565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) & 0xf)*B12) | 103665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | B8 | addr.vencoding(); 103765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 103865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 103965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 104065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 104165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vpushs(SRegister reg, int nregs, Condition cond) { 104265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, false, cond); 104365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 104465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 104565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 104665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vpushd(DRegister reg, int nregs, Condition cond) { 104765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, true, cond); 104865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 104965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 105065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 105165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vpops(SRegister reg, int nregs, Condition cond) { 105265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, false, cond); 105365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 105465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 105565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 105665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vpopd(DRegister reg, int nregs, Condition cond) { 105765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, true, cond); 105865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 105965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 106065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 106165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVPushPop(uint32_t reg, int nregs, bool push, bool dbl, Condition cond) { 106265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 106365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_GT(nregs, 0); 106465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint32_t D; 106565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint32_t Vd; 106665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (dbl) { 106765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Encoded as D:Vd. 106865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison D = (reg >> 4) & 1; 1069c8ccf68b805c92674545f63e0341ba47e8d9701cAndreas Gampe Vd = reg & 15U /* 0b1111 */; 107065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 107165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Encoded as Vd:D. 107265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison D = reg & 1; 1073c8ccf68b805c92674545f63e0341ba47e8d9701cAndreas Gampe Vd = (reg >> 1) & 15U /* 0b1111 */; 107465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 107565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = B27 | B26 | B21 | B19 | B18 | B16 | 107665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | 107765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (dbl ? B8 : 0) | 107865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (push ? B24 : (B23 | B20)) | 107965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(cond) << kConditionShift | 108065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison nregs << (dbl ? 1 : 0) | 108165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison D << 22 | 108265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Vd << 12; 108365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 108465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 108565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 108665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 108765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVFPsss(Condition cond, int32_t opcode, 108865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison SRegister sd, SRegister sn, SRegister sm) { 108965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sd, kNoSRegister); 109065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sn, kNoSRegister); 109165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, kNoSRegister); 109265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 109365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 109465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B11 | B9 | opcode | 109565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) & 1)*B22) | 109665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) >> 1)*B16) | 109765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) >> 1)*B12) | 109865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) & 1)*B7) | 109965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sm) & 1)*B5) | 110065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(sm) >> 1); 110165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 110265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 110365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 110465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 110565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVFPddd(Condition cond, int32_t opcode, 110665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison DRegister dd, DRegister dn, DRegister dm) { 110765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dd, kNoDRegister); 110865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dn, kNoDRegister); 110965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dm, kNoDRegister); 111065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 111165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 111265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B11 | B9 | B8 | opcode | 111365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) >> 4)*B22) | 111465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dn) & 0xf)*B16) | 111565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) & 0xf)*B12) | 111665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dn) >> 4)*B7) | 111765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dm) >> 4)*B5) | 111865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(dm) & 0xf); 111965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 112065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 112165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 112265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 112365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVFPsd(Condition cond, int32_t opcode, 112465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison SRegister sd, DRegister dm) { 112565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sd, kNoSRegister); 112665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dm, kNoDRegister); 112765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 112865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 112965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B11 | B9 | opcode | 113065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) & 1)*B22) | 113165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) >> 1)*B12) | 113265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dm) >> 4)*B5) | 113365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(dm) & 0xf); 113465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 113565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 113665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 113765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 113865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVFPds(Condition cond, int32_t opcode, 113965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison DRegister dd, SRegister sm) { 114065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dd, kNoDRegister); 114165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, kNoSRegister); 114265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 114365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 114465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B11 | B9 | opcode | 114565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) >> 4)*B22) | 114665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) & 0xf)*B12) | 114765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sm) & 1)*B5) | 114865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(sm) >> 1); 114965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 115065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 115165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 115265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 115365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Lsl(Register rd, Register rm, uint32_t shift_imm, 115445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 11559aec02fc5df5518c16f1e5a9b6cb198a192db973Calin Juravle CHECK_LE(shift_imm, 31u); 115645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 115745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, LSL, shift_imm), cond); 115845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 115945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, LSL, shift_imm), cond); 116045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 116165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 116265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 116365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 116465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Lsr(Register rd, Register rm, uint32_t shift_imm, 116545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 11669aec02fc5df5518c16f1e5a9b6cb198a192db973Calin Juravle CHECK(1u <= shift_imm && shift_imm <= 32u); 116765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. 116845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 116945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, LSR, shift_imm), cond); 117045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 117145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, LSR, shift_imm), cond); 117245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 117365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 117465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 117565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 117665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Asr(Register rd, Register rm, uint32_t shift_imm, 117745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 11789aec02fc5df5518c16f1e5a9b6cb198a192db973Calin Juravle CHECK(1u <= shift_imm && shift_imm <= 32u); 117965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. 118045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 118145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ASR, shift_imm), cond); 118245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 118345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ASR, shift_imm), cond); 118445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 118565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 118665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 118765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 118865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Ror(Register rd, Register rm, uint32_t shift_imm, 118945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 11909aec02fc5df5518c16f1e5a9b6cb198a192db973Calin Juravle CHECK(1u <= shift_imm && shift_imm <= 31u); 119145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 119245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ROR, shift_imm), cond); 119345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 119445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ROR, shift_imm), cond); 119545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 119665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 119765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 119845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Rrx(Register rd, Register rm, bool setcc, Condition cond) { 119945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 120045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ROR, 0), cond); 120145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 120245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ROR, 0), cond); 120345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 120465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 120565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 120665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 120745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Lsl(Register rd, Register rm, Register rn, 120845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 120945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 121045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, LSL, rn), cond); 121145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 121245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, LSL, rn), cond); 121345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 121445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison} 121545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 121645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 121745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Lsr(Register rd, Register rm, Register rn, 121845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 121945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 122045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, LSR, rn), cond); 122145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 122245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, LSR, rn), cond); 122345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 122445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison} 122545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 122645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 122745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Asr(Register rd, Register rm, Register rn, 122845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 122945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 123045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ASR, rn), cond); 123145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 123245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ASR, rn), cond); 123345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 123445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison} 123545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 123645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 123745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Ror(Register rd, Register rm, Register rn, 123845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 123945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 124045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ROR, rn), cond); 124145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 124245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ROR, rn), cond); 124345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 124445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison} 124545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 124665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmstat(Condition cond) { // VMRS APSR_nzcv, FPSCR 124765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 124865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 124965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | 125065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(PC)*B12) | 125165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | B4; 125265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 125365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 125465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 125565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 125665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::svc(uint32_t imm24) { 1257ab1eb0d1d047e3478ebb891e5259d2f1d1dd78bdAndreas Gampe CHECK(IsUint<24>(imm24)) << imm24; 125865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (AL << kConditionShift) | B27 | B26 | B25 | B24 | imm24; 125965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 126065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 126165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 126265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 126365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::bkpt(uint16_t imm16) { 126465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (AL << kConditionShift) | B24 | B21 | 126565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf); 126665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 126765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 126865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 126965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 127065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::blx(Register rm, Condition cond) { 127165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 127265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 127365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 127465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | B21 | (0xfff << 8) | B5 | B4 | 127565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << kRmShift); 127665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 127765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 127865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 127965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 128065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::bx(Register rm, Condition cond) { 128165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 128265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 128365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 128465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | B21 | (0xfff << 8) | B4 | 128565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << kRmShift); 128665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 128765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 128865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 128965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 129065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Push(Register rd, Condition cond) { 129165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond); 129265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 129365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 129465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 129565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Pop(Register rd, Condition cond) { 129665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond); 129765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 129865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 129965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 130065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::PushList(RegList regs, Condition cond) { 130165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison stm(DB_W, SP, regs, cond); 130265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 130365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 130465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 130565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::PopList(RegList regs, Condition cond) { 130665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldm(IA_W, SP, regs, cond); 130765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 130865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 130965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 131065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Mov(Register rd, Register rm, Condition cond) { 131165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (rd != rm) { 131265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mov(rd, ShifterOperand(rm), cond); 131365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 131465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 131565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 131665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 131765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Bind(Label* label) { 131865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(!label->IsBound()); 131965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int bound_pc = buffer_.Size(); 132065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison while (label->IsLinked()) { 132165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t position = label->Position(); 132265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t next = buffer_.Load<int32_t>(position); 132365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoded = Arm32Assembler::EncodeBranchOffset(bound_pc - position, next); 132465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison buffer_.Store<int32_t>(position, encoded); 132565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison label->position_ = Arm32Assembler::DecodeBranchOffset(next); 132665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 132765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison label->BindTo(bound_pc); 132865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 132965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 133065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 133165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonint32_t Arm32Assembler::EncodeBranchOffset(int offset, int32_t inst) { 133265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // The offset is off by 8 due to the way the ARM CPUs read PC. 133365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset -= 8; 133465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_ALIGNED(offset, 4); 133565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(IsInt(POPCOUNT(kBranchOffsetMask), offset)) << offset; 133665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 133765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Properly preserve only the bits supported in the instruction. 133865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset >>= 2; 133965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset &= kBranchOffsetMask; 134065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return (inst & ~kBranchOffsetMask) | offset; 134165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 134265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 134365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 134465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonint Arm32Assembler::DecodeBranchOffset(int32_t inst) { 134565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Sign-extend, left-shift by 2, then add 8. 134665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return ((((inst & kBranchOffsetMask) << 8) >> 6) + 8); 134765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 134865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 134965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 135065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::AddConstant(Register rd, int32_t value, Condition cond) { 135165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison AddConstant(rd, rd, value, cond); 135265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 135365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 135465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 135565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::AddConstant(Register rd, Register rn, int32_t value, 135665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 135765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (value == 0) { 135865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (rd != rn) { 135965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mov(rd, ShifterOperand(rn), cond); 136065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 136165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return; 136265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 136365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // We prefer to select the shorter code sequence rather than selecting add for 136465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // positive values and sub for negatives ones, which would slightly improve 136565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // the readability of generated code for some constants. 136665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ShifterOperand shifter_op; 13673bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray if (ShifterOperandCanHoldArm32(value, &shifter_op)) { 136865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(rd, rn, shifter_op, cond); 13693bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray } else if (ShifterOperandCanHoldArm32(-value, &shifter_op)) { 137065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison sub(rd, rn, shifter_op, cond); 137165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 137265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(rn != IP); 13733bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray if (ShifterOperandCanHoldArm32(~value, &shifter_op)) { 137465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(IP, shifter_op, cond); 137565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(rd, rn, ShifterOperand(IP), cond); 13763bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray } else if (ShifterOperandCanHoldArm32(~(-value), &shifter_op)) { 137765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(IP, shifter_op, cond); 137865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison sub(rd, rn, ShifterOperand(IP), cond); 137965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 138065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movw(IP, Low16Bits(value), cond); 138165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint16_t value_high = High16Bits(value); 138265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (value_high != 0) { 138365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movt(IP, value_high, cond); 138465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 138565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(rd, rn, ShifterOperand(IP), cond); 138665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 138765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 138865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 138965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 139065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 139165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::AddConstantSetFlags(Register rd, Register rn, int32_t value, 139265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 139365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ShifterOperand shifter_op; 13943bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray if (ShifterOperandCanHoldArm32(value, &shifter_op)) { 139565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison adds(rd, rn, shifter_op, cond); 13963bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray } else if (ShifterOperandCanHoldArm32(-value, &shifter_op)) { 139765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison subs(rd, rn, shifter_op, cond); 139865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 139965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(rn != IP); 14003bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray if (ShifterOperandCanHoldArm32(~value, &shifter_op)) { 140165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(IP, shifter_op, cond); 140265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison adds(rd, rn, ShifterOperand(IP), cond); 14033bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray } else if (ShifterOperandCanHoldArm32(~(-value), &shifter_op)) { 140465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(IP, shifter_op, cond); 140565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison subs(rd, rn, ShifterOperand(IP), cond); 140665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 140765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movw(IP, Low16Bits(value), cond); 140865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint16_t value_high = High16Bits(value); 140965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (value_high != 0) { 141065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movt(IP, value_high, cond); 141165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 141265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison adds(rd, rn, ShifterOperand(IP), cond); 141365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 141465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 141565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 141665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 141765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) { 141865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ShifterOperand shifter_op; 14193bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray if (ShifterOperandCanHoldArm32(value, &shifter_op)) { 142065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mov(rd, shifter_op, cond); 14213bcc8ea079d867f26622defd0611d134a3b4ae49Nicolas Geoffray } else if (ShifterOperandCanHoldArm32(~value, &shifter_op)) { 142265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(rd, shifter_op, cond); 142365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 142465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movw(rd, Low16Bits(value), cond); 142565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint16_t value_high = High16Bits(value); 142665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (value_high != 0) { 142765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movt(rd, value_high, cond); 142865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 142965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 143065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 143165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 143265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 143365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 143465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldLoadOffsetArm. 143565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::LoadFromOffset(LoadOperandType type, 143665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register reg, 143765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 143865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 143965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 144065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldLoadOffsetArm(type, offset)) { 144165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(base != IP); 144265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 144365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 144465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 144565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 144665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 144765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldLoadOffsetArm(type, offset)); 144865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison switch (type) { 144965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadSignedByte: 145065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrsb(reg, Address(base, offset), cond); 145165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 145265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadUnsignedByte: 145365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrb(reg, Address(base, offset), cond); 145465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 145565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadSignedHalfword: 145665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrsh(reg, Address(base, offset), cond); 145765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 145865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadUnsignedHalfword: 145965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrh(reg, Address(base, offset), cond); 146065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 146165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadWord: 146265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldr(reg, Address(base, offset), cond); 146365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 146465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadWordPair: 146565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrd(reg, Address(base, offset), cond); 146665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 146765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison default: 146865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LOG(FATAL) << "UNREACHABLE"; 14692c4257be8191c5eefde744e8965fcefc80a0a97dIan Rogers UNREACHABLE(); 147065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 147165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 147265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 147365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 147465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 147565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldLoadOffsetArm, as expected by JIT::GuardedLoadFromOffset. 147665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::LoadSFromOffset(SRegister reg, 147765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 147865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 147965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 148065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldLoadOffsetArm(kLoadSWord, offset)) { 148165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, IP); 148265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 148365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 148465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 148565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 148665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 148765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldLoadOffsetArm(kLoadSWord, offset)); 148865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison vldrs(reg, Address(base, offset), cond); 148965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 149065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 149165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 149265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 149365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldLoadOffsetArm, as expected by JIT::GuardedLoadFromOffset. 149465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::LoadDFromOffset(DRegister reg, 149565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 149665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 149765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 149865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldLoadOffsetArm(kLoadDWord, offset)) { 149965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, IP); 150065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 150165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 150265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 150365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 150465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 150565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldLoadOffsetArm(kLoadDWord, offset)); 150665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison vldrd(reg, Address(base, offset), cond); 150765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 150865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 150965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 151065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 151165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldStoreOffsetArm. 151265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::StoreToOffset(StoreOperandType type, 151365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register reg, 151465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 151565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 151665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 151765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldStoreOffsetArm(type, offset)) { 151865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(reg != IP); 151965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(base != IP); 152065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 152165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 152265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 152365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 152465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 152565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldStoreOffsetArm(type, offset)); 152665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison switch (type) { 152765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kStoreByte: 152865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison strb(reg, Address(base, offset), cond); 152965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 153065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kStoreHalfword: 153165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison strh(reg, Address(base, offset), cond); 153265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 153365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kStoreWord: 153465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison str(reg, Address(base, offset), cond); 153565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 153665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kStoreWordPair: 153765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison strd(reg, Address(base, offset), cond); 153865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 153965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison default: 154065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LOG(FATAL) << "UNREACHABLE"; 15412c4257be8191c5eefde744e8965fcefc80a0a97dIan Rogers UNREACHABLE(); 154265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 154365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 154465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 154565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 154665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 154765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldStoreOffsetArm, as expected by JIT::GuardedStoreToOffset. 154865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::StoreSToOffset(SRegister reg, 154965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 155065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 155165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 155265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldStoreOffsetArm(kStoreSWord, offset)) { 155365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, IP); 155465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 155565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 155665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 155765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 155865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 155965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldStoreOffsetArm(kStoreSWord, offset)); 156065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison vstrs(reg, Address(base, offset), cond); 156165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 156265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 156365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 156465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 156565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldStoreOffsetArm, as expected by JIT::GuardedStoreSToOffset. 156665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::StoreDToOffset(DRegister reg, 156765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 156865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 156965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 157065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldStoreOffsetArm(kStoreDWord, offset)) { 157165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, IP); 157265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 157365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 157465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 157565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 157665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 157765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldStoreOffsetArm(kStoreDWord, offset)); 157865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison vstrd(reg, Address(base, offset), cond); 157965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 158065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 158165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 158265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::MemoryBarrier(ManagedRegister mscratch) { 158365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_EQ(mscratch.AsArm().AsCoreRegister(), R12); 158419a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray dmb(SY); 158519a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray} 158619a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray 158719a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray 158819a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffrayvoid Arm32Assembler::dmb(DmbOptions flavor) { 158965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = 0xf57ff05f; // dmb 159019a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray Emit(encoding | flavor); 159165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 159265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 159365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15946a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866fIan Rogersvoid Arm32Assembler::cbz(Register rn ATTRIBUTE_UNUSED, Label* target ATTRIBUTE_UNUSED) { 159565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LOG(FATAL) << "cbz is not supported on ARM32"; 159665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 159765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 159865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15996a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866fIan Rogersvoid Arm32Assembler::cbnz(Register rn ATTRIBUTE_UNUSED, Label* target ATTRIBUTE_UNUSED) { 160065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LOG(FATAL) << "cbnz is not supported on ARM32"; 160165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 160265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 160365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 160465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::CompareAndBranchIfZero(Register r, Label* label) { 160565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison cmp(r, ShifterOperand(0)); 160665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison b(label, EQ); 160765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 160865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 160965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 161065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::CompareAndBranchIfNonZero(Register r, Label* label) { 161165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison cmp(r, ShifterOperand(0)); 161265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison b(label, NE); 161365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 161465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 161565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 161665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} // namespace arm 161765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} // namespace art 1618