assembler_arm32.cc revision 981e45424f52735b1c61ae0eac7e299ed313f8db
165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison/* 265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * Copyright (C) 2014 The Android Open Source Project 365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * 465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * Licensed under the Apache License, Version 2.0 (the "License"); 565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * you may not use this file except in compliance with the License. 665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * You may obtain a copy of the License at 765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * 865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * http://www.apache.org/licenses/LICENSE-2.0 965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * 1065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * Unless required by applicable law or agreed to in writing, software 1165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * distributed under the License is distributed on an "AS IS" BASIS, 1265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * See the License for the specific language governing permissions and 1465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison * limitations under the License. 1565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison */ 1665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 1765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "assembler_arm32.h" 1865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 1965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "base/logging.h" 2065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "entrypoints/quick/quick_entrypoints.h" 2165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "offsets.h" 2265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "thread.h" 2365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#include "utils.h" 2465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 2565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonnamespace art { 2665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonnamespace arm { 2765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 2865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, 2965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 3065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), AND, 0, rn, rd, so); 3165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 3265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 3365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 3465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, 3565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 3665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), EOR, 0, rn, rd, so); 3765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 3865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 3965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 4065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, 4165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 4265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), SUB, 0, rn, rd, so); 4365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 4465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 4565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, 4665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 4765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), RSB, 0, rn, rd, so); 4865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 4965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 5065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so, 5165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 5265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), RSB, 1, rn, rd, so); 5365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 5465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 5565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 5665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::add(Register rd, Register rn, const ShifterOperand& so, 5765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 5865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ADD, 0, rn, rd, so); 5965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 6065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 6165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 6265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::adds(Register rd, Register rn, const ShifterOperand& so, 6365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 6465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ADD, 1, rn, rd, so); 6565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 6665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 6765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 6865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::subs(Register rd, Register rn, const ShifterOperand& so, 6965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 7065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), SUB, 1, rn, rd, so); 7165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 7265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 7365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 7465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::adc(Register rd, Register rn, const ShifterOperand& so, 7565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 7665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ADC, 0, rn, rd, so); 7765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 7865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 7965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 8065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::sbc(Register rd, Register rn, const ShifterOperand& so, 8165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 8265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), SBC, 0, rn, rd, so); 8365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 8465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 8565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 8665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::rsc(Register rd, Register rn, const ShifterOperand& so, 8765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 8865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), RSC, 0, rn, rd, so); 8965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 9065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 9165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 9265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::tst(Register rn, const ShifterOperand& so, Condition cond) { 9365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. 9465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), TST, 1, rn, R0, so); 9565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 9665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 9765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 9865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::teq(Register rn, const ShifterOperand& so, Condition cond) { 9965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. 10065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), TEQ, 1, rn, R0, so); 10165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 10265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 10365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 10465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::cmp(Register rn, const ShifterOperand& so, Condition cond) { 10565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), CMP, 1, rn, R0, so); 10665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 10765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 10865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 10965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::cmn(Register rn, const ShifterOperand& so, Condition cond) { 11065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), CMN, 1, rn, R0, so); 11165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 11265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 11365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 11465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::orr(Register rd, Register rn, 11565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so, Condition cond) { 11665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ORR, 0, rn, rd, so); 11765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 11865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 11965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 12065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::orrs(Register rd, Register rn, 12165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so, Condition cond) { 12265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), ORR, 1, rn, rd, so); 12365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 12465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 12565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 12665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mov(Register rd, const ShifterOperand& so, Condition cond) { 12765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), MOV, 0, R0, rd, so); 12865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 12965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 13065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 13165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::movs(Register rd, const ShifterOperand& so, Condition cond) { 13265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), MOV, 1, R0, rd, so); 13365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 13465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 13565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 13665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::bic(Register rd, Register rn, const ShifterOperand& so, 13765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 13865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), BIC, 0, rn, rd, so); 13965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 14065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 14165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 14265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mvn(Register rd, const ShifterOperand& so, Condition cond) { 14365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), MVN, 0, R0, rd, so); 14465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 14565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 14665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 14765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mvns(Register rd, const ShifterOperand& so, Condition cond) { 14865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(cond, so.type(), MVN, 1, R0, rd, so); 14965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 15065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { 15365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Assembler registers rd, rn, rm are encoded as rn, rm, rs. 15465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMulOp(cond, 0, R0, rd, rn, rm); 15565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 15665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mla(Register rd, Register rn, Register rm, Register ra, 15965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 16065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 16165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMulOp(cond, B21, ra, rd, rn, rm); 16265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 16365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 16465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 16565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::mls(Register rd, Register rn, Register rm, Register ra, 16665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 16765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 16865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMulOp(cond, B22 | B21, ra, rd, rn, rm); 16965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 17065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 17165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 17265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::umull(Register rd_lo, Register rd_hi, Register rn, 17365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rm, Condition cond) { 17465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 17565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm); 17665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 17765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 17865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 17965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) { 18065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 18165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 18265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 18365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 18465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = B26 | B25 | B24 | B20 | 18565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B15 | B14 | B13 | B12 | 18665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(cond) << kConditionShift) | 18765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << 0) | 18865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << 16) | 18965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << 8) | 19065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B4; 19165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 19265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 19365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 19465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 19565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) { 19665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 19765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 19865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 19965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 20065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = B26 | B25 | B24 | B21 | B20 | 20165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B15 | B14 | B13 | B12 | 20265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(cond) << kConditionShift) | 20365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << 0) | 20465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << 16) | 20565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << 8) | 20665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B4; 20765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 20865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 20965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 21065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 21151d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillainvoid Arm32Assembler::sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) { 21251d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK_NE(rd, kNoRegister); 21351d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK_NE(rn, kNoRegister); 21451d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK_NE(cond, kNoCondition); 21551d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK_LE(lsb, 31U); 21651d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain CHECK(1U <= width && width <= 32U) << width; 21751d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain uint32_t widthminus1 = width - 1; 21851d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain 21951d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 22051d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain B26 | B25 | B24 | B23 | B21 | 22151d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain (widthminus1 << 16) | 22251d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain (static_cast<uint32_t>(rd) << 12) | 22351d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain (lsb << 7) | 22451d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain B6 | B4 | 22551d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain static_cast<uint32_t>(rn); 22651d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain Emit(encoding); 22751d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain} 22851d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain 22951d3fc40637fc73d4156ad617cd451b844cbb75eRoland Levillain 230981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillainvoid Arm32Assembler::ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) { 231981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK_NE(rd, kNoRegister); 232981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK_NE(rn, kNoRegister); 233981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK_NE(cond, kNoCondition); 234981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK_LE(lsb, 31U); 235981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain CHECK(1U <= width && width <= 32U) << width; 236981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain uint32_t widthminus1 = width - 1; 237981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain 238981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 239981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain B26 | B25 | B24 | B23 | B22 | B21 | 240981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain (widthminus1 << 16) | 241981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain (static_cast<uint32_t>(rd) << 12) | 242981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain (lsb << 7) | 243981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain B6 | B4 | 244981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain static_cast<uint32_t>(rn); 245981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain Emit(encoding); 246981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain} 247981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain 248981e45424f52735b1c61ae0eac7e299ed313f8dbRoland Levillain 24965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldr(Register rd, const Address& ad, Condition cond) { 25065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOp(cond, true, false, rd, ad); 25165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 25265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 25365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 25465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::str(Register rd, const Address& ad, Condition cond) { 25565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOp(cond, false, false, rd, ad); 25665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 25765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 25865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 25965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrb(Register rd, const Address& ad, Condition cond) { 26065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOp(cond, true, true, rd, ad); 26165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 26265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 26365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 26465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::strb(Register rd, const Address& ad, Condition cond) { 26565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOp(cond, false, true, rd, ad); 26665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 26765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 26865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 26965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrh(Register rd, const Address& ad, Condition cond) { 27065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad); 27165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 27265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 27365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 27465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::strh(Register rd, const Address& ad, Condition cond) { 27565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad); 27665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 27765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 27865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 27965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrsb(Register rd, const Address& ad, Condition cond) { 28065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad); 28165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 28265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 28365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 28465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrsh(Register rd, const Address& ad, Condition cond) { 28565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad); 28665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 28765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 28865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 28965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrd(Register rd, const Address& ad, Condition cond) { 29065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_EQ(rd % 2, 0); 29165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad); 29265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 29365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 29465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 29565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::strd(Register rd, const Address& ad, Condition cond) { 29665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_EQ(rd % 2, 0); 29765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad); 29865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 29965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 30065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 30165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldm(BlockAddressMode am, 30265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 30365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison RegList regs, 30465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 30565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMultiMemOp(cond, am, true, base, regs); 30665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 30765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 30865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 30965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::stm(BlockAddressMode am, 31065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 31165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison RegList regs, 31265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 31365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitMultiMemOp(cond, am, false, base, regs); 31465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 31565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 31665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 31765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovs(SRegister sd, SRegister sm, Condition cond) { 31865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm); 31965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 32065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 32165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 32265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) { 32365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm); 32465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 32565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 32665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 32765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonbool Arm32Assembler::vmovs(SRegister sd, float s_imm, Condition cond) { 32865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint32_t imm32 = bit_cast<uint32_t, float>(s_imm); 32965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (((imm32 & ((1 << 19) - 1)) == 0) && 33065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) || 33165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) -1)))) { 33265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint8_t imm8 = ((imm32 >> 31) << 7) | (((imm32 >> 29) & 1) << 6) | 33365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((imm32 >> 19) & ((1 << 6) -1)); 33465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf), 33565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison sd, S0, S0); 33665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return true; 33765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 33865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return false; 33965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 34065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 34165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 34265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonbool Arm32Assembler::vmovd(DRegister dd, double d_imm, Condition cond) { 34365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint64_t imm64 = bit_cast<uint64_t, double>(d_imm); 34465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (((imm64 & ((1LL << 48) - 1)) == 0) && 34565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) || 34665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) -1)))) { 34765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint8_t imm8 = ((imm64 >> 63) << 7) | (((imm64 >> 61) & 1) << 6) | 34865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((imm64 >> 48) & ((1 << 6) -1)); 34965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf), 35065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison dd, D0, D0); 35165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return true; 35265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 35365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return false; 35465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 35565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 35665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 35765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vadds(SRegister sd, SRegister sn, SRegister sm, 35865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 35965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B21 | B20, sd, sn, sm); 36065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 36165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 36265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 36365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm, 36465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 36565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B21 | B20, dd, dn, dm); 36665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 36765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 36865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 36965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vsubs(SRegister sd, SRegister sn, SRegister sm, 37065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 37165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm); 37265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 37365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 37465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 37565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm, 37665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 37765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm); 37865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 37965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 38065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 38165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmuls(SRegister sd, SRegister sn, SRegister sm, 38265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 38365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B21, sd, sn, sm); 38465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 38565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 38665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 38765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm, 38865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 38965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B21, dd, dn, dm); 39065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 39165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 39265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 39365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmlas(SRegister sd, SRegister sn, SRegister sm, 39465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 39565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, 0, sd, sn, sm); 39665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 39765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 39865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 39965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmlad(DRegister dd, DRegister dn, DRegister dm, 40065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 40165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, 0, dd, dn, dm); 40265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 40365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 40465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 40565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmlss(SRegister sd, SRegister sn, SRegister sm, 40665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 40765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B6, sd, sn, sm); 40865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 40965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 41065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 41165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmlsd(DRegister dd, DRegister dn, DRegister dm, 41265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 41365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B6, dd, dn, dm); 41465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 41565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 41665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 41765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vdivs(SRegister sd, SRegister sn, SRegister sm, 41865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 41965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23, sd, sn, sm); 42065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 42165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 42265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 42365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vdivd(DRegister dd, DRegister dn, DRegister dm, 42465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 42565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23, dd, dn, dm); 42665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 42765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 42865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 42965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vabss(SRegister sd, SRegister sm, Condition cond) { 43065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm); 43165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 43265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 43365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 43465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vabsd(DRegister dd, DRegister dm, Condition cond) { 43565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm); 43665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 43765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 43865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 43965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vnegs(SRegister sd, SRegister sm, Condition cond) { 44065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm); 44165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 44265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 44365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 44465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vnegd(DRegister dd, DRegister dm, Condition cond) { 44565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm); 44665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 44765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 44865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 44965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vsqrts(SRegister sd, SRegister sm, Condition cond) { 45065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm); 45165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 45265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 45365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) { 45465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm); 45565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 45665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 45765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 45865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) { 45965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm); 46065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 46165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 46265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 46365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtds(DRegister dd, SRegister sm, Condition cond) { 46465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm); 46565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 46665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 46765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 46865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtis(SRegister sd, SRegister sm, Condition cond) { 46965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); 47065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 47165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 47265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 47365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtid(SRegister sd, DRegister dm, Condition cond) { 47465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm); 47565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 47665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 47765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 47865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) { 47965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); 48065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 48165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 48265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 48365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) { 48465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm); 48565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 48665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 48765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 48865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtus(SRegister sd, SRegister sm, Condition cond) { 48965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); 49065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 49165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 49265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 49365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtud(SRegister sd, DRegister dm, Condition cond) { 49465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm); 49565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 49665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 49765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 49865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) { 49965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm); 50065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 50165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 50265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 50365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) { 50465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm); 50565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 50665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 50765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 50865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) { 50965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm); 51065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 51165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 51265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 51365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcmpd(DRegister dd, DRegister dm, Condition cond) { 51465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm); 51565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 51665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 51765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 51865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcmpsz(SRegister sd, Condition cond) { 51965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0); 52065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 52165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 52265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 52365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vcmpdz(DRegister dd, Condition cond) { 52465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0); 52565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 52665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 52765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::b(Label* label, Condition cond) { 52865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitBranch(cond, label, false); 52965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 53065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 53165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 53265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::bl(Label* label, Condition cond) { 53365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitBranch(cond, label, true); 53465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 53565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 53665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 53765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::MarkExceptionHandler(Label* label) { 53865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0)); 53965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Label l; 54065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison b(&l); 54165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitBranch(AL, label, false); 54265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Bind(&l); 54365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 54465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 54565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 54665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Emit(int32_t value) { 54765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison AssemblerBuffer::EnsureCapacity ensured(&buffer_); 54865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison buffer_.Emit<int32_t>(value); 54965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 55065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 55165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 55265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitType01(Condition cond, 55365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int type, 55465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Opcode opcode, 55565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int set_cc, 55665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rn, 55765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, 55865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so) { 55965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 56065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 56165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 56265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison type << kTypeShift | 56365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(opcode) << kOpcodeShift | 56465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison set_cc << kSShift | 56565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rn) << kRnShift | 56665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | 56765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison so.encodingArm(); 56865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 56965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 57065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 57165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 57265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitType5(Condition cond, int offset, bool link) { 57365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 57465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 57565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 5 << kTypeShift | 57665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (link ? 1 : 0) << kLinkShift; 57765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(Arm32Assembler::EncodeBranchOffset(offset, encoding)); 57865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 57965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 58065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 58165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitMemOp(Condition cond, 58245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool load, 58345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool byte, 58445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison Register rd, 58545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison const Address& ad) { 58665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 58765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 58865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 58965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 59045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison int32_t encoding = 0; 59145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (!ad.IsImmediate() && ad.GetRegisterOffset() == PC) { 59245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison // PC relative LDR(literal) 59345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison int32_t offset = ad.GetOffset(); 59445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison int32_t u = B23; 59545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (offset < 0) { 59645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison offset = -offset; 59745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison u = 0; 59845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 59945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison CHECK_LT(offset, (1 << 12)); 60045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison encoding = (static_cast<int32_t>(cond) << kConditionShift) | 60145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison B26 | B24 | u | B20 | 60245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (load ? L : 0) | 60345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (byte ? B : 0) | 60445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 60545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 0xf << 16 | 60645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (offset & 0xfff); 60745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 60845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 60945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison encoding = (static_cast<int32_t>(cond) << kConditionShift) | 61045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison B26 | 61145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (load ? L : 0) | 61245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (byte ? B : 0) | 61345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 61445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison addr.encodingArm(); 61545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 61665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 61765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 61865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 61965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 62065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitMemOpAddressMode3(Condition cond, 62165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t mode, 62265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, 62365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& ad) { 62465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 62565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 62665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 62765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 62865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B22 | 62965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mode | 63065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 63165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison addr.encoding3(); 63265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 63365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 63465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 63565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 63665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitMultiMemOp(Condition cond, 63765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison BlockAddressMode am, 63865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison bool load, 63965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 64065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison RegList regs) { 64165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, kNoRegister); 64265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 64365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 64465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | 64565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison am | 64665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (load ? L : 0) | 64765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(base) << kRnShift) | 64865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison regs; 64965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 65065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 65165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 65265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 65365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitShiftImmediate(Condition cond, 65465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Shift opcode, 65565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, 65665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rm, 65765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so) { 65865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 65965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(so.IsImmediate()); 66065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 66165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(MOV) << kOpcodeShift | 66265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | 66365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison so.encodingArm() << kShiftImmShift | 66465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(opcode) << kShiftShift | 66565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rm); 66665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 66765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 66865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 66965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 67065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitShiftRegister(Condition cond, 67165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Shift opcode, 67265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, 67365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rm, 67465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const ShifterOperand& so) { 67565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 67665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(so.IsRegister()); 67765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 67865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(MOV) << kOpcodeShift | 67965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | 68065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison so.encodingArm() << kShiftRegisterShift | 68165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(opcode) << kShiftShift | 68265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B4 | 68365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rm); 68465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 68565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 68665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 68765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 68865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitBranch(Condition cond, Label* label, bool link) { 68965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (label->IsBound()) { 69065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType5(cond, label->Position() - buffer_.Size(), link); 69165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 69265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int position = buffer_.Size(); 69365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Use the offset field of the branch instruction for linking the sites. 69465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitType5(cond, label->position_, link); 69565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison label->LinkTo(position); 69665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 69765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 69865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 69965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 70065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::clz(Register rd, Register rm, Condition cond) { 70165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 70265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 70365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 70465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, PC); 70565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, PC); 70665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 70765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | B22 | B21 | (0xf << 16) | 70865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 70965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (0xf << 8) | B4 | static_cast<int32_t>(rm); 71065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 71165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 71265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 71365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 71465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::movw(Register rd, uint16_t imm16, Condition cond) { 71565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 71665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 71765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B25 | B24 | ((imm16 >> 12) << 16) | 71865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); 71965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 72065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 72165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 72265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 72365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::movt(Register rd, uint16_t imm16, Condition cond) { 72465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 72565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 72665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B25 | B24 | B22 | ((imm16 >> 12) << 16) | 72765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); 72865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 72965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 73065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 73165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 73265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitMulOp(Condition cond, int32_t opcode, 73365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rd, Register rn, 73465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rm, Register rs) { 73565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 73665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 73765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 73865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rs, kNoRegister); 73965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 74065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = opcode | 74165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(cond) << kConditionShift) | 74265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << kRnShift) | 74365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << kRdShift) | 74465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rs) << kRsShift) | 74565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B7 | B4 | 74665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << kRmShift); 74765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 74865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 74965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 75065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::ldrex(Register rt, Register rn, Condition cond) { 75165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 75265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 75365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 75465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 75565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | 75665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B23 | 75765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison L | 75865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << kLdExRnShift) | 75965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt) << kLdExRtShift) | 76065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0; 76165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 76265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 76365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 76465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 76565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::strex(Register rd, 76665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rt, 76765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register rn, 76865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 76965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rn, kNoRegister); 77065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rd, kNoRegister); 77165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 77265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 77365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 77465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | 77565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B23 | 77665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rn) << kStrExRnShift) | 77765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rd) << kStrExRdShift) | 77865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B10 | B9 | B8 | B7 | B4 | 77965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt) << kStrExRtShift); 78065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 78165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 78265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 78365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 78465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::clrex(Condition cond) { 78565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_EQ(cond, AL); // This cannot be conditional on ARM. 78665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (kSpecialCondition << kConditionShift) | 78765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf; 78865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 78965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 79065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 79165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 79265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::nop(Condition cond) { 79365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 79465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 79565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B25 | B24 | B21 | (0xf << 12); 79665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 79765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 79865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 79965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 80065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovsr(SRegister sn, Register rt, Condition cond) { 80165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sn, kNoSRegister); 80265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 80365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 80465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 80565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 80665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 80765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | 80865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) >> 1)*B16) | 80965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | 81065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) & 1)*B7) | B4; 81165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 81265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 81365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 81465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 81565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovrs(Register rt, SRegister sn, Condition cond) { 81665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sn, kNoSRegister); 81765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 81865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 81965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 82065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 82165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 82265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B20 | 82365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) >> 1)*B16) | 82465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | 82565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) & 1)*B7) | B4; 82665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 82765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 82865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 82965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 83065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovsrr(SRegister sm, Register rt, Register rt2, 83165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 83265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, kNoSRegister); 83365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, S31); 83465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 83565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 83665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 83765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, kNoRegister); 83865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, SP); 83965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, PC); 84065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 84165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 84265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B22 | 84365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt2)*B16) | 84465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | 84565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sm) & 1)*B5) | B4 | 84665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(sm) >> 1); 84765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 84865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 84965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 85065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 85165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovrrs(Register rt, Register rt2, SRegister sm, 85265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 85365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, kNoSRegister); 85465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, S31); 85565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 85665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 85765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 85865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, kNoRegister); 85965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, SP); 86065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, PC); 86165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, rt2); 86265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 86365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 86465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B22 | B20 | 86565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt2)*B16) | 86665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | 86765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sm) & 1)*B5) | B4 | 86865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(sm) >> 1); 86965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 87065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 87165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 87265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 87365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovdrr(DRegister dm, Register rt, Register rt2, 87465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 87565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dm, kNoDRegister); 87665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 87765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 87865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 87965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, kNoRegister); 88065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, SP); 88165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, PC); 88265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 88365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 88465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B22 | 88565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt2)*B16) | 88665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | 88765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | 88865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(dm) & 0xf); 88965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 89065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 89165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 89265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 89365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmovrrd(Register rt, Register rt2, DRegister dm, 89465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 89565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dm, kNoDRegister); 89665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, kNoRegister); 89765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, SP); 89865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, PC); 89965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, kNoRegister); 90065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, SP); 90165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt2, PC); 90265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rt, rt2); 90365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 90465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 90565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B22 | B20 | 90665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt2)*B16) | 90765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | 90865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | 90965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(dm) & 0xf); 91065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 91165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 91265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 91365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 91465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vldrs(SRegister sd, const Address& ad, Condition cond) { 91565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 91665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sd, kNoSRegister); 91765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 91865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 91965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B24 | B20 | 92065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) & 1)*B22) | 92165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) >> 1)*B12) | 92265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | addr.vencoding(); 92365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 92465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 92565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 92665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 92765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vstrs(SRegister sd, const Address& ad, Condition cond) { 92865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 92965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); 93065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sd, kNoSRegister); 93165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 93265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 93365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B24 | 93465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) & 1)*B22) | 93565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) >> 1)*B12) | 93665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | addr.vencoding(); 93765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 93865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 93965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 94065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 94165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vldrd(DRegister dd, const Address& ad, Condition cond) { 94265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 94365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dd, kNoDRegister); 94465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 94565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 94665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B24 | B20 | 94765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) >> 4)*B22) | 94865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) & 0xf)*B12) | 94965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | B8 | addr.vencoding(); 95065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 95165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 95265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 95365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 95465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vstrd(DRegister dd, const Address& ad, Condition cond) { 95565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison const Address& addr = static_cast<const Address&>(ad); 95665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); 95765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dd, kNoDRegister); 95865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 95965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 96065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B24 | 96165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) >> 4)*B22) | 96265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) & 0xf)*B12) | 96365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | B8 | addr.vencoding(); 96465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 96565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 96665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 96765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 96865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vpushs(SRegister reg, int nregs, Condition cond) { 96965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, false, cond); 97065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 97165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 97265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 97365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vpushd(DRegister reg, int nregs, Condition cond) { 97465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, true, cond); 97565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 97665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 97765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 97865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vpops(SRegister reg, int nregs, Condition cond) { 97965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, false, cond); 98065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 98165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 98265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 98365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vpopd(DRegister reg, int nregs, Condition cond) { 98465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, true, cond); 98565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 98665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 98765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 98865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVPushPop(uint32_t reg, int nregs, bool push, bool dbl, Condition cond) { 98965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 99065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_GT(nregs, 0); 99165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint32_t D; 99265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint32_t Vd; 99365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (dbl) { 99465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Encoded as D:Vd. 99565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison D = (reg >> 4) & 1; 996c8ccf68b805c92674545f63e0341ba47e8d9701cAndreas Gampe Vd = reg & 15U /* 0b1111 */; 99765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 99865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Encoded as Vd:D. 99965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison D = reg & 1; 1000c8ccf68b805c92674545f63e0341ba47e8d9701cAndreas Gampe Vd = (reg >> 1) & 15U /* 0b1111 */; 100165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 100265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = B27 | B26 | B21 | B19 | B18 | B16 | 100365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | 100465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (dbl ? B8 : 0) | 100565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (push ? B24 : (B23 | B20)) | 100665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison static_cast<int32_t>(cond) << kConditionShift | 100765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison nregs << (dbl ? 1 : 0) | 100865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison D << 22 | 100965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Vd << 12; 101065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 101165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 101265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 101365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 101465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVFPsss(Condition cond, int32_t opcode, 101565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison SRegister sd, SRegister sn, SRegister sm) { 101665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sd, kNoSRegister); 101765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sn, kNoSRegister); 101865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, kNoSRegister); 101965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 102065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 102165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B11 | B9 | opcode | 102265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) & 1)*B22) | 102365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) >> 1)*B16) | 102465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) >> 1)*B12) | 102565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sn) & 1)*B7) | 102665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sm) & 1)*B5) | 102765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(sm) >> 1); 102865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 102965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 103065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 103165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 103265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVFPddd(Condition cond, int32_t opcode, 103365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison DRegister dd, DRegister dn, DRegister dm) { 103465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dd, kNoDRegister); 103565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dn, kNoDRegister); 103665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dm, kNoDRegister); 103765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 103865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 103965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B11 | B9 | B8 | opcode | 104065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) >> 4)*B22) | 104165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dn) & 0xf)*B16) | 104265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) & 0xf)*B12) | 104365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dn) >> 4)*B7) | 104465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dm) >> 4)*B5) | 104565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(dm) & 0xf); 104665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 104765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 104865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 104965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 105065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVFPsd(Condition cond, int32_t opcode, 105165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison SRegister sd, DRegister dm) { 105265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sd, kNoSRegister); 105365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dm, kNoDRegister); 105465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 105565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 105665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B11 | B9 | opcode | 105765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) & 1)*B22) | 105865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sd) >> 1)*B12) | 105965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dm) >> 4)*B5) | 106065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(dm) & 0xf); 106165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 106265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 106365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 106465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 106565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::EmitVFPds(Condition cond, int32_t opcode, 106665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison DRegister dd, SRegister sm) { 106765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(dd, kNoDRegister); 106865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(sm, kNoSRegister); 106965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 107065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 107165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B11 | B9 | opcode | 107265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) >> 4)*B22) | 107365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(dd) & 0xf)*B12) | 107465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((static_cast<int32_t>(sm) & 1)*B5) | 107565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(sm) >> 1); 107665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 107765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 107865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 107965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 108065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Lsl(Register rd, Register rm, uint32_t shift_imm, 108145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 108265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(shift_imm, 0u); // Do not use Lsl if no shift is wanted. 108345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 108445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, LSL, shift_imm), cond); 108545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 108645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, LSL, shift_imm), cond); 108745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 108865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 108965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 109065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 109165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Lsr(Register rd, Register rm, uint32_t shift_imm, 109245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 109365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(shift_imm, 0u); // Do not use Lsr if no shift is wanted. 109465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. 109545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 109645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, LSR, shift_imm), cond); 109745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 109845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, LSR, shift_imm), cond); 109945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 110065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 110165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 110265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 110365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Asr(Register rd, Register rm, uint32_t shift_imm, 110445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 110565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(shift_imm, 0u); // Do not use Asr if no shift is wanted. 110665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. 110745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 110845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ASR, shift_imm), cond); 110945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 111045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ASR, shift_imm), cond); 111145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 111265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 111365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 111465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 111565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Ror(Register rd, Register rm, uint32_t shift_imm, 111645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 111765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(shift_imm, 0u); // Use Rrx instruction. 111845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 111945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ROR, shift_imm), cond); 112045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 112145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ROR, shift_imm), cond); 112245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 112365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 112465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 112545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Rrx(Register rd, Register rm, bool setcc, Condition cond) { 112645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 112745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ROR, 0), cond); 112845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 112945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ROR, 0), cond); 113045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 113165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 113265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 113365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 113445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Lsl(Register rd, Register rm, Register rn, 113545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 113645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 113745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, LSL, rn), cond); 113845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 113945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, LSL, rn), cond); 114045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 114145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison} 114245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 114345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 114445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Lsr(Register rd, Register rm, Register rn, 114545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 114645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 114745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, LSR, rn), cond); 114845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 114945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, LSR, rn), cond); 115045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 115145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison} 115245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 115345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 115445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Asr(Register rd, Register rm, Register rn, 115545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 115645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 115745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ASR, rn), cond); 115845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 115945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ASR, rn), cond); 116045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 116145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison} 116245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 116345fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 116445fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allisonvoid Arm32Assembler::Ror(Register rd, Register rm, Register rn, 116545fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison bool setcc, Condition cond) { 116645fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison if (setcc) { 116745fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison movs(rd, ShifterOperand(rm, ROR, rn), cond); 116845fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } else { 116945fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison mov(rd, ShifterOperand(rm, ROR, rn), cond); 117045fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison } 117145fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison} 117245fdb93f04b981f70f7b6d98949ab3986b7331f8Dave Allison 117365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::vmstat(Condition cond) { // VMRS APSR_nzcv, FPSCR 117465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 117565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 117665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | 117765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(PC)*B12) | 117865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B11 | B9 | B4; 117965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 118065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 118165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 118265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 118365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::svc(uint32_t imm24) { 118465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(IsUint(24, imm24)) << imm24; 118565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (AL << kConditionShift) | B27 | B26 | B25 | B24 | imm24; 118665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 118765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 118865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 118965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 119065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::bkpt(uint16_t imm16) { 119165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (AL << kConditionShift) | B24 | B21 | 119265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf); 119365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 119465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 119565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 119665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 119765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::blx(Register rm, Condition cond) { 119865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 119965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 120065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 120165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | B21 | (0xfff << 8) | B5 | B4 | 120265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << kRmShift); 120365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 120465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 120565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 120665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 120765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::bx(Register rm, Condition cond) { 120865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(rm, kNoRegister); 120965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(cond, kNoCondition); 121065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 121165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison B24 | B21 | (0xfff << 8) | B4 | 121265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison (static_cast<int32_t>(rm) << kRmShift); 121365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Emit(encoding); 121465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 121565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 121665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 121765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Push(Register rd, Condition cond) { 121865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond); 121965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 122065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 122165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 122265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Pop(Register rd, Condition cond) { 122365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond); 122465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 122565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 122665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 122765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::PushList(RegList regs, Condition cond) { 122865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison stm(DB_W, SP, regs, cond); 122965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 123065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 123165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 123265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::PopList(RegList regs, Condition cond) { 123365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldm(IA_W, SP, regs, cond); 123465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 123565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 123665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 123765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Mov(Register rd, Register rm, Condition cond) { 123865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (rd != rm) { 123965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mov(rd, ShifterOperand(rm), cond); 124065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 124165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 124265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 124365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 124465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::Bind(Label* label) { 124565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(!label->IsBound()); 124665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int bound_pc = buffer_.Size(); 124765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison while (label->IsLinked()) { 124865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t position = label->Position(); 124965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t next = buffer_.Load<int32_t>(position); 125065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoded = Arm32Assembler::EncodeBranchOffset(bound_pc - position, next); 125165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison buffer_.Store<int32_t>(position, encoded); 125265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison label->position_ = Arm32Assembler::DecodeBranchOffset(next); 125365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 125465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison label->BindTo(bound_pc); 125565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 125665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 125765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 125865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonint32_t Arm32Assembler::EncodeBranchOffset(int offset, int32_t inst) { 125965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // The offset is off by 8 due to the way the ARM CPUs read PC. 126065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset -= 8; 126165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_ALIGNED(offset, 4); 126265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(IsInt(POPCOUNT(kBranchOffsetMask), offset)) << offset; 126365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 126465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Properly preserve only the bits supported in the instruction. 126565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset >>= 2; 126665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset &= kBranchOffsetMask; 126765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return (inst & ~kBranchOffsetMask) | offset; 126865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 126965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 127065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 127165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonint Arm32Assembler::DecodeBranchOffset(int32_t inst) { 127265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // Sign-extend, left-shift by 2, then add 8. 127365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return ((((inst & kBranchOffsetMask) << 8) >> 6) + 8); 127465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 127565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 127665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 127765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::AddConstant(Register rd, int32_t value, Condition cond) { 127865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison AddConstant(rd, rd, value, cond); 127965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 128065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 128165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 128265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::AddConstant(Register rd, Register rn, int32_t value, 128365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 128465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (value == 0) { 128565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (rd != rn) { 128665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mov(rd, ShifterOperand(rn), cond); 128765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 128865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison return; 128965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 129065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // We prefer to select the shorter code sequence rather than selecting add for 129165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // positive values and sub for negatives ones, which would slightly improve 129265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison // the readability of generated code for some constants. 129365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ShifterOperand shifter_op; 129465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (ShifterOperand::CanHoldArm(value, &shifter_op)) { 129565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(rd, rn, shifter_op, cond); 129665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else if (ShifterOperand::CanHoldArm(-value, &shifter_op)) { 129765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison sub(rd, rn, shifter_op, cond); 129865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 129965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(rn != IP); 130065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (ShifterOperand::CanHoldArm(~value, &shifter_op)) { 130165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(IP, shifter_op, cond); 130265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(rd, rn, ShifterOperand(IP), cond); 130365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else if (ShifterOperand::CanHoldArm(~(-value), &shifter_op)) { 130465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(IP, shifter_op, cond); 130565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison sub(rd, rn, ShifterOperand(IP), cond); 130665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 130765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movw(IP, Low16Bits(value), cond); 130865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint16_t value_high = High16Bits(value); 130965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (value_high != 0) { 131065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movt(IP, value_high, cond); 131165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 131265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(rd, rn, ShifterOperand(IP), cond); 131365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 131465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 131565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 131665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 131765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 131865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::AddConstantSetFlags(Register rd, Register rn, int32_t value, 131965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 132065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ShifterOperand shifter_op; 132165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (ShifterOperand::CanHoldArm(value, &shifter_op)) { 132265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison adds(rd, rn, shifter_op, cond); 132365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else if (ShifterOperand::CanHoldArm(-value, &shifter_op)) { 132465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison subs(rd, rn, shifter_op, cond); 132565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 132665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(rn != IP); 132765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (ShifterOperand::CanHoldArm(~value, &shifter_op)) { 132865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(IP, shifter_op, cond); 132965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison adds(rd, rn, ShifterOperand(IP), cond); 133065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else if (ShifterOperand::CanHoldArm(~(-value), &shifter_op)) { 133165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(IP, shifter_op, cond); 133265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison subs(rd, rn, ShifterOperand(IP), cond); 133365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 133465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movw(IP, Low16Bits(value), cond); 133565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint16_t value_high = High16Bits(value); 133665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (value_high != 0) { 133765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movt(IP, value_high, cond); 133865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 133965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison adds(rd, rn, ShifterOperand(IP), cond); 134065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 134165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 134265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 134365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 134465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) { 134565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ShifterOperand shifter_op; 134665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (ShifterOperand::CanHoldArm(value, &shifter_op)) { 134765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mov(rd, shifter_op, cond); 134865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else if (ShifterOperand::CanHoldArm(~value, &shifter_op)) { 134965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison mvn(rd, shifter_op, cond); 135065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } else { 135165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movw(rd, Low16Bits(value), cond); 135265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison uint16_t value_high = High16Bits(value); 135365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (value_high != 0) { 135465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison movt(rd, value_high, cond); 135565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 135665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 135765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 135865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 135965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 136065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 136165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldLoadOffsetArm. 136265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::LoadFromOffset(LoadOperandType type, 136365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register reg, 136465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 136565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 136665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 136765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldLoadOffsetArm(type, offset)) { 136865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(base != IP); 136965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 137065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 137165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 137265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 137365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 137465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldLoadOffsetArm(type, offset)); 137565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison switch (type) { 137665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadSignedByte: 137765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrsb(reg, Address(base, offset), cond); 137865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 137965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadUnsignedByte: 138065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrb(reg, Address(base, offset), cond); 138165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 138265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadSignedHalfword: 138365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrsh(reg, Address(base, offset), cond); 138465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 138565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadUnsignedHalfword: 138665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrh(reg, Address(base, offset), cond); 138765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 138865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadWord: 138965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldr(reg, Address(base, offset), cond); 139065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 139165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kLoadWordPair: 139265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison ldrd(reg, Address(base, offset), cond); 139365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 139465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison default: 139565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LOG(FATAL) << "UNREACHABLE"; 13962c4257be8191c5eefde744e8965fcefc80a0a97dIan Rogers UNREACHABLE(); 139765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 139865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 139965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 140065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 140165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 140265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldLoadOffsetArm, as expected by JIT::GuardedLoadFromOffset. 140365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::LoadSFromOffset(SRegister reg, 140465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 140565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 140665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 140765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldLoadOffsetArm(kLoadSWord, offset)) { 140865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, IP); 140965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 141065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 141165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 141265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 141365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 141465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldLoadOffsetArm(kLoadSWord, offset)); 141565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison vldrs(reg, Address(base, offset), cond); 141665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 141765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 141865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 141965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 142065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldLoadOffsetArm, as expected by JIT::GuardedLoadFromOffset. 142165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::LoadDFromOffset(DRegister reg, 142265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 142365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 142465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 142565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldLoadOffsetArm(kLoadDWord, offset)) { 142665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, IP); 142765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 142865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 142965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 143065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 143165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 143265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldLoadOffsetArm(kLoadDWord, offset)); 143365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison vldrd(reg, Address(base, offset), cond); 143465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 143565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 143665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 143765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 143865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldStoreOffsetArm. 143965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::StoreToOffset(StoreOperandType type, 144065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register reg, 144165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 144265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 144365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 144465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldStoreOffsetArm(type, offset)) { 144565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(reg != IP); 144665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(base != IP); 144765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 144865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 144965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 145065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 145165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 145265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldStoreOffsetArm(type, offset)); 145365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison switch (type) { 145465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kStoreByte: 145565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison strb(reg, Address(base, offset), cond); 145665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 145765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kStoreHalfword: 145865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison strh(reg, Address(base, offset), cond); 145965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 146065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kStoreWord: 146165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison str(reg, Address(base, offset), cond); 146265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 146365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison case kStoreWordPair: 146465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison strd(reg, Address(base, offset), cond); 146565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison break; 146665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison default: 146765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LOG(FATAL) << "UNREACHABLE"; 14682c4257be8191c5eefde744e8965fcefc80a0a97dIan Rogers UNREACHABLE(); 146965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 147065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 147165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 147265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 147365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 147465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldStoreOffsetArm, as expected by JIT::GuardedStoreToOffset. 147565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::StoreSToOffset(SRegister reg, 147665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 147765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 147865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 147965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldStoreOffsetArm(kStoreSWord, offset)) { 148065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, IP); 148165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 148265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 148365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 148465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 148565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 148665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldStoreOffsetArm(kStoreSWord, offset)); 148765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison vstrs(reg, Address(base, offset), cond); 148865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 148965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 149065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 149165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Implementation note: this method must emit at most one instruction when 149265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison// Address::CanHoldStoreOffsetArm, as expected by JIT::GuardedStoreSToOffset. 149365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::StoreDToOffset(DRegister reg, 149465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Register base, 149565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t offset, 149665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison Condition cond) { 149765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison if (!Address::CanHoldStoreOffsetArm(kStoreDWord, offset)) { 149865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_NE(base, IP); 149965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LoadImmediate(IP, offset, cond); 150065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison add(IP, IP, ShifterOperand(base), cond); 150165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison base = IP; 150265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison offset = 0; 150365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison } 150465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK(Address::CanHoldStoreOffsetArm(kStoreDWord, offset)); 150565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison vstrd(reg, Address(base, offset), cond); 150665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 150765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 150865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 150965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::MemoryBarrier(ManagedRegister mscratch) { 151065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison CHECK_EQ(mscratch.AsArm().AsCoreRegister(), R12); 151119a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray dmb(SY); 151219a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray} 151319a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray 151419a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray 151519a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffrayvoid Arm32Assembler::dmb(DmbOptions flavor) { 151665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#if ANDROID_SMP != 0 151765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison int32_t encoding = 0xf57ff05f; // dmb 151819a19cffd197a28ae4c9c3e59eff6352fd392241Nicolas Geoffray Emit(encoding | flavor); 151965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison#endif 152065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 152165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 152265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15236a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866fIan Rogersvoid Arm32Assembler::cbz(Register rn ATTRIBUTE_UNUSED, Label* target ATTRIBUTE_UNUSED) { 152465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LOG(FATAL) << "cbz is not supported on ARM32"; 152565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 152665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 152765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 15286a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866fIan Rogersvoid Arm32Assembler::cbnz(Register rn ATTRIBUTE_UNUSED, Label* target ATTRIBUTE_UNUSED) { 152965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison LOG(FATAL) << "cbnz is not supported on ARM32"; 153065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 153165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 153265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 153365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::CompareAndBranchIfZero(Register r, Label* label) { 153465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison cmp(r, ShifterOperand(0)); 153565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison b(label, EQ); 153665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 153765fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 153865fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 153965fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allisonvoid Arm32Assembler::CompareAndBranchIfNonZero(Register r, Label* label) { 154065fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison cmp(r, ShifterOperand(0)); 154165fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison b(label, NE); 154265fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} 154365fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 154465fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison 154565fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} // namespace arm 154665fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7Dave Allison} // namespace art 1547