assembler_x86.h revision 154552e666347d41d95d7619c6ee56249ff4feca 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
18#define ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
19
20#include <vector>
21#include "base/macros.h"
22#include "constants_x86.h"
23#include "globals.h"
24#include "managed_register_x86.h"
25#include "offsets.h"
26#include "utils/assembler.h"
27#include "utils.h"
28
29namespace art {
30namespace x86 {
31
32class Immediate : public ValueObject {
33 public:
34  explicit Immediate(int32_t value_in) : value_(value_in) {}
35
36  int32_t value() const { return value_; }
37
38  bool is_int8() const { return IsInt<8>(value_); }
39  bool is_uint8() const { return IsUint<8>(value_); }
40  bool is_int16() const { return IsInt<16>(value_); }
41  bool is_uint16() const { return IsUint<16>(value_); }
42
43 private:
44  const int32_t value_;
45};
46
47
48class Operand : public ValueObject {
49 public:
50  uint8_t mod() const {
51    return (encoding_at(0) >> 6) & 3;
52  }
53
54  Register rm() const {
55    return static_cast<Register>(encoding_at(0) & 7);
56  }
57
58  ScaleFactor scale() const {
59    return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
60  }
61
62  Register index() const {
63    return static_cast<Register>((encoding_at(1) >> 3) & 7);
64  }
65
66  Register base() const {
67    return static_cast<Register>(encoding_at(1) & 7);
68  }
69
70  int8_t disp8() const {
71    CHECK_GE(length_, 2);
72    return static_cast<int8_t>(encoding_[length_ - 1]);
73  }
74
75  int32_t disp32() const {
76    CHECK_GE(length_, 5);
77    int32_t value;
78    memcpy(&value, &encoding_[length_ - 4], sizeof(value));
79    return value;
80  }
81
82  bool IsRegister(Register reg) const {
83    return ((encoding_[0] & 0xF8) == 0xC0)  // Addressing mode is register only.
84        && ((encoding_[0] & 0x07) == reg);  // Register codes match.
85  }
86
87 protected:
88  // Operand can be sub classed (e.g: Address).
89  Operand() : length_(0) { }
90
91  void SetModRM(int mod_in, Register rm_in) {
92    CHECK_EQ(mod_in & ~3, 0);
93    encoding_[0] = (mod_in << 6) | rm_in;
94    length_ = 1;
95  }
96
97  void SetSIB(ScaleFactor scale_in, Register index_in, Register base_in) {
98    CHECK_EQ(length_, 1);
99    CHECK_EQ(scale_in & ~3, 0);
100    encoding_[1] = (scale_in << 6) | (index_in << 3) | base_in;
101    length_ = 2;
102  }
103
104  void SetDisp8(int8_t disp) {
105    CHECK(length_ == 1 || length_ == 2);
106    encoding_[length_++] = static_cast<uint8_t>(disp);
107  }
108
109  void SetDisp32(int32_t disp) {
110    CHECK(length_ == 1 || length_ == 2);
111    int disp_size = sizeof(disp);
112    memmove(&encoding_[length_], &disp, disp_size);
113    length_ += disp_size;
114  }
115
116 private:
117  uint8_t length_;
118  uint8_t encoding_[6];
119
120  explicit Operand(Register reg) { SetModRM(3, reg); }
121
122  // Get the operand encoding byte at the given index.
123  uint8_t encoding_at(int index_in) const {
124    CHECK_GE(index_in, 0);
125    CHECK_LT(index_in, length_);
126    return encoding_[index_in];
127  }
128
129  friend class X86Assembler;
130};
131
132
133class Address : public Operand {
134 public:
135  Address(Register base_in, int32_t disp) {
136    Init(base_in, disp);
137  }
138
139  Address(Register base_in, Offset disp) {
140    Init(base_in, disp.Int32Value());
141  }
142
143  Address(Register base_in, FrameOffset disp) {
144    CHECK_EQ(base_in, ESP);
145    Init(ESP, disp.Int32Value());
146  }
147
148  Address(Register base_in, MemberOffset disp) {
149    Init(base_in, disp.Int32Value());
150  }
151
152  void Init(Register base_in, int32_t disp) {
153    if (disp == 0 && base_in != EBP) {
154      SetModRM(0, base_in);
155      if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
156    } else if (disp >= -128 && disp <= 127) {
157      SetModRM(1, base_in);
158      if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
159      SetDisp8(disp);
160    } else {
161      SetModRM(2, base_in);
162      if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
163      SetDisp32(disp);
164    }
165  }
166
167  Address(Register index_in, ScaleFactor scale_in, int32_t disp) {
168    CHECK_NE(index_in, ESP);  // Illegal addressing mode.
169    SetModRM(0, ESP);
170    SetSIB(scale_in, index_in, EBP);
171    SetDisp32(disp);
172  }
173
174  Address(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) {
175    CHECK_NE(index_in, ESP);  // Illegal addressing mode.
176    if (disp == 0 && base_in != EBP) {
177      SetModRM(0, ESP);
178      SetSIB(scale_in, index_in, base_in);
179    } else if (disp >= -128 && disp <= 127) {
180      SetModRM(1, ESP);
181      SetSIB(scale_in, index_in, base_in);
182      SetDisp8(disp);
183    } else {
184      SetModRM(2, ESP);
185      SetSIB(scale_in, index_in, base_in);
186      SetDisp32(disp);
187    }
188  }
189
190  static Address Absolute(uintptr_t addr) {
191    Address result;
192    result.SetModRM(0, EBP);
193    result.SetDisp32(addr);
194    return result;
195  }
196
197  static Address Absolute(ThreadOffset<4> addr) {
198    return Absolute(addr.Int32Value());
199  }
200
201 private:
202  Address() {}
203};
204
205
206class X86Assembler FINAL : public Assembler {
207 public:
208  explicit X86Assembler() : cfi_cfa_offset_(0), cfi_pc_(0) {}
209  virtual ~X86Assembler() {}
210
211  /*
212   * Emit Machine Instructions.
213   */
214  void call(Register reg);
215  void call(const Address& address);
216  void call(Label* label);
217  void call(const ExternalLabel& label);
218
219  void pushl(Register reg);
220  void pushl(const Address& address);
221  void pushl(const Immediate& imm);
222
223  void popl(Register reg);
224  void popl(const Address& address);
225
226  void movl(Register dst, const Immediate& src);
227  void movl(Register dst, Register src);
228
229  void movl(Register dst, const Address& src);
230  void movl(const Address& dst, Register src);
231  void movl(const Address& dst, const Immediate& imm);
232  void movl(const Address& dst, Label* lbl);
233
234  void movzxb(Register dst, ByteRegister src);
235  void movzxb(Register dst, const Address& src);
236  void movsxb(Register dst, ByteRegister src);
237  void movsxb(Register dst, const Address& src);
238  void movb(Register dst, const Address& src);
239  void movb(const Address& dst, ByteRegister src);
240  void movb(const Address& dst, const Immediate& imm);
241
242  void movzxw(Register dst, Register src);
243  void movzxw(Register dst, const Address& src);
244  void movsxw(Register dst, Register src);
245  void movsxw(Register dst, const Address& src);
246  void movw(Register dst, const Address& src);
247  void movw(const Address& dst, Register src);
248  void movw(const Address& dst, const Immediate& imm);
249
250  void leal(Register dst, const Address& src);
251
252  void cmovl(Condition condition, Register dst, Register src);
253
254  void setb(Condition condition, Register dst);
255
256  void movaps(XmmRegister dst, XmmRegister src);
257  void movss(XmmRegister dst, const Address& src);
258  void movss(const Address& dst, XmmRegister src);
259  void movss(XmmRegister dst, XmmRegister src);
260
261  void movd(XmmRegister dst, Register src);
262  void movd(Register dst, XmmRegister src);
263
264  void addss(XmmRegister dst, XmmRegister src);
265  void addss(XmmRegister dst, const Address& src);
266  void subss(XmmRegister dst, XmmRegister src);
267  void subss(XmmRegister dst, const Address& src);
268  void mulss(XmmRegister dst, XmmRegister src);
269  void mulss(XmmRegister dst, const Address& src);
270  void divss(XmmRegister dst, XmmRegister src);
271  void divss(XmmRegister dst, const Address& src);
272
273  void movsd(XmmRegister dst, const Address& src);
274  void movsd(const Address& dst, XmmRegister src);
275  void movsd(XmmRegister dst, XmmRegister src);
276
277  void psrlq(XmmRegister reg, const Immediate& shift_count);
278  void punpckldq(XmmRegister dst, XmmRegister src);
279
280  void addsd(XmmRegister dst, XmmRegister src);
281  void addsd(XmmRegister dst, const Address& src);
282  void subsd(XmmRegister dst, XmmRegister src);
283  void subsd(XmmRegister dst, const Address& src);
284  void mulsd(XmmRegister dst, XmmRegister src);
285  void mulsd(XmmRegister dst, const Address& src);
286  void divsd(XmmRegister dst, XmmRegister src);
287  void divsd(XmmRegister dst, const Address& src);
288
289  void cvtsi2ss(XmmRegister dst, Register src);
290  void cvtsi2sd(XmmRegister dst, Register src);
291
292  void cvtss2si(Register dst, XmmRegister src);
293  void cvtss2sd(XmmRegister dst, XmmRegister src);
294
295  void cvtsd2si(Register dst, XmmRegister src);
296  void cvtsd2ss(XmmRegister dst, XmmRegister src);
297
298  void cvttss2si(Register dst, XmmRegister src);
299  void cvttsd2si(Register dst, XmmRegister src);
300
301  void cvtdq2pd(XmmRegister dst, XmmRegister src);
302
303  void comiss(XmmRegister a, XmmRegister b);
304  void comisd(XmmRegister a, XmmRegister b);
305  void ucomiss(XmmRegister a, XmmRegister b);
306  void ucomisd(XmmRegister a, XmmRegister b);
307
308  void sqrtsd(XmmRegister dst, XmmRegister src);
309  void sqrtss(XmmRegister dst, XmmRegister src);
310
311  void xorpd(XmmRegister dst, const Address& src);
312  void xorpd(XmmRegister dst, XmmRegister src);
313  void xorps(XmmRegister dst, const Address& src);
314  void xorps(XmmRegister dst, XmmRegister src);
315
316  void andpd(XmmRegister dst, const Address& src);
317
318  void flds(const Address& src);
319  void fstps(const Address& dst);
320  void fsts(const Address& dst);
321
322  void fldl(const Address& src);
323  void fstpl(const Address& dst);
324  void fstl(const Address& dst);
325
326  void fstsw();
327
328  void fucompp();
329
330  void fnstcw(const Address& dst);
331  void fldcw(const Address& src);
332
333  void fistpl(const Address& dst);
334  void fistps(const Address& dst);
335  void fildl(const Address& src);
336
337  void fincstp();
338  void ffree(const Immediate& index);
339
340  void fsin();
341  void fcos();
342  void fptan();
343  void fprem();
344
345  void xchgl(Register dst, Register src);
346  void xchgl(Register reg, const Address& address);
347
348  void cmpw(const Address& address, const Immediate& imm);
349
350  void cmpl(Register reg, const Immediate& imm);
351  void cmpl(Register reg0, Register reg1);
352  void cmpl(Register reg, const Address& address);
353
354  void cmpl(const Address& address, Register reg);
355  void cmpl(const Address& address, const Immediate& imm);
356
357  void testl(Register reg1, Register reg2);
358  void testl(Register reg, const Immediate& imm);
359  void testl(Register reg1, const Address& address);
360
361  void andl(Register dst, const Immediate& imm);
362  void andl(Register dst, Register src);
363  void andl(Register dst, const Address& address);
364
365  void orl(Register dst, const Immediate& imm);
366  void orl(Register dst, Register src);
367  void orl(Register dst, const Address& address);
368
369  void xorl(Register dst, Register src);
370  void xorl(Register dst, const Immediate& imm);
371  void xorl(Register dst, const Address& address);
372
373  void addl(Register dst, Register src);
374  void addl(Register reg, const Immediate& imm);
375  void addl(Register reg, const Address& address);
376
377  void addl(const Address& address, Register reg);
378  void addl(const Address& address, const Immediate& imm);
379
380  void adcl(Register dst, Register src);
381  void adcl(Register reg, const Immediate& imm);
382  void adcl(Register dst, const Address& address);
383
384  void subl(Register dst, Register src);
385  void subl(Register reg, const Immediate& imm);
386  void subl(Register reg, const Address& address);
387
388  void cdq();
389
390  void idivl(Register reg);
391
392  void imull(Register dst, Register src);
393  void imull(Register reg, const Immediate& imm);
394  void imull(Register reg, const Address& address);
395
396  void imull(Register reg);
397  void imull(const Address& address);
398
399  void mull(Register reg);
400  void mull(const Address& address);
401
402  void sbbl(Register dst, Register src);
403  void sbbl(Register reg, const Immediate& imm);
404  void sbbl(Register reg, const Address& address);
405
406  void incl(Register reg);
407  void incl(const Address& address);
408
409  void decl(Register reg);
410  void decl(const Address& address);
411
412  void shll(Register reg, const Immediate& imm);
413  void shll(Register operand, Register shifter);
414  void shrl(Register reg, const Immediate& imm);
415  void shrl(Register operand, Register shifter);
416  void sarl(Register reg, const Immediate& imm);
417  void sarl(Register operand, Register shifter);
418  void shld(Register dst, Register src, Register shifter);
419  void shrd(Register dst, Register src, Register shifter);
420
421  void negl(Register reg);
422  void notl(Register reg);
423
424  void enter(const Immediate& imm);
425  void leave();
426
427  void ret();
428  void ret(const Immediate& imm);
429
430  void nop();
431  void int3();
432  void hlt();
433
434  void j(Condition condition, Label* label);
435
436  void jmp(Register reg);
437  void jmp(const Address& address);
438  void jmp(Label* label);
439
440  X86Assembler* lock();
441  void cmpxchgl(const Address& address, Register reg);
442
443  void mfence();
444
445  X86Assembler* fs();
446  X86Assembler* gs();
447
448  //
449  // Macros for High-level operations.
450  //
451
452  void AddImmediate(Register reg, const Immediate& imm);
453
454  void LoadLongConstant(XmmRegister dst, int64_t value);
455  void LoadDoubleConstant(XmmRegister dst, double value);
456
457  void LockCmpxchgl(const Address& address, Register reg) {
458    lock()->cmpxchgl(address, reg);
459  }
460
461  //
462  // Misc. functionality
463  //
464  int PreferredLoopAlignment() { return 16; }
465  void Align(int alignment, int offset);
466  void Bind(Label* label);
467
468  //
469  // Overridden common assembler high-level functionality
470  //
471
472  // Emit code that will create an activation on the stack
473  void BuildFrame(size_t frame_size, ManagedRegister method_reg,
474                  const std::vector<ManagedRegister>& callee_save_regs,
475                  const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
476
477  // Emit code that will remove an activation from the stack
478  void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
479      OVERRIDE;
480
481  void IncreaseFrameSize(size_t adjust) OVERRIDE;
482  void DecreaseFrameSize(size_t adjust) OVERRIDE;
483
484  // Store routines
485  void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
486  void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
487  void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
488
489  void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
490
491  void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister scratch)
492      OVERRIDE;
493
494  void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
495                                  ManagedRegister scratch) OVERRIDE;
496
497  void StoreStackPointerToThread32(ThreadOffset<4> thr_offs) OVERRIDE;
498
499  void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
500                     ManagedRegister scratch) OVERRIDE;
501
502  // Load routines
503  void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
504
505  void LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size) OVERRIDE;
506
507  void LoadRef(ManagedRegister dest, FrameOffset  src) OVERRIDE;
508
509  void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE;
510
511  void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
512
513  void LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs) OVERRIDE;
514
515  // Copying routines
516  void Move(ManagedRegister dest, ManagedRegister src, size_t size) OVERRIDE;
517
518  void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
519                              ManagedRegister scratch) OVERRIDE;
520
521  void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
522      OVERRIDE;
523
524  void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
525
526  void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
527
528  void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
529            size_t size) OVERRIDE;
530
531  void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
532            size_t size) OVERRIDE;
533
534  void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
535            size_t size) OVERRIDE;
536
537  void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
538            ManagedRegister scratch, size_t size) OVERRIDE;
539
540  void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
541            ManagedRegister scratch, size_t size) OVERRIDE;
542
543  void MemoryBarrier(ManagedRegister) OVERRIDE;
544
545  // Sign extension
546  void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
547
548  // Zero extension
549  void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
550
551  // Exploit fast access in managed code to Thread::Current()
552  void GetCurrentThread(ManagedRegister tr) OVERRIDE;
553  void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
554
555  // Set up out_reg to hold a Object** into the handle scope, or to be NULL if the
556  // value is null and null_allowed. in_reg holds a possibly stale reference
557  // that can be used to avoid loading the handle scope entry to see if the value is
558  // NULL.
559  void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset, ManagedRegister in_reg,
560                       bool null_allowed) OVERRIDE;
561
562  // Set up out_off to hold a Object** into the handle scope, or to be NULL if the
563  // value is null and null_allowed.
564  void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset, ManagedRegister scratch,
565                       bool null_allowed) OVERRIDE;
566
567  // src holds a handle scope entry (Object**) load this into dst
568  void LoadReferenceFromHandleScope(ManagedRegister dst, ManagedRegister src) OVERRIDE;
569
570  // Heap::VerifyObject on src. In some cases (such as a reference to this) we
571  // know that src may not be null.
572  void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
573  void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
574
575  // Call to address held at [base+offset]
576  void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
577  void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
578  void CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch) OVERRIDE;
579
580  // Generate code to check if Thread::Current()->exception_ is non-null
581  // and branch to a ExceptionSlowPath if it is.
582  void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
583
584  void InitializeFrameDescriptionEntry() OVERRIDE;
585  void FinalizeFrameDescriptionEntry() OVERRIDE;
586  std::vector<uint8_t>* GetFrameDescriptionEntry() OVERRIDE {
587    return &cfi_info_;
588  }
589
590 private:
591  inline void EmitUint8(uint8_t value);
592  inline void EmitInt32(int32_t value);
593  inline void EmitRegisterOperand(int rm, int reg);
594  inline void EmitXmmRegisterOperand(int rm, XmmRegister reg);
595  inline void EmitFixup(AssemblerFixup* fixup);
596  inline void EmitOperandSizeOverride();
597
598  void EmitOperand(int rm, const Operand& operand);
599  void EmitImmediate(const Immediate& imm);
600  void EmitComplex(int rm, const Operand& operand, const Immediate& immediate);
601  void EmitLabel(Label* label, int instruction_size);
602  void EmitLabelLink(Label* label);
603  void EmitNearLabelLink(Label* label);
604
605  void EmitGenericShift(int rm, Register reg, const Immediate& imm);
606  void EmitGenericShift(int rm, Register operand, Register shifter);
607
608  std::vector<uint8_t> cfi_info_;
609  uint32_t cfi_cfa_offset_, cfi_pc_;
610
611  DISALLOW_COPY_AND_ASSIGN(X86Assembler);
612};
613
614inline void X86Assembler::EmitUint8(uint8_t value) {
615  buffer_.Emit<uint8_t>(value);
616}
617
618inline void X86Assembler::EmitInt32(int32_t value) {
619  buffer_.Emit<int32_t>(value);
620}
621
622inline void X86Assembler::EmitRegisterOperand(int rm, int reg) {
623  CHECK_GE(rm, 0);
624  CHECK_LT(rm, 8);
625  buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg);
626}
627
628inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) {
629  EmitRegisterOperand(rm, static_cast<Register>(reg));
630}
631
632inline void X86Assembler::EmitFixup(AssemblerFixup* fixup) {
633  buffer_.EmitFixup(fixup);
634}
635
636inline void X86Assembler::EmitOperandSizeOverride() {
637  EmitUint8(0x66);
638}
639
640// Slowpath entered when Thread::Current()->_exception is non-null
641class X86ExceptionSlowPath FINAL : public SlowPath {
642 public:
643  explicit X86ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
644  virtual void Emit(Assembler *sp_asm) OVERRIDE;
645 private:
646  const size_t stack_adjust_;
647};
648
649}  // namespace x86
650}  // namespace art
651
652#endif  // ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
653