assembler_x86_64.cc revision eb8167a4f4d27fce0530f6724ab8032610cd146b 
1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "assembler_x86_64.h"
18
19#include "base/casts.h"
20#include "entrypoints/quick/quick_entrypoints.h"
21#include "memory_region.h"
22#include "thread.h"
23
24namespace art {
25namespace x86_64 {
26
27std::ostream& operator<<(std::ostream& os, const CpuRegister& reg) {
28  return os << reg.AsRegister();
29}
30
31std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
32  return os << reg.AsFloatRegister();
33}
34
35std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
36  return os << "ST" << static_cast<int>(reg);
37}
38
39void X86_64Assembler::call(CpuRegister reg) {
40  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
41  EmitOptionalRex32(reg);
42  EmitUint8(0xFF);
43  EmitRegisterOperand(2, reg.LowBits());
44}
45
46
47void X86_64Assembler::call(const Address& address) {
48  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
49  EmitOptionalRex32(address);
50  EmitUint8(0xFF);
51  EmitOperand(2, address);
52}
53
54
55void X86_64Assembler::call(Label* label) {
56  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
57  EmitUint8(0xE8);
58  static const int kSize = 5;
59  EmitLabel(label, kSize);
60}
61
62
63void X86_64Assembler::pushq(CpuRegister reg) {
64  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
65  EmitOptionalRex32(reg);
66  EmitUint8(0x50 + reg.LowBits());
67}
68
69
70void X86_64Assembler::pushq(const Address& address) {
71  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
72  EmitOptionalRex32(address);
73  EmitUint8(0xFF);
74  EmitOperand(6, address);
75}
76
77
78void X86_64Assembler::pushq(const Immediate& imm) {
79  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
80  CHECK(imm.is_int32());  // pushq only supports 32b immediate.
81  if (imm.is_int8()) {
82    EmitUint8(0x6A);
83    EmitUint8(imm.value() & 0xFF);
84  } else {
85    EmitUint8(0x68);
86    EmitImmediate(imm);
87  }
88}
89
90
91void X86_64Assembler::popq(CpuRegister reg) {
92  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
93  EmitOptionalRex32(reg);
94  EmitUint8(0x58 + reg.LowBits());
95}
96
97
98void X86_64Assembler::popq(const Address& address) {
99  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
100  EmitOptionalRex32(address);
101  EmitUint8(0x8F);
102  EmitOperand(0, address);
103}
104
105
106void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) {
107  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
108  if (imm.is_int32()) {
109    // 32 bit. Note: sign-extends.
110    EmitRex64(dst);
111    EmitUint8(0xC7);
112    EmitRegisterOperand(0, dst.LowBits());
113    EmitInt32(static_cast<int32_t>(imm.value()));
114  } else {
115    EmitRex64(dst);
116    EmitUint8(0xB8 + dst.LowBits());
117    EmitInt64(imm.value());
118  }
119}
120
121
122void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) {
123  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
124  EmitOptionalRex32(dst);
125  EmitUint8(0xB8 + dst.LowBits());
126  EmitImmediate(imm);
127}
128
129
130void X86_64Assembler::movq(CpuRegister dst, CpuRegister src) {
131  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
132  // 0x89 is movq r/m64 <- r64, with op1 in r/m and op2 in reg: so reverse EmitRex64
133  EmitRex64(src, dst);
134  EmitUint8(0x89);
135  EmitRegisterOperand(src.LowBits(), dst.LowBits());
136}
137
138
139void X86_64Assembler::movl(CpuRegister dst, CpuRegister src) {
140  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
141  EmitOptionalRex32(dst, src);
142  EmitUint8(0x89);
143  EmitRegisterOperand(src.LowBits(), dst.LowBits());
144}
145
146
147void X86_64Assembler::movq(CpuRegister dst, const Address& src) {
148  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
149  EmitRex64(dst, src);
150  EmitUint8(0x8B);
151  EmitOperand(dst.LowBits(), src);
152}
153
154
155void X86_64Assembler::movl(CpuRegister dst, const Address& src) {
156  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
157  EmitOptionalRex32(dst, src);
158  EmitUint8(0x8B);
159  EmitOperand(dst.LowBits(), src);
160}
161
162
163void X86_64Assembler::movq(const Address& dst, CpuRegister src) {
164  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
165  EmitRex64(src, dst);
166  EmitUint8(0x89);
167  EmitOperand(src.LowBits(), dst);
168}
169
170
171void X86_64Assembler::movl(const Address& dst, CpuRegister src) {
172  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
173  EmitOptionalRex32(src, dst);
174  EmitUint8(0x89);
175  EmitOperand(src.LowBits(), dst);
176}
177
178void X86_64Assembler::movl(const Address& dst, const Immediate& imm) {
179  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
180  EmitOptionalRex32(dst);
181  EmitUint8(0xC7);
182  EmitOperand(0, dst);
183  EmitImmediate(imm);
184}
185
186void X86_64Assembler::movzxb(CpuRegister dst, CpuRegister src) {
187  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
188  EmitOptionalByteRegNormalizingRex32(dst, src);
189  EmitUint8(0x0F);
190  EmitUint8(0xB6);
191  EmitRegisterOperand(dst.LowBits(), src.LowBits());
192}
193
194
195void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) {
196  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
197  EmitOptionalByteRegNormalizingRex32(dst, src);
198  EmitUint8(0x0F);
199  EmitUint8(0xB6);
200  EmitOperand(dst.LowBits(), src);
201}
202
203
204void X86_64Assembler::movsxb(CpuRegister dst, CpuRegister src) {
205  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
206  EmitOptionalByteRegNormalizingRex32(dst, src);
207  EmitUint8(0x0F);
208  EmitUint8(0xBE);
209  EmitRegisterOperand(dst.LowBits(), src.LowBits());
210}
211
212
213void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) {
214  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
215  EmitOptionalByteRegNormalizingRex32(dst, src);
216  EmitUint8(0x0F);
217  EmitUint8(0xBE);
218  EmitOperand(dst.LowBits(), src);
219}
220
221
222void X86_64Assembler::movb(CpuRegister /*dst*/, const Address& /*src*/) {
223  LOG(FATAL) << "Use movzxb or movsxb instead.";
224}
225
226
227void X86_64Assembler::movb(const Address& dst, CpuRegister src) {
228  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
229  EmitOptionalByteRegNormalizingRex32(src, dst);
230  EmitUint8(0x88);
231  EmitOperand(src.LowBits(), dst);
232}
233
234
235void X86_64Assembler::movb(const Address& dst, const Immediate& imm) {
236  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
237  EmitUint8(0xC6);
238  EmitOperand(Register::RAX, dst);
239  CHECK(imm.is_int8());
240  EmitUint8(imm.value() & 0xFF);
241}
242
243
244void X86_64Assembler::movzxw(CpuRegister dst, CpuRegister src) {
245  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
246  EmitOptionalRex32(dst, src);
247  EmitUint8(0x0F);
248  EmitUint8(0xB7);
249  EmitRegisterOperand(dst.LowBits(), src.LowBits());
250}
251
252
253void X86_64Assembler::movzxw(CpuRegister dst, const Address& src) {
254  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
255  EmitOptionalRex32(dst, src);
256  EmitUint8(0x0F);
257  EmitUint8(0xB7);
258  EmitOperand(dst.LowBits(), src);
259}
260
261
262void X86_64Assembler::movsxw(CpuRegister dst, CpuRegister src) {
263  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
264  EmitOptionalRex32(dst, src);
265  EmitUint8(0x0F);
266  EmitUint8(0xBF);
267  EmitRegisterOperand(dst.LowBits(), src.LowBits());
268}
269
270
271void X86_64Assembler::movsxw(CpuRegister dst, const Address& src) {
272  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
273  EmitOptionalRex32(dst, src);
274  EmitUint8(0x0F);
275  EmitUint8(0xBF);
276  EmitOperand(dst.LowBits(), src);
277}
278
279
280void X86_64Assembler::movw(CpuRegister /*dst*/, const Address& /*src*/) {
281  LOG(FATAL) << "Use movzxw or movsxw instead.";
282}
283
284
285void X86_64Assembler::movw(const Address& dst, CpuRegister src) {
286  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
287  EmitOptionalRex32(src, dst);
288  EmitOperandSizeOverride();
289  EmitUint8(0x89);
290  EmitOperand(src.LowBits(), dst);
291}
292
293
294void X86_64Assembler::leaq(CpuRegister dst, const Address& src) {
295  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
296  EmitRex64(dst, src);
297  EmitUint8(0x8D);
298  EmitOperand(dst.LowBits(), src);
299}
300
301
302void X86_64Assembler::movss(XmmRegister dst, const Address& src) {
303  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
304  EmitUint8(0xF3);
305  EmitOptionalRex32(dst, src);
306  EmitUint8(0x0F);
307  EmitUint8(0x10);
308  EmitOperand(dst.LowBits(), src);
309}
310
311
312void X86_64Assembler::movss(const Address& dst, XmmRegister src) {
313  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
314  EmitUint8(0xF3);
315  EmitOptionalRex32(src, dst);
316  EmitUint8(0x0F);
317  EmitUint8(0x11);
318  EmitOperand(src.LowBits(), dst);
319}
320
321
322void X86_64Assembler::movss(XmmRegister dst, XmmRegister src) {
323  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
324  EmitUint8(0xF3);
325  EmitOptionalRex32(dst, src);
326  EmitUint8(0x0F);
327  EmitUint8(0x11);
328  EmitXmmRegisterOperand(src.LowBits(), dst);
329}
330
331
332void X86_64Assembler::movd(XmmRegister dst, CpuRegister src) {
333  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
334  EmitUint8(0x66);
335  EmitOptionalRex32(dst, src);
336  EmitUint8(0x0F);
337  EmitUint8(0x6E);
338  EmitOperand(dst.LowBits(), Operand(src));
339}
340
341
342void X86_64Assembler::movd(CpuRegister dst, XmmRegister src) {
343  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
344  EmitUint8(0x66);
345  EmitOptionalRex32(src, dst);
346  EmitUint8(0x0F);
347  EmitUint8(0x7E);
348  EmitOperand(src.LowBits(), Operand(dst));
349}
350
351
352void X86_64Assembler::addss(XmmRegister dst, XmmRegister src) {
353  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
354  EmitUint8(0xF3);
355  EmitOptionalRex32(dst, src);
356  EmitUint8(0x0F);
357  EmitUint8(0x58);
358  EmitXmmRegisterOperand(dst.LowBits(), src);
359}
360
361
362void X86_64Assembler::addss(XmmRegister dst, const Address& src) {
363  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
364  EmitUint8(0xF3);
365  EmitOptionalRex32(dst, src);
366  EmitUint8(0x0F);
367  EmitUint8(0x58);
368  EmitOperand(dst.LowBits(), src);
369}
370
371
372void X86_64Assembler::subss(XmmRegister dst, XmmRegister src) {
373  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
374  EmitUint8(0xF3);
375  EmitOptionalRex32(dst, src);
376  EmitUint8(0x0F);
377  EmitUint8(0x5C);
378  EmitXmmRegisterOperand(dst.LowBits(), src);
379}
380
381
382void X86_64Assembler::subss(XmmRegister dst, const Address& src) {
383  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
384  EmitUint8(0xF3);
385  EmitOptionalRex32(dst, src);
386  EmitUint8(0x0F);
387  EmitUint8(0x5C);
388  EmitOperand(dst.LowBits(), src);
389}
390
391
392void X86_64Assembler::mulss(XmmRegister dst, XmmRegister src) {
393  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
394  EmitUint8(0xF3);
395  EmitOptionalRex32(dst, src);
396  EmitUint8(0x0F);
397  EmitUint8(0x59);
398  EmitXmmRegisterOperand(dst.LowBits(), src);
399}
400
401
402void X86_64Assembler::mulss(XmmRegister dst, const Address& src) {
403  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
404  EmitUint8(0xF3);
405  EmitOptionalRex32(dst, src);
406  EmitUint8(0x0F);
407  EmitUint8(0x59);
408  EmitOperand(dst.LowBits(), src);
409}
410
411
412void X86_64Assembler::divss(XmmRegister dst, XmmRegister src) {
413  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414  EmitUint8(0xF3);
415  EmitOptionalRex32(dst, src);
416  EmitUint8(0x0F);
417  EmitUint8(0x5E);
418  EmitXmmRegisterOperand(dst.LowBits(), src);
419}
420
421
422void X86_64Assembler::divss(XmmRegister dst, const Address& src) {
423  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
424  EmitUint8(0xF3);
425  EmitOptionalRex32(dst, src);
426  EmitUint8(0x0F);
427  EmitUint8(0x5E);
428  EmitOperand(dst.LowBits(), src);
429}
430
431
432void X86_64Assembler::flds(const Address& src) {
433  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
434  EmitUint8(0xD9);
435  EmitOperand(0, src);
436}
437
438
439void X86_64Assembler::fstps(const Address& dst) {
440  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441  EmitUint8(0xD9);
442  EmitOperand(3, dst);
443}
444
445
446void X86_64Assembler::movsd(XmmRegister dst, const Address& src) {
447  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
448  EmitUint8(0xF2);
449  EmitOptionalRex32(dst, src);
450  EmitUint8(0x0F);
451  EmitUint8(0x10);
452  EmitOperand(dst.LowBits(), src);
453}
454
455
456void X86_64Assembler::movsd(const Address& dst, XmmRegister src) {
457  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
458  EmitUint8(0xF2);
459  EmitOptionalRex32(src, dst);
460  EmitUint8(0x0F);
461  EmitUint8(0x11);
462  EmitOperand(src.LowBits(), dst);
463}
464
465
466void X86_64Assembler::movsd(XmmRegister dst, XmmRegister src) {
467  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468  EmitUint8(0xF2);
469  EmitOptionalRex32(dst, src);
470  EmitUint8(0x0F);
471  EmitUint8(0x11);
472  EmitXmmRegisterOperand(src.LowBits(), dst);
473}
474
475
476void X86_64Assembler::addsd(XmmRegister dst, XmmRegister src) {
477  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
478  EmitUint8(0xF2);
479  EmitOptionalRex32(dst, src);
480  EmitUint8(0x0F);
481  EmitUint8(0x58);
482  EmitXmmRegisterOperand(dst.LowBits(), src);
483}
484
485
486void X86_64Assembler::addsd(XmmRegister dst, const Address& src) {
487  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
488  EmitUint8(0xF2);
489  EmitOptionalRex32(dst, src);
490  EmitUint8(0x0F);
491  EmitUint8(0x58);
492  EmitOperand(dst.LowBits(), src);
493}
494
495
496void X86_64Assembler::subsd(XmmRegister dst, XmmRegister src) {
497  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
498  EmitUint8(0xF2);
499  EmitOptionalRex32(dst, src);
500  EmitUint8(0x0F);
501  EmitUint8(0x5C);
502  EmitXmmRegisterOperand(dst.LowBits(), src);
503}
504
505
506void X86_64Assembler::subsd(XmmRegister dst, const Address& src) {
507  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
508  EmitUint8(0xF2);
509  EmitOptionalRex32(dst, src);
510  EmitUint8(0x0F);
511  EmitUint8(0x5C);
512  EmitOperand(dst.LowBits(), src);
513}
514
515
516void X86_64Assembler::mulsd(XmmRegister dst, XmmRegister src) {
517  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
518  EmitUint8(0xF2);
519  EmitOptionalRex32(dst, src);
520  EmitUint8(0x0F);
521  EmitUint8(0x59);
522  EmitXmmRegisterOperand(dst.LowBits(), src);
523}
524
525
526void X86_64Assembler::mulsd(XmmRegister dst, const Address& src) {
527  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
528  EmitUint8(0xF2);
529  EmitOptionalRex32(dst, src);
530  EmitUint8(0x0F);
531  EmitUint8(0x59);
532  EmitOperand(dst.LowBits(), src);
533}
534
535
536void X86_64Assembler::divsd(XmmRegister dst, XmmRegister src) {
537  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
538  EmitUint8(0xF2);
539  EmitOptionalRex32(dst, src);
540  EmitUint8(0x0F);
541  EmitUint8(0x5E);
542  EmitXmmRegisterOperand(dst.LowBits(), src);
543}
544
545
546void X86_64Assembler::divsd(XmmRegister dst, const Address& src) {
547  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
548  EmitUint8(0xF2);
549  EmitOptionalRex32(dst, src);
550  EmitUint8(0x0F);
551  EmitUint8(0x5E);
552  EmitOperand(dst.LowBits(), src);
553}
554
555
556void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src) {
557  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
558  EmitUint8(0xF3);
559  EmitOptionalRex32(dst, src);
560  EmitUint8(0x0F);
561  EmitUint8(0x2A);
562  EmitOperand(dst.LowBits(), Operand(src));
563}
564
565
566void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src) {
567  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
568  EmitUint8(0xF2);
569  EmitOptionalRex32(dst, src);
570  EmitUint8(0x0F);
571  EmitUint8(0x2A);
572  EmitOperand(dst.LowBits(), Operand(src));
573}
574
575
576void X86_64Assembler::cvtss2si(CpuRegister dst, XmmRegister src) {
577  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
578  EmitUint8(0xF3);
579  EmitOptionalRex32(dst, src);
580  EmitUint8(0x0F);
581  EmitUint8(0x2D);
582  EmitXmmRegisterOperand(dst.LowBits(), src);
583}
584
585
586void X86_64Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
587  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
588  EmitUint8(0xF3);
589  EmitOptionalRex32(dst, src);
590  EmitUint8(0x0F);
591  EmitUint8(0x5A);
592  EmitXmmRegisterOperand(dst.LowBits(), src);
593}
594
595
596void X86_64Assembler::cvtsd2si(CpuRegister dst, XmmRegister src) {
597  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
598  EmitUint8(0xF2);
599  EmitOptionalRex32(dst, src);
600  EmitUint8(0x0F);
601  EmitUint8(0x2D);
602  EmitXmmRegisterOperand(dst.LowBits(), src);
603}
604
605
606void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src) {
607  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
608  EmitUint8(0xF3);
609  EmitOptionalRex32(dst, src);
610  EmitUint8(0x0F);
611  EmitUint8(0x2C);
612  EmitXmmRegisterOperand(dst.LowBits(), src);
613}
614
615
616void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src) {
617  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
618  EmitUint8(0xF2);
619  EmitOptionalRex32(dst, src);
620  EmitUint8(0x0F);
621  EmitUint8(0x2C);
622  EmitXmmRegisterOperand(dst.LowBits(), src);
623}
624
625
626void X86_64Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
627  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
628  EmitUint8(0xF2);
629  EmitOptionalRex32(dst, src);
630  EmitUint8(0x0F);
631  EmitUint8(0x5A);
632  EmitXmmRegisterOperand(dst.LowBits(), src);
633}
634
635
636void X86_64Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
637  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638  EmitUint8(0xF3);
639  EmitOptionalRex32(dst, src);
640  EmitUint8(0x0F);
641  EmitUint8(0xE6);
642  EmitXmmRegisterOperand(dst.LowBits(), src);
643}
644
645
646void X86_64Assembler::comiss(XmmRegister a, XmmRegister b) {
647  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
648  EmitOptionalRex32(a, b);
649  EmitUint8(0x0F);
650  EmitUint8(0x2F);
651  EmitXmmRegisterOperand(a.LowBits(), b);
652}
653
654
655void X86_64Assembler::comisd(XmmRegister a, XmmRegister b) {
656  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
657  EmitUint8(0x66);
658  EmitOptionalRex32(a, b);
659  EmitUint8(0x0F);
660  EmitUint8(0x2F);
661  EmitXmmRegisterOperand(a.LowBits(), b);
662}
663
664
665void X86_64Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
666  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
667  EmitUint8(0xF2);
668  EmitOptionalRex32(dst, src);
669  EmitUint8(0x0F);
670  EmitUint8(0x51);
671  EmitXmmRegisterOperand(dst.LowBits(), src);
672}
673
674
675void X86_64Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
676  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
677  EmitUint8(0xF3);
678  EmitOptionalRex32(dst, src);
679  EmitUint8(0x0F);
680  EmitUint8(0x51);
681  EmitXmmRegisterOperand(dst.LowBits(), src);
682}
683
684
685void X86_64Assembler::xorpd(XmmRegister dst, const Address& src) {
686  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
687  EmitUint8(0x66);
688  EmitOptionalRex32(dst, src);
689  EmitUint8(0x0F);
690  EmitUint8(0x57);
691  EmitOperand(dst.LowBits(), src);
692}
693
694
695void X86_64Assembler::xorpd(XmmRegister dst, XmmRegister src) {
696  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
697  EmitUint8(0x66);
698  EmitOptionalRex32(dst, src);
699  EmitUint8(0x0F);
700  EmitUint8(0x57);
701  EmitXmmRegisterOperand(dst.LowBits(), src);
702}
703
704
705void X86_64Assembler::xorps(XmmRegister dst, const Address& src) {
706  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
707  EmitOptionalRex32(dst, src);
708  EmitUint8(0x0F);
709  EmitUint8(0x57);
710  EmitOperand(dst.LowBits(), src);
711}
712
713
714void X86_64Assembler::xorps(XmmRegister dst, XmmRegister src) {
715  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
716  EmitOptionalRex32(dst, src);
717  EmitUint8(0x0F);
718  EmitUint8(0x57);
719  EmitXmmRegisterOperand(dst.LowBits(), src);
720}
721
722
723void X86_64Assembler::andpd(XmmRegister dst, const Address& src) {
724  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
725  EmitUint8(0x66);
726  EmitOptionalRex32(dst, src);
727  EmitUint8(0x0F);
728  EmitUint8(0x54);
729  EmitOperand(dst.LowBits(), src);
730}
731
732
733void X86_64Assembler::fldl(const Address& src) {
734  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
735  EmitUint8(0xDD);
736  EmitOperand(0, src);
737}
738
739
740void X86_64Assembler::fstpl(const Address& dst) {
741  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
742  EmitUint8(0xDD);
743  EmitOperand(3, dst);
744}
745
746
747void X86_64Assembler::fnstcw(const Address& dst) {
748  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
749  EmitUint8(0xD9);
750  EmitOperand(7, dst);
751}
752
753
754void X86_64Assembler::fldcw(const Address& src) {
755  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
756  EmitUint8(0xD9);
757  EmitOperand(5, src);
758}
759
760
761void X86_64Assembler::fistpl(const Address& dst) {
762  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
763  EmitUint8(0xDF);
764  EmitOperand(7, dst);
765}
766
767
768void X86_64Assembler::fistps(const Address& dst) {
769  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
770  EmitUint8(0xDB);
771  EmitOperand(3, dst);
772}
773
774
775void X86_64Assembler::fildl(const Address& src) {
776  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
777  EmitUint8(0xDF);
778  EmitOperand(5, src);
779}
780
781
782void X86_64Assembler::fincstp() {
783  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
784  EmitUint8(0xD9);
785  EmitUint8(0xF7);
786}
787
788
789void X86_64Assembler::ffree(const Immediate& index) {
790  CHECK_LT(index.value(), 7);
791  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
792  EmitUint8(0xDD);
793  EmitUint8(0xC0 + index.value());
794}
795
796
797void X86_64Assembler::fsin() {
798  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
799  EmitUint8(0xD9);
800  EmitUint8(0xFE);
801}
802
803
804void X86_64Assembler::fcos() {
805  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
806  EmitUint8(0xD9);
807  EmitUint8(0xFF);
808}
809
810
811void X86_64Assembler::fptan() {
812  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
813  EmitUint8(0xD9);
814  EmitUint8(0xF2);
815}
816
817
818void X86_64Assembler::xchgl(CpuRegister dst, CpuRegister src) {
819  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
820  EmitOptionalRex32(dst, src);
821  EmitUint8(0x87);
822  EmitRegisterOperand(dst.LowBits(), src.LowBits());
823}
824
825void X86_64Assembler::xchgl(CpuRegister reg, const Address& address) {
826  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
827  EmitOptionalRex32(reg, address);
828  EmitUint8(0x87);
829  EmitOperand(reg.LowBits(), address);
830}
831
832
833void X86_64Assembler::cmpl(CpuRegister reg, const Immediate& imm) {
834  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
835  EmitOptionalRex32(reg);
836  EmitComplex(7, Operand(reg), imm);
837}
838
839
840void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) {
841  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
842  EmitOptionalRex32(reg0, reg1);
843  EmitUint8(0x3B);
844  EmitOperand(reg0.LowBits(), Operand(reg1));
845}
846
847
848void X86_64Assembler::cmpl(CpuRegister reg, const Address& address) {
849  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
850  EmitOptionalRex32(reg, address);
851  EmitUint8(0x3B);
852  EmitOperand(reg.LowBits(), address);
853}
854
855
856void X86_64Assembler::cmpq(CpuRegister reg0, CpuRegister reg1) {
857  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
858  EmitRex64(reg0, reg1);
859  EmitUint8(0x3B);
860  EmitOperand(reg0.LowBits(), Operand(reg1));
861}
862
863
864void X86_64Assembler::addl(CpuRegister dst, CpuRegister src) {
865  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
866  EmitOptionalRex32(dst, src);
867  EmitUint8(0x03);
868  EmitRegisterOperand(dst.LowBits(), src.LowBits());
869}
870
871
872void X86_64Assembler::addl(CpuRegister reg, const Address& address) {
873  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
874  EmitOptionalRex32(reg, address);
875  EmitUint8(0x03);
876  EmitOperand(reg.LowBits(), address);
877}
878
879
880void X86_64Assembler::cmpl(const Address& address, CpuRegister reg) {
881  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
882  EmitOptionalRex32(reg, address);
883  EmitUint8(0x39);
884  EmitOperand(reg.LowBits(), address);
885}
886
887
888void X86_64Assembler::cmpl(const Address& address, const Immediate& imm) {
889  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
890  EmitOptionalRex32(address);
891  EmitComplex(7, address, imm);
892}
893
894
895void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) {
896  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
897  EmitOptionalRex32(reg1, reg2);
898  EmitUint8(0x85);
899  EmitRegisterOperand(reg1.LowBits(), reg2.LowBits());
900}
901
902
903void X86_64Assembler::testl(CpuRegister reg, const Immediate& immediate) {
904  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
905  // For registers that have a byte variant (RAX, RBX, RCX, and RDX)
906  // we only test the byte CpuRegister to keep the encoding short.
907  if (immediate.is_uint8() && reg.AsRegister() < 4) {
908    // Use zero-extended 8-bit immediate.
909    if (reg.AsRegister() == RAX) {
910      EmitUint8(0xA8);
911    } else {
912      EmitUint8(0xF6);
913      EmitUint8(0xC0 + reg.AsRegister());
914    }
915    EmitUint8(immediate.value() & 0xFF);
916  } else if (reg.AsRegister() == RAX) {
917    // Use short form if the destination is RAX.
918    EmitUint8(0xA9);
919    EmitImmediate(immediate);
920  } else {
921    EmitOptionalRex32(reg);
922    EmitUint8(0xF7);
923    EmitOperand(0, Operand(reg));
924    EmitImmediate(immediate);
925  }
926}
927
928
929void X86_64Assembler::andl(CpuRegister dst, CpuRegister src) {
930  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
931  EmitOptionalRex32(dst, src);
932  EmitUint8(0x23);
933  EmitOperand(dst.LowBits(), Operand(src));
934}
935
936
937void X86_64Assembler::andl(CpuRegister dst, const Immediate& imm) {
938  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
939  EmitOptionalRex32(dst);
940  EmitComplex(4, Operand(dst), imm);
941}
942
943
944void X86_64Assembler::orl(CpuRegister dst, CpuRegister src) {
945  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
946  EmitOptionalRex32(dst, src);
947  EmitUint8(0x0B);
948  EmitOperand(dst.LowBits(), Operand(src));
949}
950
951
952void X86_64Assembler::orl(CpuRegister dst, const Immediate& imm) {
953  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
954  EmitOptionalRex32(dst);
955  EmitComplex(1, Operand(dst), imm);
956}
957
958
959void X86_64Assembler::xorl(CpuRegister dst, CpuRegister src) {
960  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
961  EmitOptionalRex32(dst, src);
962  EmitUint8(0x33);
963  EmitOperand(dst.LowBits(), Operand(src));
964}
965
966
967void X86_64Assembler::xorq(CpuRegister dst, const Immediate& imm) {
968  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
969  CHECK(imm.is_int32());  // xorq only supports 32b immediate.
970  EmitRex64(dst);
971  EmitComplex(6, Operand(dst), imm);
972}
973
974#if 0
975void X86_64Assembler::rex(bool force, bool w, Register* r, Register* x, Register* b) {
976  // REX.WRXB
977  // W - 64-bit operand
978  // R - MODRM.reg
979  // X - SIB.index
980  // B - MODRM.rm/SIB.base
981  uint8_t rex = force ? 0x40 : 0;
982  if (w) {
983    rex |= 0x48;  // REX.W000
984  }
985  if (r != nullptr && *r >= Register::R8 && *r < Register::kNumberOfCpuRegisters) {
986    rex |= 0x44;  // REX.0R00
987    *r = static_cast<Register>(*r - 8);
988  }
989  if (x != nullptr && *x >= Register::R8 && *x < Register::kNumberOfCpuRegisters) {
990    rex |= 0x42;  // REX.00X0
991    *x = static_cast<Register>(*x - 8);
992  }
993  if (b != nullptr && *b >= Register::R8 && *b < Register::kNumberOfCpuRegisters) {
994    rex |= 0x41;  // REX.000B
995    *b = static_cast<Register>(*b - 8);
996  }
997  if (rex != 0) {
998    EmitUint8(rex);
999  }
1000}
1001
1002void X86_64Assembler::rex_reg_mem(bool force, bool w, Register* dst, const Address& mem) {
1003  // REX.WRXB
1004  // W - 64-bit operand
1005  // R - MODRM.reg
1006  // X - SIB.index
1007  // B - MODRM.rm/SIB.base
1008  uint8_t rex = mem->rex();
1009  if (force) {
1010    rex |= 0x40;  // REX.0000
1011  }
1012  if (w) {
1013    rex |= 0x48;  // REX.W000
1014  }
1015  if (dst != nullptr && *dst >= Register::R8 && *dst < Register::kNumberOfCpuRegisters) {
1016    rex |= 0x44;  // REX.0R00
1017    *dst = static_cast<Register>(*dst - 8);
1018  }
1019  if (rex != 0) {
1020    EmitUint8(rex);
1021  }
1022}
1023
1024void rex_mem_reg(bool force, bool w, Address* mem, Register* src);
1025#endif
1026
1027void X86_64Assembler::addl(CpuRegister reg, const Immediate& imm) {
1028  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1029  EmitOptionalRex32(reg);
1030  EmitComplex(0, Operand(reg), imm);
1031}
1032
1033
1034void X86_64Assembler::addq(CpuRegister reg, const Immediate& imm) {
1035  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1036  CHECK(imm.is_int32());  // addq only supports 32b immediate.
1037  EmitRex64(reg);
1038  EmitComplex(0, Operand(reg), imm);
1039}
1040
1041
1042void X86_64Assembler::addq(CpuRegister dst, CpuRegister src) {
1043  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1044  // 0x01 is addq r/m64 <- r/m64 + r64, with op1 in r/m and op2 in reg: so reverse EmitRex64
1045  EmitRex64(src, dst);
1046  EmitUint8(0x01);
1047  EmitRegisterOperand(src.LowBits(), dst.LowBits());
1048}
1049
1050
1051void X86_64Assembler::addl(const Address& address, CpuRegister reg) {
1052  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1053  EmitOptionalRex32(reg, address);
1054  EmitUint8(0x01);
1055  EmitOperand(reg.LowBits(), address);
1056}
1057
1058
1059void X86_64Assembler::addl(const Address& address, const Immediate& imm) {
1060  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1061  EmitOptionalRex32(address);
1062  EmitComplex(0, address, imm);
1063}
1064
1065
1066void X86_64Assembler::subl(CpuRegister dst, CpuRegister src) {
1067  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1068  EmitOptionalRex32(dst, src);
1069  EmitUint8(0x2B);
1070  EmitOperand(dst.LowBits(), Operand(src));
1071}
1072
1073
1074void X86_64Assembler::subl(CpuRegister reg, const Immediate& imm) {
1075  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1076  EmitOptionalRex32(reg);
1077  EmitComplex(5, Operand(reg), imm);
1078}
1079
1080
1081void X86_64Assembler::subq(CpuRegister reg, const Immediate& imm) {
1082  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1083  CHECK(imm.is_int32());  // subq only supports 32b immediate.
1084  EmitRex64(reg);
1085  EmitComplex(5, Operand(reg), imm);
1086}
1087
1088
1089void X86_64Assembler::subq(CpuRegister dst, CpuRegister src) {
1090  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1091  EmitRex64(dst, src);
1092  EmitUint8(0x2B);
1093  EmitRegisterOperand(dst.LowBits(), src.LowBits());
1094}
1095
1096
1097void X86_64Assembler::subl(CpuRegister reg, const Address& address) {
1098  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1099  EmitOptionalRex32(reg, address);
1100  EmitUint8(0x2B);
1101  EmitOperand(reg.LowBits(), address);
1102}
1103
1104
1105void X86_64Assembler::cdq() {
1106  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1107  EmitUint8(0x99);
1108}
1109
1110
1111void X86_64Assembler::idivl(CpuRegister reg) {
1112  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1113  EmitOptionalRex32(reg);
1114  EmitUint8(0xF7);
1115  EmitUint8(0xF8 | reg.LowBits());
1116}
1117
1118
1119void X86_64Assembler::imull(CpuRegister dst, CpuRegister src) {
1120  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1121  EmitOptionalRex32(dst, src);
1122  EmitUint8(0x0F);
1123  EmitUint8(0xAF);
1124  EmitOperand(dst.LowBits(), Operand(src));
1125}
1126
1127
1128void X86_64Assembler::imull(CpuRegister reg, const Immediate& imm) {
1129  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1130  EmitOptionalRex32(reg);
1131  EmitUint8(0x69);
1132  EmitOperand(reg.LowBits(), Operand(reg));
1133  EmitImmediate(imm);
1134}
1135
1136
1137void X86_64Assembler::imull(CpuRegister reg, const Address& address) {
1138  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1139  EmitOptionalRex32(reg, address);
1140  EmitUint8(0x0F);
1141  EmitUint8(0xAF);
1142  EmitOperand(reg.LowBits(), address);
1143}
1144
1145
1146void X86_64Assembler::imull(CpuRegister reg) {
1147  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1148  EmitOptionalRex32(reg);
1149  EmitUint8(0xF7);
1150  EmitOperand(5, Operand(reg));
1151}
1152
1153
1154void X86_64Assembler::imull(const Address& address) {
1155  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1156  EmitOptionalRex32(address);
1157  EmitUint8(0xF7);
1158  EmitOperand(5, address);
1159}
1160
1161
1162void X86_64Assembler::mull(CpuRegister reg) {
1163  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1164  EmitOptionalRex32(reg);
1165  EmitUint8(0xF7);
1166  EmitOperand(4, Operand(reg));
1167}
1168
1169
1170void X86_64Assembler::mull(const Address& address) {
1171  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1172  EmitOptionalRex32(address);
1173  EmitUint8(0xF7);
1174  EmitOperand(4, address);
1175}
1176
1177
1178
1179void X86_64Assembler::shll(CpuRegister reg, const Immediate& imm) {
1180  EmitGenericShift(4, reg, imm);
1181}
1182
1183
1184void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) {
1185  EmitGenericShift(4, operand, shifter);
1186}
1187
1188
1189void X86_64Assembler::shrl(CpuRegister reg, const Immediate& imm) {
1190  EmitGenericShift(5, reg, imm);
1191}
1192
1193
1194void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) {
1195  EmitGenericShift(5, operand, shifter);
1196}
1197
1198
1199void X86_64Assembler::sarl(CpuRegister reg, const Immediate& imm) {
1200  EmitGenericShift(7, reg, imm);
1201}
1202
1203
1204void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) {
1205  EmitGenericShift(7, operand, shifter);
1206}
1207
1208
1209void X86_64Assembler::negl(CpuRegister reg) {
1210  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1211  EmitOptionalRex32(reg);
1212  EmitUint8(0xF7);
1213  EmitOperand(3, Operand(reg));
1214}
1215
1216
1217void X86_64Assembler::notl(CpuRegister reg) {
1218  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1219  EmitOptionalRex32(reg);
1220  EmitUint8(0xF7);
1221  EmitUint8(0xD0 | reg.LowBits());
1222}
1223
1224
1225void X86_64Assembler::enter(const Immediate& imm) {
1226  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1227  EmitUint8(0xC8);
1228  CHECK(imm.is_uint16());
1229  EmitUint8(imm.value() & 0xFF);
1230  EmitUint8((imm.value() >> 8) & 0xFF);
1231  EmitUint8(0x00);
1232}
1233
1234
1235void X86_64Assembler::leave() {
1236  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1237  EmitUint8(0xC9);
1238}
1239
1240
1241void X86_64Assembler::ret() {
1242  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1243  EmitUint8(0xC3);
1244}
1245
1246
1247void X86_64Assembler::ret(const Immediate& imm) {
1248  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1249  EmitUint8(0xC2);
1250  CHECK(imm.is_uint16());
1251  EmitUint8(imm.value() & 0xFF);
1252  EmitUint8((imm.value() >> 8) & 0xFF);
1253}
1254
1255
1256
1257void X86_64Assembler::nop() {
1258  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1259  EmitUint8(0x90);
1260}
1261
1262
1263void X86_64Assembler::int3() {
1264  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1265  EmitUint8(0xCC);
1266}
1267
1268
1269void X86_64Assembler::hlt() {
1270  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1271  EmitUint8(0xF4);
1272}
1273
1274
1275void X86_64Assembler::j(Condition condition, Label* label) {
1276  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1277  if (label->IsBound()) {
1278    static const int kShortSize = 2;
1279    static const int kLongSize = 6;
1280    int offset = label->Position() - buffer_.Size();
1281    CHECK_LE(offset, 0);
1282    if (IsInt(8, offset - kShortSize)) {
1283      EmitUint8(0x70 + condition);
1284      EmitUint8((offset - kShortSize) & 0xFF);
1285    } else {
1286      EmitUint8(0x0F);
1287      EmitUint8(0x80 + condition);
1288      EmitInt32(offset - kLongSize);
1289    }
1290  } else {
1291    EmitUint8(0x0F);
1292    EmitUint8(0x80 + condition);
1293    EmitLabelLink(label);
1294  }
1295}
1296
1297
1298void X86_64Assembler::jmp(CpuRegister reg) {
1299  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1300  EmitOptionalRex32(reg);
1301  EmitUint8(0xFF);
1302  EmitRegisterOperand(4, reg.LowBits());
1303}
1304
1305void X86_64Assembler::jmp(const Address& address) {
1306  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1307  EmitOptionalRex32(address);
1308  EmitUint8(0xFF);
1309  EmitOperand(4, address);
1310}
1311
1312void X86_64Assembler::jmp(Label* label) {
1313  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1314  if (label->IsBound()) {
1315    static const int kShortSize = 2;
1316    static const int kLongSize = 5;
1317    int offset = label->Position() - buffer_.Size();
1318    CHECK_LE(offset, 0);
1319    if (IsInt(8, offset - kShortSize)) {
1320      EmitUint8(0xEB);
1321      EmitUint8((offset - kShortSize) & 0xFF);
1322    } else {
1323      EmitUint8(0xE9);
1324      EmitInt32(offset - kLongSize);
1325    }
1326  } else {
1327    EmitUint8(0xE9);
1328    EmitLabelLink(label);
1329  }
1330}
1331
1332
1333X86_64Assembler* X86_64Assembler::lock() {
1334  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1335  EmitUint8(0xF0);
1336  return this;
1337}
1338
1339
1340void X86_64Assembler::cmpxchgl(const Address& address, CpuRegister reg) {
1341  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1342  EmitUint8(0x0F);
1343  EmitUint8(0xB1);
1344  EmitOperand(reg.LowBits(), address);
1345}
1346
1347void X86_64Assembler::mfence() {
1348  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1349  EmitUint8(0x0F);
1350  EmitUint8(0xAE);
1351  EmitUint8(0xF0);
1352}
1353
1354
1355X86_64Assembler* X86_64Assembler::gs() {
1356  // TODO: gs is a prefix and not an instruction
1357  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1358  EmitUint8(0x65);
1359  return this;
1360}
1361
1362
1363void X86_64Assembler::AddImmediate(CpuRegister reg, const Immediate& imm) {
1364  int value = imm.value();
1365  if (value != 0) {
1366    if (value > 0) {
1367      addl(reg, imm);
1368    } else {
1369      subl(reg, Immediate(value));
1370    }
1371  }
1372}
1373
1374
1375void X86_64Assembler::setcc(Condition condition, CpuRegister dst) {
1376  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1377  // RSP, RBP, RDI, RSI need rex prefix (else the pattern encodes ah/bh/ch/dh).
1378  if (dst.NeedsRex() || dst.AsRegister() > 3) {
1379    EmitOptionalRex(true, false, false, false, dst.NeedsRex());
1380  }
1381  EmitUint8(0x0F);
1382  EmitUint8(0x90 + condition);
1383  EmitUint8(0xC0 + dst.LowBits());
1384}
1385
1386
1387void X86_64Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
1388  // TODO: Need to have a code constants table.
1389  int64_t constant = bit_cast<int64_t, double>(value);
1390  pushq(Immediate(High32Bits(constant)));
1391  pushq(Immediate(Low32Bits(constant)));
1392  movsd(dst, Address(CpuRegister(RSP), 0));
1393  addq(CpuRegister(RSP), Immediate(2 * kWordSize));
1394}
1395
1396
1397void X86_64Assembler::FloatNegate(XmmRegister f) {
1398  static const struct {
1399    uint32_t a;
1400    uint32_t b;
1401    uint32_t c;
1402    uint32_t d;
1403  } float_negate_constant __attribute__((aligned(16))) =
1404      { 0x80000000, 0x00000000, 0x80000000, 0x00000000 };
1405  xorps(f, Address::Absolute(reinterpret_cast<uword>(&float_negate_constant)));
1406}
1407
1408
1409void X86_64Assembler::DoubleNegate(XmmRegister d) {
1410  static const struct {
1411    uint64_t a;
1412    uint64_t b;
1413  } double_negate_constant __attribute__((aligned(16))) =
1414      {0x8000000000000000LL, 0x8000000000000000LL};
1415  xorpd(d, Address::Absolute(reinterpret_cast<uword>(&double_negate_constant)));
1416}
1417
1418
1419void X86_64Assembler::DoubleAbs(XmmRegister reg) {
1420  static const struct {
1421    uint64_t a;
1422    uint64_t b;
1423  } double_abs_constant __attribute__((aligned(16))) =
1424      {0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL};
1425  andpd(reg, Address::Absolute(reinterpret_cast<uword>(&double_abs_constant)));
1426}
1427
1428
1429void X86_64Assembler::Align(int alignment, int offset) {
1430  CHECK(IsPowerOfTwo(alignment));
1431  // Emit nop instruction until the real position is aligned.
1432  while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
1433    nop();
1434  }
1435}
1436
1437
1438void X86_64Assembler::Bind(Label* label) {
1439  int bound = buffer_.Size();
1440  CHECK(!label->IsBound());  // Labels can only be bound once.
1441  while (label->IsLinked()) {
1442    int position = label->LinkPosition();
1443    int next = buffer_.Load<int32_t>(position);
1444    buffer_.Store<int32_t>(position, bound - (position + 4));
1445    label->position_ = next;
1446  }
1447  label->BindTo(bound);
1448}
1449
1450
1451void X86_64Assembler::EmitOperand(uint8_t reg_or_opcode, const Operand& operand) {
1452  CHECK_GE(reg_or_opcode, 0);
1453  CHECK_LT(reg_or_opcode, 8);
1454  const int length = operand.length_;
1455  CHECK_GT(length, 0);
1456  // Emit the ModRM byte updated with the given reg value.
1457  CHECK_EQ(operand.encoding_[0] & 0x38, 0);
1458  EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
1459  // Emit the rest of the encoded operand.
1460  for (int i = 1; i < length; i++) {
1461    EmitUint8(operand.encoding_[i]);
1462  }
1463}
1464
1465
1466void X86_64Assembler::EmitImmediate(const Immediate& imm) {
1467  if (imm.is_int32()) {
1468    EmitInt32(static_cast<int32_t>(imm.value()));
1469  } else {
1470    EmitInt64(imm.value());
1471  }
1472}
1473
1474
1475void X86_64Assembler::EmitComplex(uint8_t reg_or_opcode,
1476                                  const Operand& operand,
1477                                  const Immediate& immediate) {
1478  CHECK_GE(reg_or_opcode, 0);
1479  CHECK_LT(reg_or_opcode, 8);
1480  if (immediate.is_int8()) {
1481    // Use sign-extended 8-bit immediate.
1482    EmitUint8(0x83);
1483    EmitOperand(reg_or_opcode, operand);
1484    EmitUint8(immediate.value() & 0xFF);
1485  } else if (operand.IsRegister(CpuRegister(RAX))) {
1486    // Use short form if the destination is eax.
1487    EmitUint8(0x05 + (reg_or_opcode << 3));
1488    EmitImmediate(immediate);
1489  } else {
1490    EmitUint8(0x81);
1491    EmitOperand(reg_or_opcode, operand);
1492    EmitImmediate(immediate);
1493  }
1494}
1495
1496
1497void X86_64Assembler::EmitLabel(Label* label, int instruction_size) {
1498  if (label->IsBound()) {
1499    int offset = label->Position() - buffer_.Size();
1500    CHECK_LE(offset, 0);
1501    EmitInt32(offset - instruction_size);
1502  } else {
1503    EmitLabelLink(label);
1504  }
1505}
1506
1507
1508void X86_64Assembler::EmitLabelLink(Label* label) {
1509  CHECK(!label->IsBound());
1510  int position = buffer_.Size();
1511  EmitInt32(label->position_);
1512  label->LinkTo(position);
1513}
1514
1515
1516void X86_64Assembler::EmitGenericShift(int reg_or_opcode,
1517                                    CpuRegister reg,
1518                                    const Immediate& imm) {
1519  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1520  CHECK(imm.is_int8());
1521  if (imm.value() == 1) {
1522    EmitUint8(0xD1);
1523    EmitOperand(reg_or_opcode, Operand(reg));
1524  } else {
1525    EmitUint8(0xC1);
1526    EmitOperand(reg_or_opcode, Operand(reg));
1527    EmitUint8(imm.value() & 0xFF);
1528  }
1529}
1530
1531
1532void X86_64Assembler::EmitGenericShift(int reg_or_opcode,
1533                                    CpuRegister operand,
1534                                    CpuRegister shifter) {
1535  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1536  CHECK_EQ(shifter.AsRegister(), RCX);
1537  EmitUint8(0xD3);
1538  EmitOperand(reg_or_opcode, Operand(operand));
1539}
1540
1541void X86_64Assembler::EmitOptionalRex(bool force, bool w, bool r, bool x, bool b) {
1542  // REX.WRXB
1543  // W - 64-bit operand
1544  // R - MODRM.reg
1545  // X - SIB.index
1546  // B - MODRM.rm/SIB.base
1547  uint8_t rex = force ? 0x40 : 0;
1548  if (w) {
1549    rex |= 0x48;  // REX.W000
1550  }
1551  if (r) {
1552    rex |= 0x44;  // REX.0R00
1553  }
1554  if (x) {
1555    rex |= 0x42;  // REX.00X0
1556  }
1557  if (b) {
1558    rex |= 0x41;  // REX.000B
1559  }
1560  if (rex != 0) {
1561    EmitUint8(rex);
1562  }
1563}
1564
1565void X86_64Assembler::EmitOptionalRex32(CpuRegister reg) {
1566  EmitOptionalRex(false, false, false, false, reg.NeedsRex());
1567}
1568
1569void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, CpuRegister src) {
1570  EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1571}
1572
1573void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, XmmRegister src) {
1574  EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1575}
1576
1577void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, XmmRegister src) {
1578  EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1579}
1580
1581void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, CpuRegister src) {
1582  EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1583}
1584
1585void X86_64Assembler::EmitOptionalRex32(const Operand& operand) {
1586  uint8_t rex = operand.rex();
1587  if (rex != 0) {
1588    EmitUint8(rex);
1589  }
1590}
1591
1592void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, const Operand& operand) {
1593  uint8_t rex = operand.rex();
1594  if (dst.NeedsRex()) {
1595    rex |= 0x44;  // REX.0R00
1596  }
1597  if (rex != 0) {
1598    EmitUint8(rex);
1599  }
1600}
1601
1602void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, const Operand& operand) {
1603  uint8_t rex = operand.rex();
1604  if (dst.NeedsRex()) {
1605    rex |= 0x44;  // REX.0R00
1606  }
1607  if (rex != 0) {
1608    EmitUint8(rex);
1609  }
1610}
1611
1612void X86_64Assembler::EmitRex64(CpuRegister reg) {
1613  EmitOptionalRex(false, true, false, false, reg.NeedsRex());
1614}
1615
1616void X86_64Assembler::EmitRex64(CpuRegister dst, CpuRegister src) {
1617  EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex());
1618}
1619
1620void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) {
1621  uint8_t rex = 0x48 | operand.rex();  // REX.W000
1622  if (dst.NeedsRex()) {
1623    rex |= 0x44;  // REX.0R00
1624  }
1625  if (rex != 0) {
1626    EmitUint8(rex);
1627  }
1628}
1629
1630void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) {
1631  EmitOptionalRex(true, false, dst.NeedsRex(), false, src.NeedsRex());
1632}
1633
1634void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) {
1635  uint8_t rex = 0x40 | operand.rex();  // REX.0000
1636  if (dst.NeedsRex()) {
1637    rex |= 0x44;  // REX.0R00
1638  }
1639  if (rex != 0) {
1640    EmitUint8(rex);
1641  }
1642}
1643
1644constexpr size_t kFramePointerSize = 8;
1645
1646void X86_64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
1647                                 const std::vector<ManagedRegister>& spill_regs,
1648                                 const ManagedRegisterEntrySpills& entry_spills) {
1649  CHECK_ALIGNED(frame_size, kStackAlignment);
1650  for (int i = spill_regs.size() - 1; i >= 0; --i) {
1651    pushq(spill_regs.at(i).AsX86_64().AsCpuRegister());
1652  }
1653  // return address then method on stack
1654  addq(CpuRegister(RSP), Immediate(-frame_size + (spill_regs.size() * kFramePointerSize) +
1655                                   kFramePointerSize /*method*/ + kFramePointerSize /*return address*/));
1656  pushq(method_reg.AsX86_64().AsCpuRegister());
1657
1658  for (size_t i = 0; i < entry_spills.size(); ++i) {
1659    ManagedRegisterSpill spill = entry_spills.at(i);
1660    if (spill.AsX86_64().IsCpuRegister()) {
1661      if (spill.getSize() == 8) {
1662        movq(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
1663             spill.AsX86_64().AsCpuRegister());
1664      } else {
1665        CHECK_EQ(spill.getSize(), 4);
1666        movl(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsCpuRegister());
1667      }
1668    } else {
1669      if (spill.getSize() == 8) {
1670        movsd(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
1671      } else {
1672        CHECK_EQ(spill.getSize(), 4);
1673        movss(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
1674      }
1675    }
1676  }
1677}
1678
1679void X86_64Assembler::RemoveFrame(size_t frame_size,
1680                            const std::vector<ManagedRegister>& spill_regs) {
1681  CHECK_ALIGNED(frame_size, kStackAlignment);
1682  addq(CpuRegister(RSP), Immediate(frame_size - (spill_regs.size() * kFramePointerSize) - kFramePointerSize));
1683  for (size_t i = 0; i < spill_regs.size(); ++i) {
1684    popq(spill_regs.at(i).AsX86_64().AsCpuRegister());
1685  }
1686  ret();
1687}
1688
1689void X86_64Assembler::IncreaseFrameSize(size_t adjust) {
1690  CHECK_ALIGNED(adjust, kStackAlignment);
1691  addq(CpuRegister(RSP), Immediate(-adjust));
1692}
1693
1694void X86_64Assembler::DecreaseFrameSize(size_t adjust) {
1695  CHECK_ALIGNED(adjust, kStackAlignment);
1696  addq(CpuRegister(RSP), Immediate(adjust));
1697}
1698
1699void X86_64Assembler::Store(FrameOffset offs, ManagedRegister msrc, size_t size) {
1700  X86_64ManagedRegister src = msrc.AsX86_64();
1701  if (src.IsNoRegister()) {
1702    CHECK_EQ(0u, size);
1703  } else if (src.IsCpuRegister()) {
1704    if (size == 4) {
1705      CHECK_EQ(4u, size);
1706      movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
1707    } else {
1708      CHECK_EQ(8u, size);
1709      movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
1710    }
1711  } else if (src.IsRegisterPair()) {
1712    CHECK_EQ(0u, size);
1713    movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow());
1714    movq(Address(CpuRegister(RSP), FrameOffset(offs.Int32Value()+4)),
1715         src.AsRegisterPairHigh());
1716  } else if (src.IsX87Register()) {
1717    if (size == 4) {
1718      fstps(Address(CpuRegister(RSP), offs));
1719    } else {
1720      fstpl(Address(CpuRegister(RSP), offs));
1721    }
1722  } else {
1723    CHECK(src.IsXmmRegister());
1724    if (size == 4) {
1725      movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
1726    } else {
1727      movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
1728    }
1729  }
1730}
1731
1732void X86_64Assembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
1733  X86_64ManagedRegister src = msrc.AsX86_64();
1734  CHECK(src.IsCpuRegister());
1735  movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
1736}
1737
1738void X86_64Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
1739  X86_64ManagedRegister src = msrc.AsX86_64();
1740  CHECK(src.IsCpuRegister());
1741  movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
1742}
1743
1744void X86_64Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
1745                                            ManagedRegister) {
1746  movl(Address(CpuRegister(RSP), dest), Immediate(imm));  // TODO(64) movq?
1747}
1748
1749void X86_64Assembler::StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm,
1750                                               ManagedRegister) {
1751  gs()->movl(Address::Absolute(dest, true), Immediate(imm));  // TODO(64) movq?
1752}
1753
1754void X86_64Assembler::StoreStackOffsetToThread64(ThreadOffset<8> thr_offs,
1755                                                 FrameOffset fr_offs,
1756                                                 ManagedRegister mscratch) {
1757  X86_64ManagedRegister scratch = mscratch.AsX86_64();
1758  CHECK(scratch.IsCpuRegister());
1759  leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), fr_offs));
1760  gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
1761}
1762
1763void X86_64Assembler::StoreStackPointerToThread64(ThreadOffset<8> thr_offs) {
1764  gs()->movq(Address::Absolute(thr_offs, true), CpuRegister(RSP));
1765}
1766
1767void X86_64Assembler::StoreSpanning(FrameOffset /*dst*/, ManagedRegister /*src*/,
1768                                 FrameOffset /*in_off*/, ManagedRegister /*scratch*/) {
1769  UNIMPLEMENTED(FATAL);  // this case only currently exists for ARM
1770}
1771
1772void X86_64Assembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
1773  X86_64ManagedRegister dest = mdest.AsX86_64();
1774  if (dest.IsNoRegister()) {
1775    CHECK_EQ(0u, size);
1776  } else if (dest.IsCpuRegister()) {
1777    if (size == 4) {
1778      CHECK_EQ(4u, size);
1779      movl(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1780    } else {
1781      CHECK_EQ(8u, size);
1782      movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1783    }
1784  } else if (dest.IsRegisterPair()) {
1785    CHECK_EQ(0u, size);
1786    movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src));
1787    movq(dest.AsRegisterPairHigh(), Address(CpuRegister(RSP), FrameOffset(src.Int32Value()+4)));
1788  } else if (dest.IsX87Register()) {
1789    if (size == 4) {
1790      flds(Address(CpuRegister(RSP), src));
1791    } else {
1792      fldl(Address(CpuRegister(RSP), src));
1793    }
1794  } else {
1795    CHECK(dest.IsXmmRegister());
1796    if (size == 4) {
1797      movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
1798    } else {
1799      movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
1800    }
1801  }
1802}
1803
1804void X86_64Assembler::LoadFromThread64(ManagedRegister mdest, ThreadOffset<8> src, size_t size) {
1805  X86_64ManagedRegister dest = mdest.AsX86_64();
1806  if (dest.IsNoRegister()) {
1807    CHECK_EQ(0u, size);
1808  } else if (dest.IsCpuRegister()) {
1809    CHECK_EQ(4u, size);
1810    gs()->movl(dest.AsCpuRegister(), Address::Absolute(src, true));
1811  } else if (dest.IsRegisterPair()) {
1812    CHECK_EQ(8u, size);
1813    gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true));
1814  } else if (dest.IsX87Register()) {
1815    if (size == 4) {
1816      gs()->flds(Address::Absolute(src, true));
1817    } else {
1818      gs()->fldl(Address::Absolute(src, true));
1819    }
1820  } else {
1821    CHECK(dest.IsXmmRegister());
1822    if (size == 4) {
1823      gs()->movss(dest.AsXmmRegister(), Address::Absolute(src, true));
1824    } else {
1825      gs()->movsd(dest.AsXmmRegister(), Address::Absolute(src, true));
1826    }
1827  }
1828}
1829
1830void X86_64Assembler::LoadRef(ManagedRegister mdest, FrameOffset  src) {
1831  X86_64ManagedRegister dest = mdest.AsX86_64();
1832  CHECK(dest.IsCpuRegister());
1833  movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1834}
1835
1836void X86_64Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base,
1837                           MemberOffset offs) {
1838  X86_64ManagedRegister dest = mdest.AsX86_64();
1839  CHECK(dest.IsCpuRegister() && dest.IsCpuRegister());
1840  movq(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs));
1841}
1842
1843void X86_64Assembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base,
1844                              Offset offs) {
1845  X86_64ManagedRegister dest = mdest.AsX86_64();
1846  CHECK(dest.IsCpuRegister() && dest.IsCpuRegister());
1847  movq(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs));
1848}
1849
1850void X86_64Assembler::LoadRawPtrFromThread64(ManagedRegister mdest, ThreadOffset<8> offs) {
1851  X86_64ManagedRegister dest = mdest.AsX86_64();
1852  CHECK(dest.IsCpuRegister());
1853  gs()->movq(dest.AsCpuRegister(), Address::Absolute(offs, true));
1854}
1855
1856void X86_64Assembler::SignExtend(ManagedRegister mreg, size_t size) {
1857  X86_64ManagedRegister reg = mreg.AsX86_64();
1858  CHECK(size == 1 || size == 2) << size;
1859  CHECK(reg.IsCpuRegister()) << reg;
1860  if (size == 1) {
1861    movsxb(reg.AsCpuRegister(), reg.AsCpuRegister());
1862  } else {
1863    movsxw(reg.AsCpuRegister(), reg.AsCpuRegister());
1864  }
1865}
1866
1867void X86_64Assembler::ZeroExtend(ManagedRegister mreg, size_t size) {
1868  X86_64ManagedRegister reg = mreg.AsX86_64();
1869  CHECK(size == 1 || size == 2) << size;
1870  CHECK(reg.IsCpuRegister()) << reg;
1871  if (size == 1) {
1872    movzxb(reg.AsCpuRegister(), reg.AsCpuRegister());
1873  } else {
1874    movzxw(reg.AsCpuRegister(), reg.AsCpuRegister());
1875  }
1876}
1877
1878void X86_64Assembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) {
1879  X86_64ManagedRegister dest = mdest.AsX86_64();
1880  X86_64ManagedRegister src = msrc.AsX86_64();
1881  if (!dest.Equals(src)) {
1882    if (dest.IsCpuRegister() && src.IsCpuRegister()) {
1883      movq(dest.AsCpuRegister(), src.AsCpuRegister());
1884    } else if (src.IsX87Register() && dest.IsXmmRegister()) {
1885      // Pass via stack and pop X87 register
1886      subl(CpuRegister(RSP), Immediate(16));
1887      if (size == 4) {
1888        CHECK_EQ(src.AsX87Register(), ST0);
1889        fstps(Address(CpuRegister(RSP), 0));
1890        movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
1891      } else {
1892        CHECK_EQ(src.AsX87Register(), ST0);
1893        fstpl(Address(CpuRegister(RSP), 0));
1894        movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
1895      }
1896      addq(CpuRegister(RSP), Immediate(16));
1897    } else {
1898      // TODO: x87, SSE
1899      UNIMPLEMENTED(FATAL) << ": Move " << dest << ", " << src;
1900    }
1901  }
1902}
1903
1904void X86_64Assembler::CopyRef(FrameOffset dest, FrameOffset src,
1905                           ManagedRegister mscratch) {
1906  X86_64ManagedRegister scratch = mscratch.AsX86_64();
1907  CHECK(scratch.IsCpuRegister());
1908  movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), src));
1909  movl(Address(CpuRegister(RSP), dest), scratch.AsCpuRegister());
1910}
1911
1912void X86_64Assembler::CopyRawPtrFromThread64(FrameOffset fr_offs,
1913                                             ThreadOffset<8> thr_offs,
1914                                             ManagedRegister mscratch) {
1915  X86_64ManagedRegister scratch = mscratch.AsX86_64();
1916  CHECK(scratch.IsCpuRegister());
1917  gs()->movq(scratch.AsCpuRegister(), Address::Absolute(thr_offs, true));
1918  Store(fr_offs, scratch, 8);
1919}
1920
1921void X86_64Assembler::CopyRawPtrToThread64(ThreadOffset<8> thr_offs,
1922                                           FrameOffset fr_offs,
1923                                           ManagedRegister mscratch) {
1924  X86_64ManagedRegister scratch = mscratch.AsX86_64();
1925  CHECK(scratch.IsCpuRegister());
1926  Load(scratch, fr_offs, 8);
1927  gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
1928}
1929
1930void X86_64Assembler::Copy(FrameOffset dest, FrameOffset src,
1931                        ManagedRegister mscratch,
1932                        size_t size) {
1933  X86_64ManagedRegister scratch = mscratch.AsX86_64();
1934  if (scratch.IsCpuRegister() && size == 8) {
1935    Load(scratch, src, 4);
1936    Store(dest, scratch, 4);
1937    Load(scratch, FrameOffset(src.Int32Value() + 4), 4);
1938    Store(FrameOffset(dest.Int32Value() + 4), scratch, 4);
1939  } else {
1940    Load(scratch, src, size);
1941    Store(dest, scratch, size);
1942  }
1943}
1944
1945void X86_64Assembler::Copy(FrameOffset /*dst*/, ManagedRegister /*src_base*/, Offset /*src_offset*/,
1946                        ManagedRegister /*scratch*/, size_t /*size*/) {
1947  UNIMPLEMENTED(FATAL);
1948}
1949
1950void X86_64Assembler::Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
1951                        ManagedRegister scratch, size_t size) {
1952  CHECK(scratch.IsNoRegister());
1953  CHECK_EQ(size, 4u);
1954  pushq(Address(CpuRegister(RSP), src));
1955  popq(Address(dest_base.AsX86_64().AsCpuRegister(), dest_offset));
1956}
1957
1958void X86_64Assembler::Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
1959                        ManagedRegister mscratch, size_t size) {
1960  CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
1961  CHECK_EQ(size, 4u);
1962  movq(scratch, Address(CpuRegister(RSP), src_base));
1963  movq(scratch, Address(scratch, src_offset));
1964  movq(Address(CpuRegister(RSP), dest), scratch);
1965}
1966
1967void X86_64Assembler::Copy(ManagedRegister dest, Offset dest_offset,
1968                        ManagedRegister src, Offset src_offset,
1969                        ManagedRegister scratch, size_t size) {
1970  CHECK_EQ(size, 4u);
1971  CHECK(scratch.IsNoRegister());
1972  pushq(Address(src.AsX86_64().AsCpuRegister(), src_offset));
1973  popq(Address(dest.AsX86_64().AsCpuRegister(), dest_offset));
1974}
1975
1976void X86_64Assembler::Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
1977                        ManagedRegister mscratch, size_t size) {
1978  CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
1979  CHECK_EQ(size, 4u);
1980  CHECK_EQ(dest.Int32Value(), src.Int32Value());
1981  movq(scratch, Address(CpuRegister(RSP), src));
1982  pushq(Address(scratch, src_offset));
1983  popq(Address(scratch, dest_offset));
1984}
1985
1986void X86_64Assembler::MemoryBarrier(ManagedRegister) {
1987#if ANDROID_SMP != 0
1988  mfence();
1989#endif
1990}
1991
1992void X86_64Assembler::CreateHandleScopeEntry(ManagedRegister mout_reg,
1993                                   FrameOffset handle_scope_offset,
1994                                   ManagedRegister min_reg, bool null_allowed) {
1995  X86_64ManagedRegister out_reg = mout_reg.AsX86_64();
1996  X86_64ManagedRegister in_reg = min_reg.AsX86_64();
1997  if (in_reg.IsNoRegister()) {  // TODO(64): && null_allowed
1998    // Use out_reg as indicator of NULL
1999    in_reg = out_reg;
2000    // TODO: movzwl
2001    movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2002  }
2003  CHECK(in_reg.IsCpuRegister());
2004  CHECK(out_reg.IsCpuRegister());
2005  VerifyObject(in_reg, null_allowed);
2006  if (null_allowed) {
2007    Label null_arg;
2008    if (!out_reg.Equals(in_reg)) {
2009      xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister());
2010    }
2011    testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
2012    j(kZero, &null_arg);
2013    leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2014    Bind(&null_arg);
2015  } else {
2016    leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2017  }
2018}
2019
2020void X86_64Assembler::CreateHandleScopeEntry(FrameOffset out_off,
2021                                   FrameOffset handle_scope_offset,
2022                                   ManagedRegister mscratch,
2023                                   bool null_allowed) {
2024  X86_64ManagedRegister scratch = mscratch.AsX86_64();
2025  CHECK(scratch.IsCpuRegister());
2026  if (null_allowed) {
2027    Label null_arg;
2028    movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2029    testl(scratch.AsCpuRegister(), scratch.AsCpuRegister());
2030    j(kZero, &null_arg);
2031    leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2032    Bind(&null_arg);
2033  } else {
2034    leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
2035  }
2036  Store(out_off, scratch, 8);
2037}
2038
2039// Given a handle scope entry, load the associated reference.
2040void X86_64Assembler::LoadReferenceFromHandleScope(ManagedRegister mout_reg,
2041                                         ManagedRegister min_reg) {
2042  X86_64ManagedRegister out_reg = mout_reg.AsX86_64();
2043  X86_64ManagedRegister in_reg = min_reg.AsX86_64();
2044  CHECK(out_reg.IsCpuRegister());
2045  CHECK(in_reg.IsCpuRegister());
2046  Label null_arg;
2047  if (!out_reg.Equals(in_reg)) {
2048    xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister());
2049  }
2050  testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
2051  j(kZero, &null_arg);
2052  movq(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0));
2053  Bind(&null_arg);
2054}
2055
2056void X86_64Assembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) {
2057  // TODO: not validating references
2058}
2059
2060void X86_64Assembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) {
2061  // TODO: not validating references
2062}
2063
2064void X86_64Assembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister) {
2065  X86_64ManagedRegister base = mbase.AsX86_64();
2066  CHECK(base.IsCpuRegister());
2067  call(Address(base.AsCpuRegister(), offset.Int32Value()));
2068  // TODO: place reference map on call
2069}
2070
2071void X86_64Assembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) {
2072  CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
2073  movq(scratch, Address(CpuRegister(RSP), base));
2074  call(Address(scratch, offset));
2075}
2076
2077void X86_64Assembler::CallFromThread64(ThreadOffset<8> offset, ManagedRegister /*mscratch*/) {
2078  gs()->call(Address::Absolute(offset, true));
2079}
2080
2081void X86_64Assembler::GetCurrentThread(ManagedRegister tr) {
2082  gs()->movq(tr.AsX86_64().AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
2083}
2084
2085void X86_64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister mscratch) {
2086  X86_64ManagedRegister scratch = mscratch.AsX86_64();
2087  gs()->movq(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
2088  movq(Address(CpuRegister(RSP), offset), scratch.AsCpuRegister());
2089}
2090
2091// Slowpath entered when Thread::Current()->_exception is non-null
2092class X86_64ExceptionSlowPath FINAL : public SlowPath {
2093 public:
2094  explicit X86_64ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
2095  virtual void Emit(Assembler *sp_asm) OVERRIDE;
2096 private:
2097  const size_t stack_adjust_;
2098};
2099
2100void X86_64Assembler::ExceptionPoll(ManagedRegister /*scratch*/, size_t stack_adjust) {
2101  X86_64ExceptionSlowPath* slow = new X86_64ExceptionSlowPath(stack_adjust);
2102  buffer_.EnqueueSlowPath(slow);
2103  gs()->cmpl(Address::Absolute(Thread::ExceptionOffset<8>(), true), Immediate(0));
2104  j(kNotEqual, slow->Entry());
2105}
2106
2107void X86_64ExceptionSlowPath::Emit(Assembler *sasm) {
2108  X86_64Assembler* sp_asm = down_cast<X86_64Assembler*>(sasm);
2109#define __ sp_asm->
2110  __ Bind(&entry_);
2111  // Note: the return value is dead
2112  if (stack_adjust_ != 0) {  // Fix up the frame.
2113    __ DecreaseFrameSize(stack_adjust_);
2114  }
2115  // Pass exception as argument in RDI
2116  __ gs()->movq(CpuRegister(RDI), Address::Absolute(Thread::ExceptionOffset<8>(), true));
2117  __ gs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), true));
2118  // this call should never return
2119  __ int3();
2120#undef __
2121}
2122
2123}  // namespace x86_64
2124}  // namespace art
2125
2126