dex_instruction-inl.h revision 7934ac288acfb2552bb0b06ec1f61e5820d924a4 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_RUNTIME_DEX_INSTRUCTION_INL_H_
18#define ART_RUNTIME_DEX_INSTRUCTION_INL_H_
19
20#include "dex_instruction.h"
21
22namespace art {
23
24//------------------------------------------------------------------------------
25// VRegA
26//------------------------------------------------------------------------------
27inline int8_t Instruction::VRegA_10t() const {
28  DCHECK_EQ(FormatOf(Opcode()), k10t);
29  return static_cast<int8_t>(InstAA());
30}
31
32inline uint8_t Instruction::VRegA_10x() const {
33  DCHECK_EQ(FormatOf(Opcode()), k10x);
34  return InstAA();
35}
36
37inline uint4_t Instruction::VRegA_11n() const {
38  DCHECK_EQ(FormatOf(Opcode()), k11n);
39  return InstA();
40}
41
42inline uint8_t Instruction::VRegA_11x() const {
43  DCHECK_EQ(FormatOf(Opcode()), k11x);
44  return InstAA();
45}
46
47inline uint4_t Instruction::VRegA_12x() const {
48  DCHECK_EQ(FormatOf(Opcode()), k12x);
49  return InstA();
50}
51
52inline int16_t Instruction::VRegA_20t() const {
53  DCHECK_EQ(FormatOf(Opcode()), k20t);
54  return static_cast<int16_t>(Fetch16(1));
55}
56
57inline uint8_t Instruction::VRegA_21c() const {
58  DCHECK_EQ(FormatOf(Opcode()), k21c);
59  return InstAA();
60}
61
62inline uint8_t Instruction::VRegA_21h() const {
63  DCHECK_EQ(FormatOf(Opcode()), k21h);
64  return InstAA();
65}
66
67inline uint8_t Instruction::VRegA_21s() const {
68  DCHECK_EQ(FormatOf(Opcode()), k21s);
69  return InstAA();
70}
71
72inline uint8_t Instruction::VRegA_21t() const {
73  DCHECK_EQ(FormatOf(Opcode()), k21t);
74  return InstAA();
75}
76
77inline uint8_t Instruction::VRegA_22b() const {
78  DCHECK_EQ(FormatOf(Opcode()), k22b);
79  return InstAA();
80}
81
82inline uint4_t Instruction::VRegA_22c() const {
83  DCHECK_EQ(FormatOf(Opcode()), k22c);
84  return InstA();
85}
86
87inline uint4_t Instruction::VRegA_22s() const {
88  DCHECK_EQ(FormatOf(Opcode()), k22s);
89  return InstA();
90}
91
92inline uint4_t Instruction::VRegA_22t() const {
93  DCHECK_EQ(FormatOf(Opcode()), k22t);
94  return InstA();
95}
96
97inline uint8_t Instruction::VRegA_22x() const {
98  DCHECK_EQ(FormatOf(Opcode()), k22x);
99  return InstAA();
100}
101
102inline uint8_t Instruction::VRegA_23x() const {
103  DCHECK_EQ(FormatOf(Opcode()), k23x);
104  return InstAA();
105}
106
107inline int32_t Instruction::VRegA_30t() const {
108  DCHECK_EQ(FormatOf(Opcode()), k30t);
109  return static_cast<int32_t>(Fetch32(1));
110}
111
112inline uint8_t Instruction::VRegA_31c() const {
113  DCHECK_EQ(FormatOf(Opcode()), k31c);
114  return InstAA();
115}
116
117inline uint8_t Instruction::VRegA_31i() const {
118  DCHECK_EQ(FormatOf(Opcode()), k31i);
119  return InstAA();
120}
121
122inline uint8_t Instruction::VRegA_31t() const {
123  DCHECK_EQ(FormatOf(Opcode()), k31t);
124  return InstAA();
125}
126
127inline uint16_t Instruction::VRegA_32x() const {
128  DCHECK_EQ(FormatOf(Opcode()), k32x);
129  return Fetch16(1);
130}
131
132inline uint4_t Instruction::VRegA_35c() const {
133  DCHECK_EQ(FormatOf(Opcode()), k35c);
134  return InstB();  // This is labeled A in the spec.
135}
136
137inline uint8_t Instruction::VRegA_3rc() const {
138  DCHECK_EQ(FormatOf(Opcode()), k3rc);
139  return InstAA();
140}
141
142inline uint8_t Instruction::VRegA_51l() const {
143  DCHECK_EQ(FormatOf(Opcode()), k51l);
144  return InstAA();
145}
146
147//------------------------------------------------------------------------------
148// VRegB
149//------------------------------------------------------------------------------
150inline int4_t Instruction::VRegB_11n() const {
151  DCHECK_EQ(FormatOf(Opcode()), k11n);
152  return static_cast<int4_t>((InstB() << 28) >> 28);
153}
154
155inline uint4_t Instruction::VRegB_12x() const {
156  DCHECK_EQ(FormatOf(Opcode()), k12x);
157  return InstB();
158}
159
160inline uint16_t Instruction::VRegB_21c() const {
161  DCHECK_EQ(FormatOf(Opcode()), k21c);
162  return Fetch16(1);
163}
164
165inline uint16_t Instruction::VRegB_21h() const {
166  DCHECK_EQ(FormatOf(Opcode()), k21h);
167  return Fetch16(1);
168}
169
170inline int16_t Instruction::VRegB_21s() const {
171  DCHECK_EQ(FormatOf(Opcode()), k21s);
172  return static_cast<int16_t>(Fetch16(1));
173}
174
175inline int16_t Instruction::VRegB_21t() const {
176  DCHECK_EQ(FormatOf(Opcode()), k21t);
177  return static_cast<int16_t>(Fetch16(1));
178}
179
180inline uint8_t Instruction::VRegB_22b() const {
181  DCHECK_EQ(FormatOf(Opcode()), k22b);
182  return static_cast<uint8_t>(Fetch16(1) & 0xff);
183}
184
185inline uint4_t Instruction::VRegB_22c() const {
186  DCHECK_EQ(FormatOf(Opcode()), k22c);
187  return InstB();
188}
189
190inline uint4_t Instruction::VRegB_22s() const {
191  DCHECK_EQ(FormatOf(Opcode()), k22s);
192  return InstB();
193}
194
195inline uint4_t Instruction::VRegB_22t() const {
196  DCHECK_EQ(FormatOf(Opcode()), k22t);
197  return InstB();
198}
199
200inline uint16_t Instruction::VRegB_22x() const {
201  DCHECK_EQ(FormatOf(Opcode()), k22x);
202  return Fetch16(1);
203}
204
205inline uint8_t Instruction::VRegB_23x() const {
206  DCHECK_EQ(FormatOf(Opcode()), k23x);
207  return static_cast<uint8_t>(Fetch16(1) & 0xff);
208}
209
210inline uint32_t Instruction::VRegB_31c() const {
211  DCHECK_EQ(FormatOf(Opcode()), k31c);
212  return Fetch32(1);
213}
214
215inline int32_t Instruction::VRegB_31i() const {
216  DCHECK_EQ(FormatOf(Opcode()), k31i);
217  return static_cast<int32_t>(Fetch32(1));
218}
219
220inline int32_t Instruction::VRegB_31t() const {
221  DCHECK_EQ(FormatOf(Opcode()), k31t);
222  return static_cast<int32_t>(Fetch32(1));
223}
224
225inline uint16_t Instruction::VRegB_32x() const {
226  DCHECK_EQ(FormatOf(Opcode()), k32x);
227  return Fetch16(2);
228}
229
230inline uint16_t Instruction::VRegB_35c() const {
231  DCHECK_EQ(FormatOf(Opcode()), k35c);
232  return Fetch16(1);
233}
234
235inline uint16_t Instruction::VRegB_3rc() const {
236  DCHECK_EQ(FormatOf(Opcode()), k3rc);
237  return Fetch16(1);
238}
239
240inline uint64_t Instruction::VRegB_51l() const {
241  DCHECK_EQ(FormatOf(Opcode()), k51l);
242  uint64_t vB_wide = Fetch32(1) | ((uint64_t) Fetch32(3) << 32);
243  return vB_wide;
244}
245
246//------------------------------------------------------------------------------
247// VRegC
248//------------------------------------------------------------------------------
249inline int8_t Instruction::VRegC_22b() const {
250  DCHECK_EQ(FormatOf(Opcode()), k22b);
251  return static_cast<int8_t>(Fetch16(1) >> 8);
252}
253
254inline uint16_t Instruction::VRegC_22c() const {
255  DCHECK_EQ(FormatOf(Opcode()), k22c);
256  return Fetch16(1);
257}
258
259inline int16_t Instruction::VRegC_22s() const {
260  DCHECK_EQ(FormatOf(Opcode()), k22s);
261  return static_cast<int16_t>(Fetch16(1));
262}
263
264inline int16_t Instruction::VRegC_22t() const {
265  DCHECK_EQ(FormatOf(Opcode()), k22t);
266  return static_cast<int16_t>(Fetch16(1));
267}
268
269inline uint8_t Instruction::VRegC_23x() const {
270  DCHECK_EQ(FormatOf(Opcode()), k23x);
271  return static_cast<uint8_t>(Fetch16(1) >> 8);
272}
273
274inline uint4_t Instruction::VRegC_35c() const {
275  DCHECK_EQ(FormatOf(Opcode()), k35c);
276  return static_cast<uint4_t>(Fetch16(2) & 0x0f);
277}
278
279inline uint16_t Instruction::VRegC_3rc() const {
280  DCHECK_EQ(FormatOf(Opcode()), k3rc);
281  return Fetch16(2);
282}
283
284inline void Instruction::GetArgs(uint32_t arg[5]) const {
285  DCHECK_EQ(FormatOf(Opcode()), k35c);
286
287  /*
288   * Note that the fields mentioned in the spec don't appear in
289   * their "usual" positions here compared to most formats. This
290   * was done so that the field names for the argument count and
291   * reference index match between this format and the corresponding
292   * range formats (3rc and friends).
293   *
294   * Bottom line: The argument count is always in vA, and the
295   * method constant (or equivalent) is always in vB.
296   */
297  uint16_t regList = Fetch16(2);
298  uint4_t count = InstB();  // This is labeled A in the spec.
299
300  /*
301   * Copy the argument registers into the arg[] array, and
302   * also copy the first argument (if any) into vC. (The
303   * DecodedInstruction structure doesn't have separate
304   * fields for {vD, vE, vF, vG}, so there's no need to make
305   * copies of those.) Note that cases 5..2 fall through.
306   */
307  switch (count) {
308    case 5: arg[4] = InstA();
309    case 4: arg[3] = (regList >> 12) & 0x0f;
310    case 3: arg[2] = (regList >> 8) & 0x0f;
311    case 2: arg[1] = (regList >> 4) & 0x0f;
312    case 1: arg[0] = regList & 0x0f; break;
313    case 0: break;  // Valid, but no need to do anything.
314    default:
315      LOG(ERROR) << "Invalid arg count in 35c (" << count << ")";
316      return;
317  }
318}
319
320}  // namespace art
321
322#endif  // ART_RUNTIME_DEX_INSTRUCTION_INL_H_
323