simd_codegen.cpp revision 0e2c34f92f00628d48968dfea096d36381f494cb
1// RUN: %clang_cc1 -verify -fopenmp=libiomp5 -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s 2// RUN: %clang_cc1 -fopenmp=libiomp5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 3// RUN: %clang_cc1 -fopenmp=libiomp5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -g -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s 4// 5// expected-no-diagnostics 6#ifndef HEADER 7#define HEADER 8 9// CHECK-LABEL: define {{.*void}} @{{.*}}simple{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) 10void simple(float *a, float *b, float *c, float *d) { 11 #pragma omp simd 12// CHECK: store i32 0, i32* [[OMP_IV:%[^,]+]] 13 14// CHECK: [[IV:%.+]] = load i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID:[0-9]+]] 15// CHECK-NEXT: [[CMP:%.+]] = icmp slt i32 [[IV]], 6 16// CHECK-NEXT: br i1 [[CMP]], label %[[SIMPLE_LOOP1_BODY:.+]], label %[[SIMPLE_LOOP1_END:[^,]+]] 17 for (int i = 3; i < 32; i += 5) { 18// CHECK: [[SIMPLE_LOOP1_BODY]] 19// Start of body: calculate i from IV: 20// CHECK: [[IV1_1:%.+]] = load i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 21// CHECK: [[CALC_I_1:%.+]] = mul nsw i32 [[IV1_1]], 5 22// CHECK-NEXT: [[CALC_I_2:%.+]] = add nsw i32 3, [[CALC_I_1]] 23// CHECK-NEXT: store i32 [[CALC_I_2]], i32* [[LC_I:.+]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 24// ... loop body ... 25// End of body: store into a[i]: 26// CHECK: store float [[RESULT:%.+]], float* {{%.+}}{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 27 a[i] = b[i] * c[i] * d[i]; 28// CHECK: [[IV1_2:%.+]] = load i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 29// CHECK-NEXT: [[ADD1_2:%.+]] = add nsw i32 [[IV1_2]], 1 30// CHECK-NEXT: store i32 [[ADD1_2]], i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 31// br label %{{.+}}, !llvm.loop !{{.+}} 32 } 33// CHECK: [[SIMPLE_LOOP1_END]] 34 35 #pragma omp simd 36// CHECK: store i32 0, i32* [[OMP_IV2:%[^,]+]] 37 38// CHECK: [[IV2:%.+]] = load i32* [[OMP_IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID:[0-9]+]] 39// CHECK-NEXT: [[CMP2:%.+]] = icmp slt i32 [[IV2]], 9 40// CHECK-NEXT: br i1 [[CMP2]], label %[[SIMPLE_LOOP2_BODY:.+]], label %[[SIMPLE_LOOP2_END:[^,]+]] 41 for (int i = 10; i > 1; i--) { 42// CHECK: [[SIMPLE_LOOP2_BODY]] 43// Start of body: calculate i from IV: 44// CHECK: [[IV2_0:%.+]] = load i32* [[OMP_IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 45// FIXME: It is interesting, why the following "mul 1" was not constant folded? 46// CHECK-NEXT: [[IV2_1:%.+]] = mul nsw i32 [[IV2_0]], 1 47// CHECK-NEXT: [[LC_I_1:%.+]] = sub nsw i32 10, [[IV2_1]] 48// CHECK-NEXT: store i32 [[LC_I_1]], i32* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 49 a[i]++; 50// CHECK: [[IV2_2:%.+]] = load i32* [[OMP_IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 51// CHECK-NEXT: [[ADD2_2:%.+]] = add nsw i32 [[IV2_2]], 1 52// CHECK-NEXT: store i32 [[ADD2_2]], i32* [[OMP_IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 53// br label {{.+}}, !llvm.loop ![[SIMPLE_LOOP2_ID]] 54 } 55// CHECK: [[SIMPLE_LOOP2_END]] 56 57 #pragma omp simd 58// CHECK: store i64 0, i64* [[OMP_IV3:%[^,]+]] 59 60// CHECK: [[IV3:%.+]] = load i64* [[OMP_IV3]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID:[0-9]+]] 61// CHECK-NEXT: [[CMP3:%.+]] = icmp ult i64 [[IV3]], 4 62// CHECK-NEXT: br i1 [[CMP3]], label %[[SIMPLE_LOOP3_BODY:.+]], label %[[SIMPLE_LOOP3_END:[^,]+]] 63 for (unsigned long long it = 2000; it >= 600; it-=400) { 64// CHECK: [[SIMPLE_LOOP3_BODY]] 65// Start of body: calculate it from IV: 66// CHECK: [[IV3_0:%.+]] = load i64* [[OMP_IV3]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 67// CHECK-NEXT: [[LC_IT_1:%.+]] = mul i64 [[IV3_0]], 400 68// CHECK-NEXT: [[LC_IT_2:%.+]] = sub i64 2000, [[LC_IT_1]] 69// CHECK-NEXT: store i64 [[LC_IT_2]], i64* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 70 a[it]++; 71// CHECK: [[IV3_2:%.+]] = load i64* [[OMP_IV3]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 72// CHECK-NEXT: [[ADD3_2:%.+]] = add i64 [[IV3_2]], 1 73// CHECK-NEXT: store i64 [[ADD3_2]], i64* [[OMP_IV3]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 74 } 75// CHECK: [[SIMPLE_LOOP3_END]] 76 77 #pragma omp simd 78// CHECK: store i32 0, i32* [[OMP_IV4:%[^,]+]] 79 80// CHECK: [[IV4:%.+]] = load i32* [[OMP_IV4]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID:[0-9]+]] 81// CHECK-NEXT: [[CMP4:%.+]] = icmp slt i32 [[IV4]], 4 82// CHECK-NEXT: br i1 [[CMP4]], label %[[SIMPLE_LOOP4_BODY:.+]], label %[[SIMPLE_LOOP4_END:[^,]+]] 83 for (short it = 6; it <= 20; it-=-4) { 84// CHECK: [[SIMPLE_LOOP4_BODY]] 85// Start of body: calculate it from IV: 86// CHECK: [[IV4_0:%.+]] = load i32* [[OMP_IV4]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID]] 87// CHECK-NEXT: [[LC_IT_1:%.+]] = mul nsw i32 [[IV4_0]], 4 88// CHECK-NEXT: [[LC_IT_2:%.+]] = add nsw i32 6, [[LC_IT_1]] 89// CHECK-NEXT: [[LC_IT_3:%.+]] = trunc i32 [[LC_IT_2]] to i16 90// CHECK-NEXT: store i16 [[LC_IT_3]], i16* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID]] 91 92// CHECK: [[IV4_2:%.+]] = load i32* [[OMP_IV4]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID]] 93// CHECK-NEXT: [[ADD4_2:%.+]] = add nsw i32 [[IV4_2]], 1 94// CHECK-NEXT: store i32 [[ADD4_2]], i32* [[OMP_IV4]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID]] 95 } 96// CHECK: [[SIMPLE_LOOP4_END]] 97 98 #pragma omp simd 99// CHECK: store i32 0, i32* [[OMP_IV5:%[^,]+]] 100 101// CHECK: [[IV5:%.+]] = load i32* [[OMP_IV5]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID:[0-9]+]] 102// CHECK-NEXT: [[CMP5:%.+]] = icmp slt i32 [[IV5]], 26 103// CHECK-NEXT: br i1 [[CMP5]], label %[[SIMPLE_LOOP5_BODY:.+]], label %[[SIMPLE_LOOP5_END:[^,]+]] 104 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 105// CHECK: [[SIMPLE_LOOP5_BODY]] 106// Start of body: calculate it from IV: 107// CHECK: [[IV5_0:%.+]] = load i32* [[OMP_IV5]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID]] 108// CHECK-NEXT: [[IV5_1:%.+]] = mul nsw i32 [[IV5_0]], 1 109// CHECK-NEXT: [[LC_IT_1:%.+]] = sub nsw i32 122, [[IV5_1]] 110// CHECK-NEXT: [[LC_IT_2:%.+]] = trunc i32 [[LC_IT_1]] to i8 111// CHECK-NEXT: store i8 [[LC_IT_2]], i8* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID]] 112 113// CHECK: [[IV5_2:%.+]] = load i32* [[OMP_IV5]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID]] 114// CHECK-NEXT: [[ADD5_2:%.+]] = add nsw i32 [[IV5_2]], 1 115// CHECK-NEXT: store i32 [[ADD5_2]], i32* [[OMP_IV5]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID]] 116 } 117// CHECK: [[SIMPLE_LOOP5_END]] 118 119 #pragma omp simd 120// FIXME: I think we would get wrong result using 'unsigned' in the loop below. 121// So we'll need to add zero trip test for 'unsigned' counters. 122// 123// CHECK: store i32 0, i32* [[OMP_IV6:%[^,]+]] 124 125// CHECK: [[IV6:%.+]] = load i32* [[OMP_IV6]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP6_ID:[0-9]+]] 126// CHECK-NEXT: [[CMP6:%.+]] = icmp slt i32 [[IV6]], -8 127// CHECK-NEXT: br i1 [[CMP6]], label %[[SIMPLE_LOOP6_BODY:.+]], label %[[SIMPLE_LOOP6_END:[^,]+]] 128 for (int i=100; i<10; i+=10) { 129// CHECK: [[SIMPLE_LOOP6_BODY]] 130// Start of body: calculate i from IV: 131// CHECK: [[IV6_0:%.+]] = load i32* [[OMP_IV6]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP6_ID]] 132// CHECK-NEXT: [[LC_IT_1:%.+]] = mul nsw i32 [[IV6_0]], 10 133// CHECK-NEXT: [[LC_IT_2:%.+]] = add nsw i32 100, [[LC_IT_1]] 134// CHECK-NEXT: store i32 [[LC_IT_2]], i32* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP6_ID]] 135 136// CHECK: [[IV6_2:%.+]] = load i32* [[OMP_IV6]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP6_ID]] 137// CHECK-NEXT: [[ADD6_2:%.+]] = add nsw i32 [[IV6_2]], 1 138// CHECK-NEXT: store i32 [[ADD6_2]], i32* [[OMP_IV6]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP6_ID]] 139 } 140// CHECK: [[SIMPLE_LOOP6_END]] 141 142 int A; 143 #pragma omp simd lastprivate(A) 144// Clause 'lastprivate' implementation is not completed yet. 145// Test checks that one iteration is separated in presence of lastprivate. 146// 147// CHECK: store i64 0, i64* [[OMP_IV7:%[^,]+]] 148// CHECK: br i1 true, label %[[SIMPLE_IF7_THEN:.+]], label %[[SIMPLE_IF7_END:[^,]+]] 149// CHECK: [[SIMPLE_IF7_THEN]] 150// CHECK: br label %[[SIMD_LOOP7_COND:[^,]+]] 151// CHECK: [[SIMD_LOOP7_COND]] 152// CHECK-NEXT: [[IV7:%.+]] = load i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID:[0-9]+]] 153// CHECK-NEXT: [[CMP7:%.+]] = icmp slt i64 [[IV7]], 6 154// CHECK-NEXT: br i1 [[CMP7]], label %[[SIMPLE_LOOP7_BODY:.+]], label %[[SIMPLE_LOOP7_END:[^,]+]] 155 for (long long i = -10; i < 10; i += 3) { 156// CHECK: [[SIMPLE_LOOP7_BODY]] 157// Start of body: calculate i from IV: 158// CHECK: [[IV7_0:%.+]] = load i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 159// CHECK-NEXT: [[LC_IT_1:%.+]] = mul nsw i64 [[IV7_0]], 3 160// CHECK-NEXT: [[LC_IT_2:%.+]] = add nsw i64 -10, [[LC_IT_1]] 161// CHECK-NEXT: store i64 [[LC_IT_2]], i64* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 162 A = i; 163// CHECK: [[IV7_2:%.+]] = load i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 164// CHECK-NEXT: [[ADD7_2:%.+]] = add nsw i64 [[IV7_2]], 1 165// CHECK-NEXT: store i64 [[ADD7_2]], i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 166 } 167// CHECK: [[SIMPLE_LOOP7_END]] 168// Separated last iteration. 169// CHECK: [[IV7_4:%.+]] = load i64* [[OMP_IV7]] 170// CHECK-NEXT: [[LC_FIN_1:%.+]] = mul nsw i64 [[IV7_4]], 3 171// CHECK-NEXT: [[LC_FIN_2:%.+]] = add nsw i64 -10, [[LC_FIN_1]] 172// CHECK-NEXT: store i64 [[LC_FIN_2]], i64* [[ADDR_I:%[^,]+]] 173// CHECK: [[LOAD_I:%.+]] = load i64* [[ADDR_I]] 174// CHECK-NEXT: [[CONV_I:%.+]] = trunc i64 [[LOAD_I]] to i32 175// 176// CHECK: br label %[[SIMPLE_IF7_END]] 177// CHECK: [[SIMPLE_IF7_END]] 178// 179 180// CHECK: ret void 181} 182 183template <class T, unsigned K> T tfoo(T a) { return a + K; } 184 185template <typename T, unsigned N> 186int templ1(T a, T *z) { 187 #pragma omp simd collapse(N) 188 for (int i = 0; i < N * 2; i++) { 189 for (long long j = 0; j < (N + N + N + N); j += 2) { 190 z[i + j] = a + tfoo<T, N>(i + j); 191 } 192 } 193 return 0; 194} 195 196// Instatiation templ1<float,2> 197// CHECK-LABEL: define {{.*i32}} @{{.*}}templ1{{.*}}(float {{.+}}, float* {{.+}}) 198// CHECK: store i64 0, i64* [[T1_OMP_IV:[^,]+]] 199// ... 200// CHECK: [[IV:%.+]] = load i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID:[0-9]+]] 201// CHECK-NEXT: [[CMP1:%.+]] = icmp slt i64 [[IV]], 16 202// CHECK-NEXT: br i1 [[CMP1]], label %[[T1_BODY:.+]], label %[[T1_END:[^,]+]] 203// CHECK: [[T1_BODY]] 204// Loop counters i and j updates: 205// CHECK: [[IV1:%.+]] = load i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 206// CHECK-NEXT: [[I_1:%.+]] = sdiv i64 [[IV1]], 4 207// CHECK-NEXT: [[I_1_MUL1:%.+]] = mul nsw i64 [[I_1]], 1 208// CHECK-NEXT: [[I_1_ADD0:%.+]] = add nsw i64 0, [[I_1_MUL1]] 209// CHECK-NEXT: [[I_2:%.+]] = trunc i64 [[I_1_ADD0]] to i32 210// CHECK-NEXT: store i32 [[I_2]], i32* {{%.+}}{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 211// CHECK: [[IV2:%.+]] = load i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 212// CHECK-NEXT: [[J_1:%.+]] = srem i64 [[IV2]], 4 213// CHECK-NEXT: [[J_2:%.+]] = mul nsw i64 [[J_1]], 2 214// CHECK-NEXT: [[J_2_ADD0:%.+]] = add nsw i64 0, [[J_2]] 215// CHECK-NEXT: store i64 [[J_2_ADD0]], i64* {{%.+}}{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 216// simd.for.inc: 217// CHECK: [[IV3:%.+]] = load i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 218// CHECK-NEXT: [[INC:%.+]] = add nsw i64 [[IV3]], 1 219// CHECK-NEXT: store i64 [[INC]], i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 220// CHECK-NEXT: br label {{%.+}} 221// CHECK: [[T1_END]] 222// CHECK: ret i32 0 223// 224void inst_templ1() { 225 float a; 226 float z[100]; 227 templ1<float,2> (a, z); 228} 229 230 231typedef int MyIdx; 232 233class IterDouble { 234 double *Ptr; 235public: 236 IterDouble operator++ () const { 237 IterDouble n; 238 n.Ptr = Ptr + 1; 239 return n; 240 } 241 bool operator < (const IterDouble &that) const { 242 return Ptr < that.Ptr; 243 } 244 double & operator *() const { 245 return *Ptr; 246 } 247 MyIdx operator - (const IterDouble &that) const { 248 return (MyIdx) (Ptr - that.Ptr); 249 } 250 IterDouble operator + (int Delta) { 251 IterDouble re; 252 re.Ptr = Ptr + Delta; 253 return re; 254 } 255 256 ///~IterDouble() {} 257}; 258 259// CHECK-LABEL: define {{.*void}} @{{.*}}iter_simple{{.*}} 260void iter_simple(IterDouble ia, IterDouble ib, IterDouble ic) { 261// 262// CHECK: store i32 0, i32* [[IT_OMP_IV:%[^,]+]] 263// Calculate number of iterations before the loop body. 264// CHECK: [[DIFF1:%.+]] = call {{.*}}i32 @{{.*}}IterDouble{{.*}} 265// CHECK-NEXT: [[DIFF2:%.+]] = sub nsw i32 [[DIFF1]], 1 266// CHECK-NEXT: [[DIFF3:%.+]] = add nsw i32 [[DIFF2]], 1 267// CHECK-NEXT: [[DIFF4:%.+]] = sdiv i32 [[DIFF3]], 1 268// CHECK-NEXT: [[DIFF5:%.+]] = sub nsw i32 [[DIFF4]], 1 269// CHECK-NEXT: store i32 [[DIFF5]], i32* [[OMP_LAST_IT:%[^,]+]]{{.+}} 270 #pragma omp simd 271 272// CHECK: [[IV:%.+]] = load i32* [[IT_OMP_IV]]{{.+}} !llvm.mem.parallel_loop_access ![[ITER_LOOP_ID:[0-9]+]] 273// CHECK-NEXT: [[LAST_IT:%.+]] = load i32* [[OMP_LAST_IT]]{{.+}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 274// CHECK-NEXT: [[NUM_IT:%.+]] = add nsw i32 [[LAST_IT]], 1 275// CHECK-NEXT: [[CMP:%.+]] = icmp slt i32 [[IV]], [[NUM_IT]] 276// CHECK-NEXT: br i1 [[CMP]], label %[[IT_BODY:[^,]+]], label %[[IT_END:[^,]+]] 277 for (IterDouble i = ia; i < ib; ++i) { 278// CHECK: [[IT_BODY]] 279// Start of body: calculate i from index: 280// CHECK: [[IV1:%.+]] = load i32* [[IT_OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 281// Call of operator+ (i, IV). 282// CHECK: {{%.+}} = call {{.+}} @{{.*}}IterDouble{{.*}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 283// ... loop body ... 284 *i = *ic * 0.5; 285// Float multiply and save result. 286// CHECK: [[MULR:%.+]] = fmul double {{%.+}}, 5.000000e-01 287// CHECK-NEXT: call {{.+}} @{{.*}}IterDouble{{.*}} 288// CHECK: store double [[MULR:%.+]], double* [[RESULT_ADDR:%.+]], !llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 289 ++ic; 290// 291// CHECK: [[IV2:%.+]] = load i32* [[IT_OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 292// CHECK-NEXT: [[ADD2:%.+]] = add nsw i32 [[IV2]], 1 293// CHECK-NEXT: store i32 [[ADD2]], i32* [[IT_OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 294// br label %{{.*}}, !llvm.loop ![[ITER_LOOP_ID]] 295 } 296// CHECK: [[IT_END]] 297// CHECK: ret void 298} 299 300 301// CHECK-LABEL: define {{.*void}} @{{.*}}collapsed{{.*}} 302void collapsed(float *a, float *b, float *c, float *d) { 303 int i; // outer loop counter 304 unsigned j; // middle loop couter, leads to unsigned icmp in loop header. 305 // k declared in the loop init below 306 short l; // inner loop counter 307// CHECK: store i32 0, i32* [[OMP_IV:[^,]+]] 308// 309 #pragma omp simd collapse(4) 310 311// CHECK: [[IV:%.+]] = load i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID:[0-9]+]] 312// CHECK-NEXT: [[CMP:%.+]] = icmp ult i32 [[IV]], 120 313// CHECK-NEXT: br i1 [[CMP]], label %[[COLL1_BODY:[^,]+]], label %[[COLL1_END:[^,]+]] 314 for (i = 1; i < 3; i++) // 2 iterations 315 for (j = 2u; j < 5u; j++) //3 iterations 316 for (int k = 3; k <= 6; k++) // 4 iterations 317 for (l = 4; l < 9; ++l) // 5 iterations 318 { 319// CHECK: [[COLL1_BODY]] 320// Start of body: calculate i from index: 321// CHECK: [[IV1:%.+]] = load i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 322// Calculation of the loop counters values. 323// CHECK: [[CALC_I_1:%.+]] = udiv i32 [[IV1]], 60 324// CHECK-NEXT: [[CALC_I_1_MUL1:%.+]] = mul i32 [[CALC_I_1]], 1 325// CHECK-NEXT: [[CALC_I_2:%.+]] = add i32 1, [[CALC_I_1_MUL1]] 326// CHECK-NEXT: store i32 [[CALC_I_2]], i32* [[LC_I:.+]] 327// CHECK: [[IV1_2:%.+]] = load i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 328// CHECK-NEXT: [[CALC_J_1:%.+]] = udiv i32 [[IV1_2]], 20 329// CHECK-NEXT: [[CALC_J_2:%.+]] = urem i32 [[CALC_J_1]], 3 330// CHECK-NEXT: [[CALC_J_2_MUL1:%.+]] = mul i32 [[CALC_J_2]], 1 331// CHECK-NEXT: [[CALC_J_3:%.+]] = add i32 2, [[CALC_J_2_MUL1]] 332// CHECK-NEXT: store i32 [[CALC_J_3]], i32* [[LC_J:.+]] 333// CHECK: [[IV1_3:%.+]] = load i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 334// CHECK-NEXT: [[CALC_K_1:%.+]] = udiv i32 [[IV1_3]], 5 335// CHECK-NEXT: [[CALC_K_2:%.+]] = urem i32 [[CALC_K_1]], 4 336// CHECK-NEXT: [[CALC_K_2_MUL1:%.+]] = mul i32 [[CALC_K_2]], 1 337// CHECK-NEXT: [[CALC_K_3:%.+]] = add i32 3, [[CALC_K_2_MUL1]] 338// CHECK-NEXT: store i32 [[CALC_K_3]], i32* [[LC_K:.+]] 339// CHECK: [[IV1_4:%.+]] = load i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 340// CHECK-NEXT: [[CALC_L_1:%.+]] = urem i32 [[IV1_4]], 5 341// CHECK-NEXT: [[CALC_L_1_MUL1:%.+]] = mul i32 [[CALC_L_1]], 1 342// CHECK-NEXT: [[CALC_L_2:%.+]] = add i32 4, [[CALC_L_1_MUL1]] 343// CHECK-NEXT: [[CALC_L_3:%.+]] = trunc i32 [[CALC_L_2]] to i16 344// CHECK-NEXT: store i16 [[CALC_L_3]], i16* [[LC_L:.+]] 345// ... loop body ... 346// End of body: store into a[i]: 347// CHECK: store float [[RESULT:%.+]], float* [[RESULT_ADDR:%.+]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 348 float res = b[j] * c[k]; 349 a[i] = res * d[l]; 350// CHECK: [[IV2:%.+]] = load i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 351// CHECK-NEXT: [[ADD2:%.+]] = add i32 [[IV2]], 1 352// CHECK-NEXT: store i32 [[ADD2]], i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 353// br label %{{[^,]+}}, !llvm.loop ![[COLL1_LOOP_ID]] 354// CHECK: [[COLL1_END]] 355 } 356// i,j,l are updated; k is not updated. 357// CHECK: store i32 3, i32* [[I:%[^,]+]] 358// CHECK-NEXT: store i32 5, i32* [[I:%[^,]+]] 359// CHECK-NEXT: store i16 9, i16* [[I:%[^,]+]] 360// CHECK: ret void 361} 362 363extern char foo(); 364 365// CHECK-LABEL: define {{.*void}} @{{.*}}widened{{.*}} 366void widened(float *a, float *b, float *c, float *d) { 367 int i; // outer loop counter 368 short j; // inner loop counter 369// Counter is widened to 64 bits. 370// CHECK: store i64 0, i64* [[OMP_IV:[^,]+]] 371// 372 #pragma omp simd collapse(2) 373 374// CHECK: [[IV:%.+]] = load i64* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID:[0-9]+]] 375// CHECK-NEXT: [[LI:%.+]] = load i64* [[OMP_LI:%[^,]+]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 376// CHECK-NEXT: [[NUMIT:%.+]] = add nsw i64 [[LI]], 1 377// CHECK-NEXT: [[CMP:%.+]] = icmp slt i64 [[IV]], [[NUMIT]] 378// CHECK-NEXT: br i1 [[CMP]], label %[[WIDE1_BODY:[^,]+]], label %[[WIDE1_END:[^,]+]] 379 for (i = 1; i < 3; i++) // 2 iterations 380 for (j = 0; j < foo(); j++) // foo() iterations 381 { 382// CHECK: [[WIDE1_BODY]] 383// Start of body: calculate i from index: 384// CHECK: [[IV1:%.+]] = load i64* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 385// Calculation of the loop counters values... 386// CHECK: store i32 {{[^,]+}}, i32* [[LC_I:.+]] 387// CHECK: [[IV1_2:%.+]] = load i64* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 388// CHECK: store i16 {{[^,]+}}, i16* [[LC_J:.+]] 389// ... loop body ... 390// End of body: store into a[i]: 391// CHECK: store float [[RESULT:%.+]], float* [[RESULT_ADDR:%.+]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 392 float res = b[j] * c[j]; 393 a[i] = res * d[i]; 394// CHECK: [[IV2:%.+]] = load i64* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 395// CHECK-NEXT: [[ADD2:%.+]] = add nsw i64 [[IV2]], 1 396// CHECK-NEXT: store i64 [[ADD2]], i64* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 397// br label %{{[^,]+}}, !llvm.loop ![[WIDE1_LOOP_ID]] 398// CHECK: [[WIDE1_END]] 399 } 400// i,j are updated. 401// CHECK: store i32 3, i32* [[I:%[^,]+]] 402// CHECK: store i16 403// CHECK: ret void 404} 405 406void parallel_simd(float *a) { 407#pragma omp parallel 408#pragma omp simd 409 // CHECK-NOT: __kmpc_global_thread_num 410 for (unsigned i = 131071; i <= 2147483647; i += 127) 411 a[i] += i; 412} 413 414#endif // HEADER 415 416