130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- 230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com 330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * All rights reserved. 830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Permission is hereby granted, free of charge, to any person obtaining a 1030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * copy of this software and associated documentation files (the "Software"), 1130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * to deal in the Software without restriction, including without limitation 1230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * and/or sell copies of the Software, and to permit persons to whom the 1430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Software is furnished to do so, subject to the following conditions: 1530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 1630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * The above copyright notice and this permission notice (including the next 1730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * paragraph) shall be included in all copies or substantial portions of the 1830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Software. 1930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 2030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * DEALINGS IN THE SOFTWARE. 2730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 2830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Authors: 2930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Gareth Hughes <gareth@valinux.com> 3030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Kevin E. Martin <martin@valinux.com> 3130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 3230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 3330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#ifndef __R128_DRM_H__ 3430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define __R128_DRM_H__ 3530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 3630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* WARNING: If you change any of these defines, make sure to change the 3730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * defines in the X server file (r128_sarea.h) 3830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 3930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#ifndef __R128_SAREA_DEFINES__ 4030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define __R128_SAREA_DEFINES__ 4130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 4230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* What needs to be changed for the current vertex buffer? 4330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 4430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_CONTEXT 0x001 4530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_SETUP 0x002 4630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_TEX0 0x004 4730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_TEX1 0x008 4830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_TEX0IMAGES 0x010 4930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_TEX1IMAGES 0x020 5030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_CORE 0x040 5130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_MASKS 0x080 5230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_WINDOW 0x100 5330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ 5430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_REQUIRE_QUIESCENCE 0x400 5530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_UPLOAD_ALL 0x7ff 5630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 5730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_FRONT 0x1 5830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_BACK 0x2 5930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_DEPTH 0x4 6030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 6130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Primitive types 6230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 6330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_POINTS 0x1 6430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_LINES 0x2 6530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_LINE_STRIP 0x3 6630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_TRIANGLES 0x4 6730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_TRIANGLE_FAN 0x5 6830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_TRIANGLE_STRIP 0x6 6930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 7030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Vertex/indirect buffer size 7130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 7230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_BUFFER_SIZE 16384 7330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 7430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Byte offsets for indirect buffer data 7530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 7630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_INDEX_PRIM_OFFSET 20 7730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_HOSTDATA_BLIT_OFFSET 32 7830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 7930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Keep these small for testing. 8030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 8130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_NR_SAREA_CLIPRECTS 12 8230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 8330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* There are 2 heaps (local/AGP). Each region within a heap is a 8430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * minimum of 64k, and there are at most 64 of them per heap. 8530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 8630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_LOCAL_TEX_HEAP 0 8730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_AGP_TEX_HEAP 1 8830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_NR_TEX_HEAPS 2 8930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_NR_TEX_REGIONS 64 9030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_LOG_TEX_GRANULARITY 16 9130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 9230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_NR_CONTEXT_REGS 12 9330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 9430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_MAX_TEXTURE_LEVELS 11 9530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_MAX_TEXTURE_UNITS 2 9630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 9730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#endif /* __R128_SAREA_DEFINES__ */ 9830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 9930692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct { 10030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Context state - can be written in one large chunk */ 10130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int dst_pitch_offset_c; 10230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int dp_gui_master_cntl_c; 10330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int sc_top_left_c; 10430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int sc_bottom_right_c; 10530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int z_offset_c; 10630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int z_pitch_c; 10730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int z_sten_cntl_c; 10830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int tex_cntl_c; 10930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int misc_3d_state_cntl_reg; 11030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int texture_clr_cmp_clr_c; 11130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int texture_clr_cmp_msk_c; 11230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int fog_color_c; 11330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 11430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Texture state */ 11530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int tex_size_pitch_c; 11630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int constant_color_c; 11730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 11830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Setup state */ 11930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int pm4_vc_fpu_setup; 12030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int setup_cntl; 12130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 12230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Mask state */ 12330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int dp_write_mask; 12430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int sten_ref_mask_c; 12530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int plane_3d_mask_c; 12630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 12730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Window state */ 12830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int window_xy_offset; 12930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 13030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Core state */ 13130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int scale_3d_cntl; 13230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_context_regs_t; 13330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 13430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Setup registers for each texture unit 13530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 13630692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct { 13730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int tex_cntl; 13830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int tex_combine_cntl; 13930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int tex_size_pitch; 14030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; 14130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int tex_border_color; 14230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_texture_regs_t; 14330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 14430692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_sarea { 14530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* The channel for communication of state information to the kernel 14630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * on firing a vertex buffer. 14730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 14830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng drm_r128_context_regs_t context_state; 14930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; 15030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int dirty; 15130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int vertsize; 15230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int vc_format; 15330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 15430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* The current cliprects, or a subset thereof. 15530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 15630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; 15730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int nbox; 15830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 15930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Counters for client-side throttling of rendering clients. 16030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 16130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int last_frame; 16230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int last_dispatch; 16330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 16430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; 16530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int tex_age[R128_NR_TEX_HEAPS]; 16630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int ctx_owner; 16730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ 16830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int pfCurrentPage; /* which buffer is being displayed? */ 16930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_sarea_t; 17030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 17130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* WARNING: If you change any of these defines, make sure to change the 17230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * defines in the Xserver file (xf86drmR128.h) 17330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 17430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 17530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Rage 128 specific ioctls 17630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * The device specific ioctl range is 0x40 to 0x79. 17730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 17830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_INIT 0x00 17930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_CCE_START 0x01 18030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_CCE_STOP 0x02 18130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_CCE_RESET 0x03 18230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_CCE_IDLE 0x04 18330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 0x05 not used */ 18430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_RESET 0x06 18530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_SWAP 0x07 18630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_CLEAR 0x08 18730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_VERTEX 0x09 18830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_INDICES 0x0a 18930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_BLIT 0x0b 19030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_DEPTH 0x0c 19130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_STIPPLE 0x0d 19230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 0x0e not used */ 19330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_INDIRECT 0x0f 19430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_FULLSCREEN 0x10 19530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_CLEAR2 0x11 19630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_GETPARAM 0x12 19730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_R128_FLIP 0x13 19830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 19930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) 20030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) 20130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) 20230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) 20330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) 20430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 0x05 not used */ 20530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) 20630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) 20730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) 20830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) 20930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) 21030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) 21130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) 21230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) 21330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 0x0e not used */ 21430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) 21530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) 21630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) 21730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) 21830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) 21930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 22030692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_init { 22130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng enum { 22230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng R128_INIT_CCE = 0x01, 22330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng R128_CLEANUP_CCE = 0x02 22430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng } func; 22530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long sarea_priv_offset; 22630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int is_pci; 22730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int cce_mode; 22830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int cce_secure; 22930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int ring_size; 23030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int usec_timeout; 23130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 23230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int fb_bpp; 23330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int front_offset, front_pitch; 23430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int back_offset, back_pitch; 23530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int depth_bpp; 23630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int depth_offset, depth_pitch; 23730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int span_offset; 23830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 23930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long fb_offset; 24030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long mmio_offset; 24130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long ring_offset; 24230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long ring_rptr_offset; 24330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long buffers_offset; 24430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long agp_textures_offset; 24530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_init_t; 24630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 24730692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_cce_stop { 24830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int flush; 24930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int idle; 25030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_cce_stop_t; 25130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 25230692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_clear { 25330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int flags; 25430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int clear_color; 25530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int clear_depth; 25630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int color_mask; 25730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int depth_mask; 25830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_clear_t; 25930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 26030692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_vertex { 26130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int prim; 26230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int idx; /* Index of vertex buffer */ 26330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int count; /* Number of vertices in buffer */ 26430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int discard; /* Client finished with buffer? */ 26530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_vertex_t; 26630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 26730692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_indices { 26830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int prim; 26930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int idx; 27030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int start; 27130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int end; 27230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int discard; /* Client finished with buffer? */ 27330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_indices_t; 27430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 27530692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_blit { 27630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int idx; 27730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int pitch; 27830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int offset; 27930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int format; 28030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned short x, y; 28130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned short width, height; 28230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_blit_t; 28330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 28430692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_depth { 28530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng enum { 28630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng R128_WRITE_SPAN = 0x01, 28730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng R128_WRITE_PIXELS = 0x02, 28830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng R128_READ_SPAN = 0x03, 28930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng R128_READ_PIXELS = 0x04 29030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng } func; 29130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int n; 29230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int __user *x; 29330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int __user *y; 29430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int __user *buffer; 29530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char __user *mask; 29630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_depth_t; 29730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 29830692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_stipple { 29930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned int __user *mask; 30030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_stipple_t; 30130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 30230692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_indirect { 30330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int idx; 30430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int start; 30530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int end; 30630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int discard; 30730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_indirect_t; 30830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 30930692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_fullscreen { 31030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng enum { 31130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng R128_INIT_FULLSCREEN = 0x01, 31230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng R128_CLEANUP_FULLSCREEN = 0x02 31330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng } func; 31430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_fullscreen_t; 31530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 31630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 2.3: An ioctl to get parameters that aren't available to the 3d 31730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * client any other way. 31830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 31930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define R128_PARAM_IRQ_NR 1 32030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 32130692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct drm_r128_getparam { 32230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng int param; 32330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng void __user *value; 32430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} drm_r128_getparam_t; 32530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 32630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#endif 327