12b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 22b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * 32b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 42b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 52b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 62b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * All rights reserved. 72b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * 82b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Permission is hereby granted, free of charge, to any person obtaining a 92b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * copy of this software and associated documentation files (the "Software"), 102b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * to deal in the Software without restriction, including without limitation 112b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 122b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * and/or sell copies of the Software, and to permit persons to whom the 132b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Software is furnished to do so, subject to the following conditions: 142b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * 152b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * The above copyright notice and this permission notice (including the next 162b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * paragraph) shall be included in all copies or substantial portions of the 172b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Software. 182b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * 192b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 202b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 212b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 222b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 232b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 242b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 252b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * DEALINGS IN THE SOFTWARE. 262b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * 272b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Authors: 282b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Kevin E. Martin <martin@valinux.com> 292b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Gareth Hughes <gareth@valinux.com> 302b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Keith Whitwell <keith@tungstengraphics.com> 312b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 322b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 332b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#ifndef __RADEON_DRM_H__ 342b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define __RADEON_DRM_H__ 352b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 36170674a606f6d7869b5fa4457c07e10dd27f2771Robert Noland#include "drm.h" 372b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* WARNING: If you change any of these defines, make sure to change the 392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * defines in the X server file (radeon_sarea.h) 402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#ifndef __RADEON_SAREA_DEFINES__ 422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define __RADEON_SAREA_DEFINES__ 432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Old style state flags, required for sarea interface (1.1 and 1.2 452b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * clears) and 1.2 drm_vertex2 ioctl. 462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_CONTEXT 0x00000001 482b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_VERTFMT 0x00000002 492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_LINE 0x00000004 502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_BUMPMAP 0x00000008 512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_MASKS 0x00000010 522b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_VIEWPORT 0x00000020 532b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_SETUP 0x00000040 542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_TCL 0x00000080 552b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_MISC 0x00000100 562b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_TEX0 0x00000200 572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_TEX1 0x00000400 582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_TEX2 0x00000800 592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_REQUIRE_QUIESCENCE 0x00010000 642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_ALL 0x003effff 662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 682b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* New style per-packet identifiers for use in cmd_buffer ioctl with 692b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * the RADEON_EMIT_PACKET command. Comments relate new packets to old 702b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * state bits and the packet size: 712b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 722b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_MISC 0 /* context/7 */ 732b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 742b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 752b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 762b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 772b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 782b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 792b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 802b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 812b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 822b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 832b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 842b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 852b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 862b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 872b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 882b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 892b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 902b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 912b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 922b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 932b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 942b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 952b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 962b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 972b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 982b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 992b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 1002b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 1012b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 1022b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 1032b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 1042b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_VAP_CTL 32 /* vap/1 */ 1052b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 1062b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 1072b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 1082b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 1092b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 1102b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 1112b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 1122b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 1132b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 1142b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 1152b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 1162b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 1172b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 1182b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 1192b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 1202b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 1212b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 1222b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 1232b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 1242b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 1252b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 1262b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 1272b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 1282b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 1292b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 1302b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 1312b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 1322b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 1332b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_FACES_0 61 1342b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 1352b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_FACES_1 63 1362b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 1372b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_FACES_2 65 1382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 1392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_FACES_3 67 1402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 1412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_FACES_4 69 1422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 1432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_FACES_5 71 1442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 1452b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_TEX_SIZE_0 73 1462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_TEX_SIZE_1 74 1472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_TEX_SIZE_2 75 1482b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_RB3D_BLENDCOLOR 76 1492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 1502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_CUBIC_FACES_0 78 1512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 1522b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_CUBIC_FACES_1 80 1532b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 1542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_CUBIC_FACES_2 82 1552b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 1562b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TRI_PERF_CNTL 84 1572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_AFS_0 85 1582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_AFS_1 86 1592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_ATF_TFACTOR 87 1602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCTLALL_0 88 1612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCTLALL_1 89 1622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCTLALL_2 90 1632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCTLALL_3 91 1642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCTLALL_4 92 1652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_PP_TXCTLALL_5 93 1662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R200_EMIT_VAP_PVS_CNTL 94 1672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_MAX_STATE_PACKETS 95 1682b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 1692b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Commands understood by cmd_buffer ioctl. More can be added but 1702b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * obviously these can't be removed or changed: 1712b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 1722b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 1732b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 1742b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CMD_VECTORS 3 /* emit vector data */ 1752b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 1762b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CMD_PACKET3 5 /* emit hw packet */ 1772b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 1782b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 1792b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 1802b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * doesn't make the cpu wait, just 1812b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * the graphics hardware */ 1822b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ 1832b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 1842b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef union { 1852b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int i; 1862b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 1872b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, pad0, pad1, pad2; 1882b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } header; 1892b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 1902b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, packet_id, pad0, pad1; 1912b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } packet; 1922b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 1932b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, offset, stride, count; 1942b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } scalars; 1952b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 1962b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, offset, stride, count; 1972b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } vectors; 1982b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 1992b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, addr_lo, addr_hi, count; 2002b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } veclinear; 2012b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2022b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, buf_idx, pad0, pad1; 2032b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } dma; 2042b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2052b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, flags, pad0, pad1; 2062b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } wait; 2072b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_cmd_header_t; 2082b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2092b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_WAIT_2D 0x1 2102b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_WAIT_3D 0x2 2112b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2122b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Allowed parameters for R300_CMD_PACKET3 2132b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 2142b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_PACKET3_CLEAR 0 2152b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_PACKET3_RAW 1 2162b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2172b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Commands understood by cmd_buffer ioctl for R300. 2182b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * The interface has not been stabilized, so some of these may be removed 2192b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * and eventually reordered before stabilization. 2202b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 2212b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_PACKET0 1 2222b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_VPU 2 /* emit vertex program upload */ 2232b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_PACKET3 3 /* emit a packet3 */ 2242b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 2252b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_CP_DELAY 5 2262b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_DMA_DISCARD 6 2272b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_WAIT 7 2282b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg# define R300_WAIT_2D 0x1 2292b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg# define R300_WAIT_3D 0x2 2302b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* these two defines are DOING IT WRONG - however 2312b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * we have userspace which relies on using these. 2322b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * The wait interface is backwards compat new 2332b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * code should use the NEW_WAIT defines below 2342b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * THESE ARE NOT BIT FIELDS 2352b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 2362b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg# define R300_WAIT_2D_CLEAN 0x3 2372b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg# define R300_WAIT_3D_CLEAN 0x4 2382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg# define R300_NEW_WAIT_2D_3D 0x3 2402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 2412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 2422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 2432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_SCRATCH 8 2452b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R300_CMD_R500FP 9 2462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef union { 2482b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int u; 2492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, pad0, pad1, pad2; 2512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } header; 2522b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2532b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, count, reglo, reghi; 2542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } packet0; 2552b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2562b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, count, adrlo, adrhi; 2572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } vpu; 2582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, packet, pad0, pad1; 2602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } packet3; 2612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, packet; 2632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned short count; /* amount of packet2 to emit */ 2642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } delay; 2652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, buf_idx, pad0, pad1; 2672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } dma; 2682b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2692b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, flags, pad0, pad1; 2702b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } wait; 2712b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2722b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, reg, n_bufs, flags; 2732b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } scratch; 2742b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct { 2752b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned char cmd_type, count, adrlo, adrhi_flags; 2762b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } r500fp; 2772b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_r300_cmd_header_t; 2782b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2792b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_FRONT 0x1 2802b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_BACK 0x2 2812b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_DEPTH 0x4 2822b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_STENCIL 0x8 2832b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CLEAR_FASTZ 0x80000000 2842b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_USE_HIERZ 0x40000000 2852b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_USE_COMP_ZBUF 0x20000000 2862b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2872b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R500FP_CONSTANT_TYPE (1 << 1) 2882b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R500FP_CONSTANT_CLAMP (1 << 2) 2892b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2902b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Primitive types 2912b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 2922b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_POINTS 0x1 2932b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_LINES 0x2 2942b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_LINE_STRIP 0x3 2952b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_TRIANGLES 0x4 2962b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_TRIANGLE_FAN 0x5 2972b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_TRIANGLE_STRIP 0x6 2982b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 2992b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Vertex/indirect buffer size 3002b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 3012b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_BUFFER_SIZE 65536 3022b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3032b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Byte offsets for indirect buffer data 3042b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 3052b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_INDEX_PRIM_OFFSET 20 3062b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3072b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_SCRATCH_REG_OFFSET 32 3082b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3092b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define R600_SCRATCH_REG_OFFSET 256 3102b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3112b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_NR_SAREA_CLIPRECTS 12 3122b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3132b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* There are 2 heaps (local/GART). Each region within a heap is a 3142b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * minimum of 64k, and there are at most 64 of them per heap. 3152b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 3162b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_LOCAL_TEX_HEAP 0 3172b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_GART_TEX_HEAP 1 3182b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_NR_TEX_HEAPS 2 3192b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_NR_TEX_REGIONS 64 3202b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_LOG_TEX_GRANULARITY 16 3212b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3222b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_MAX_TEXTURE_LEVELS 12 3232b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_MAX_TEXTURE_UNITS 3 3242b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3252b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_MAX_SURFACES 8 3262b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3272b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Blits have strict offset rules. All blit offset must be aligned on 3282b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * a 1K-byte boundary. 3292b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 3302b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_OFFSET_SHIFT 10 3312b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 3322b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 3332b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3342b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#endif /* __RADEON_SAREA_DEFINES__ */ 3352b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3362b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct { 3372b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int red; 3382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int green; 3392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int blue; 3402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int alpha; 3412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} radeon_color_regs_t; 3422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct { 3442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Context state */ 3452b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_misc; /* 0x1c14 */ 3462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_fog_color; 3472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int re_solid_color; 3482b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_blendcntl; 3492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_depthoffset; 3502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_depthpitch; 3512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_zstencilcntl; 3522b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3532b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_cntl; /* 0x1c38 */ 3542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_cntl; 3552b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_coloroffset; 3562b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int re_width_height; 3572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_colorpitch; 3582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_cntl; 3592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Vertex format state */ 3612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_coord_fmt; /* 0x1c50 */ 3622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Line state */ 3642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int re_line_pattern; /* 0x1cd0 */ 3652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int re_line_state; 3662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_line_width; /* 0x1db8 */ 3682b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3692b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Bumpmap state */ 3702b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_lum_matrix; /* 0x1d00 */ 3712b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3722b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_rot_matrix_0; /* 0x1d58 */ 3732b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_rot_matrix_1; 3742b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3752b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Mask state */ 3762b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 3772b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_ropcntl; 3782b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int rb3d_planemask; 3792b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3802b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Viewport state */ 3812b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_vport_xscale; /* 0x1d98 */ 3822b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_vport_xoffset; 3832b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_vport_yscale; 3842b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_vport_yoffset; 3852b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_vport_zscale; 3862b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_vport_zoffset; 3872b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3882b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Setup state */ 3892b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_cntl_status; /* 0x2140 */ 3902b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3912b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Misc state */ 3922b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int re_top_left; /* 0x26c0 */ 3932b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int re_misc; 3942b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_context_regs_t; 3952b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 3962b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct { 3972b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Zbias state */ 3982b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_zbias_factor; /* 0x1dac */ 3992b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int se_zbias_constant; 4002b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_context2_regs_t; 4012b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 4022b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Setup registers for each texture unit 4032b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 4042b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct { 4052b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_txfilter; 4062b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_txformat; 4072b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_txoffset; 4082b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_txcblend; 4092b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_txablend; 4102b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_tfactor; 4112b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int pp_border_color; 4122b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_texture_regs_t; 4132b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 4142b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct { 4152b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int start; 4162b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int finish; 4172b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int prim:8; 4182b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int stateidx:8; 4192b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 4202b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int vc_format; /* vertex format */ 4212b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_prim_t; 4222b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 4232b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct { 4242b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg drm_radeon_context_regs_t context; 4252b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 4262b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg drm_radeon_context2_regs_t context2; 4272b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int dirty; 4282b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_state_t; 4292b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 4302b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct { 4312b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* The channel for communication of state information to the 4322b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * kernel on firing a vertex buffer with either of the 4332b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * obsoleted vertex/index ioctls. 4342b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 4352b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg drm_radeon_context_regs_t context_state; 4362b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 4372b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int dirty; 4382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int vertsize; 4392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int vc_format; 4402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 4412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* The current cliprects, or a subset thereof. 4422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 4432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 4442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int nbox; 4452b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 4462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* Counters for client-side throttling of rendering clients. 4472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 4482b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int last_frame; 4492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int last_dispatch; 4502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int last_clear; 4512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 4522b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 4532b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 1]; 4542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 4552b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int ctx_owner; 4562b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int pfState; /* number of 3d windows (0,1,2ormore) */ 4572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int pfCurrentPage; /* which buffer is being displayed? */ 4582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int crtc2_base; /* CRTC2 frame offset */ 4592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 4602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_sarea_t; 4612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 4622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* WARNING: If you change any of these defines, make sure to change the 4632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * defines in the Xserver file (xf86drmRadeon.h) 4642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * 4652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * KW: actually it's illegal to change any of this (backwards compatibility). 4662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 4672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 4682b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Radeon specific ioctls 4692b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * The device specific ioctl range is 0x40 to 0x79. 4702b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 4712b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_CP_INIT 0x00 4722b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_CP_START 0x01 4732b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_CP_STOP 0x02 4742b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_CP_RESET 0x03 4752b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_CP_IDLE 0x04 4762b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_RESET 0x05 4772b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_FULLSCREEN 0x06 4782b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_SWAP 0x07 4792b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_CLEAR 0x08 4802b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_VERTEX 0x09 4812b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_INDICES 0x0A 4822b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_NOT_USED 4832b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_STIPPLE 0x0C 4842b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_INDIRECT 0x0D 4852b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_TEXTURE 0x0E 4862b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_VERTEX2 0x0F 4872b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_CMDBUF 0x10 4882b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GETPARAM 0x11 4892b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_FLIP 0x12 4902b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_ALLOC 0x13 4912b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_FREE 0x14 4922b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_INIT_HEAP 0x15 4932b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_IRQ_EMIT 0x16 4942b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_IRQ_WAIT 0x17 4952b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_CP_RESUME 0x18 4962b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_SETPARAM 0x19 4972b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_SURF_ALLOC 0x1a 4982b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_SURF_FREE 0x1b 4992b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* KMS ioctl */ 5002b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_INFO 0x1c 5012b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_CREATE 0x1d 5022b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_MMAP 0x1e 5032b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_PREAD 0x21 5042b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_PWRITE 0x22 5052b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_SET_DOMAIN 0x23 5062b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_WAIT_IDLE 0x24 5072b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_CS 0x26 5082b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_INFO 0x27 5092b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_SET_TILING 0x28 5102b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_GET_TILING 0x29 5112b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_GEM_BUSY 0x2a 512309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define DRM_RADEON_GEM_VA 0x2b 5134e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define DRM_RADEON_GEM_OP 0x2c 5142b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 5152b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 5162b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 5172b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 5182b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 5192b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 5202b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 5212b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 5222b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 5232b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 5242b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 5252b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 5262b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 5272b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 5282b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 5292b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 5302b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 5312b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 5322b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 5332b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 5342b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 5352b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 5362b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 5372b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 5382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 5392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 5402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 5412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 5422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* KMS */ 5432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 5442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 5452b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 5462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 5472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 5482b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 5492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 5502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 5512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 5524e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 5534e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 5542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 555309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 5564e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) 5572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 5582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_init { 5592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg enum { 5602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg RADEON_INIT_CP = 0x01, 5612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg RADEON_CLEANUP_CP = 0x02, 5622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg RADEON_INIT_R200_CP = 0x03, 5632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg RADEON_INIT_R300_CP = 0x04, 5642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg RADEON_INIT_R600_CP = 0x05 5652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } func; 5662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned long sarea_priv_offset; 5672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int is_pci; 5682b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int cp_mode; 5692b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int gart_size; 5702b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int ring_size; 5712b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int usec_timeout; 5722b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 5732b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int fb_bpp; 5742b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int front_offset, front_pitch; 5752b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int back_offset, back_pitch; 5762b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int depth_bpp; 5772b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int depth_offset, depth_pitch; 5782b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 5792b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned long fb_offset; 5802b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned long mmio_offset; 5812b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned long ring_offset; 5822b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned long ring_rptr_offset; 5832b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned long buffers_offset; 5842b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned long gart_textures_offset; 5852b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_init_t; 5862b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 5872b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_cp_stop { 5882b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int flush; 5892b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int idle; 5902b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_cp_stop_t; 5912b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 5922b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_fullscreen { 5932b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg enum { 5942b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg RADEON_INIT_FULLSCREEN = 0x01, 5952b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg RADEON_CLEANUP_FULLSCREEN = 0x02 5962b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg } func; 5972b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_fullscreen_t; 5982b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 5992b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define CLEAR_X1 0 6002b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define CLEAR_Y1 1 6012b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define CLEAR_X2 2 6022b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define CLEAR_Y2 3 6032b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define CLEAR_DEPTH 4 6042b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6052b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef union drm_radeon_clear_rect { 6062b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg float f[5]; 6072b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int ui[5]; 6082b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_clear_rect_t; 6092b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6102b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_clear { 6112b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int flags; 6122b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int clear_color; 6132b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int clear_depth; 6142b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int color_mask; 6152b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int depth_mask; /* misnamed field: should be stencil */ 6162b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg drm_radeon_clear_rect_t *depth_boxes; 6172b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_clear_t; 6182b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6192b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_vertex { 6202b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int prim; 6212b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int idx; /* Index of vertex buffer */ 6222b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int count; /* Number of vertices in buffer */ 6232b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int discard; /* Client finished with buffer? */ 6242b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_vertex_t; 6252b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6262b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_indices { 6272b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int prim; 6282b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int idx; 6292b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int start; 6302b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int end; 6312b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int discard; /* Client finished with buffer? */ 6322b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_indices_t; 6332b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6342b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 6352b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * - allows multiple primitives and state changes in a single ioctl 6362b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * - supports driver change to emit native primitives 6372b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 6382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_vertex2 { 6392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int idx; /* Index of vertex buffer */ 6402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int discard; /* Client finished with buffer? */ 6412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int nr_states; 6422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg drm_radeon_state_t *state; 6432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int nr_prims; 6442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg drm_radeon_prim_t *prim; 6452b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_vertex2_t; 6462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* v1.3 - obsoletes drm_radeon_vertex2 6484e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák * - allows arbitrarily large cliprect list 6492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * - allows updating of tcl packet, vector and scalar state 6502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * - allows memory-efficient description of state updates 6512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * - allows state to be emitted without a primitive 6522b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * (for clears, ctx switches) 6532b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * - allows more than one dma buffer to be referenced per ioctl 6542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * - supports tcl driver 6552b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * - may be extended in future versions with new cmd types, packets 6562b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 6572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_cmd_buffer { 6582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int bufsz; 6592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg char *buf; 6602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int nbox; 6612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg struct drm_clip_rect *boxes; 6622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_cmd_buffer_t; 6632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_tex_image { 6652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int x, y; /* Blit coordinates */ 6662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int width, height; 6672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg const void *data; 6682b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_tex_image_t; 6692b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6702b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_texture { 6712b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int offset; 6722b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int pitch; 6732b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int format; 6742b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int width; /* Texture image coordinates */ 6752b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int height; 6762b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg drm_radeon_tex_image_t *image; 6772b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_texture_t; 6782b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6792b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_stipple { 6802b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int *mask; 6812b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_stipple_t; 6822b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6832b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_indirect { 6842b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int idx; 6852b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int start; 6862b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int end; 6872b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int discard; 6882b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_indirect_t; 6892b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6902b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* enum for card type parameters */ 6912b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CARD_PCI 0 6922b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CARD_AGP 1 6932b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CARD_PCIE 2 6942b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 6952b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* 1.3: An ioctl to get parameters that aren't available to the 3d 6962b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * client any other way. 6972b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 6982b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 6992b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_LAST_FRAME 2 7002b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_LAST_DISPATCH 3 7012b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_LAST_CLEAR 4 7022b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Added with DRM version 1.6. */ 7032b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_IRQ_NR 5 7042b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 7052b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* Added with DRM version 1.8. */ 7062b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 7072b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_STATUS_HANDLE 8 7082b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_SAREA_HANDLE 9 7092b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_GART_TEX_HANDLE 10 7102b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_SCRATCH_OFFSET 11 7112b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_CARD_TYPE 12 7122b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 7132b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 7142b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ 7152b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_DEVICE_ID 16 7162b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ 7172b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7182b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_getparam { 7192b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int param; 7202b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg void *value; 7212b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_getparam_t; 7222b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7232b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* 1.6: Set up a memory manager for regions of shared memory: 7242b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 7252b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_MEM_REGION_GART 1 7262b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_MEM_REGION_FB 2 7272b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7282b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_mem_alloc { 7292b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int region; 7302b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int alignment; 7312b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int size; 7322b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int *region_offset; /* offset from start of fb or GART */ 7332b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_mem_alloc_t; 7342b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7352b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_mem_free { 7362b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int region; 7372b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int region_offset; 7382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_mem_free_t; 7392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_mem_init_heap { 7412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int region; 7422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int size; 7432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int start; 7442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_mem_init_heap_t; 7452b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* 1.6: Userspace can request & wait on irq's: 7472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 7482b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_irq_emit { 7492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int *irq_seq; 7502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_irq_emit_t; 7512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7522b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_irq_wait { 7532b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg int irq_seq; 7542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_irq_wait_t; 7552b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7562b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* 1.10: Clients tell the DRM where they think the framebuffer is located in 7572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * the card's address space, via a new generic ioctl to set parameters 7582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 7592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_setparam { 7612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int param; 7622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg __s64 value; 7632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_setparam_t; 7642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 7662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 7672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ 7682b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ 7692b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ 7702b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ 7712b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* 1.14: Clients can allocate/free a surface 7722b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 7732b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_surface_alloc { 7742b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int address; 7752b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int size; 7762b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int flags; 7772b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_surface_alloc_t; 7782b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7792b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergtypedef struct drm_radeon_surface_free { 7802b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg unsigned int address; 7812b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg} drm_radeon_surface_free_t; 7822b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7832b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_VBLANK_CRTC1 1 7842b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define DRM_RADEON_VBLANK_CRTC2 2 7852b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7862b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg/* 7872b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg * Kernel modesetting world below. 7882b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg */ 7892b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_GEM_DOMAIN_CPU 0x1 7902b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_GEM_DOMAIN_GTT 0x2 7912b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_GEM_DOMAIN_VRAM 0x4 7922b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7932b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_info { 7942b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t gart_size; 7952b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t vram_size; 7962b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t vram_visible; 7972b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 7982b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 7992b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_GEM_NO_BACKING_STORE 1 8002b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8012b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_create { 8022b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t size; 8032b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t alignment; 8042b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 8052b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t initial_domain; 8062b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t flags; 8072b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 8082b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 809c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_MACRO 0x1 810c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_MICRO 0x2 811c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_SWAP_16BIT 0x4 8124c5de721c4ef96ef412fd6af4cb415f04a7515f6Marek Olšák#define RADEON_TILING_R600_NO_SCANOUT RADEON_TILING_SWAP_16BIT 813c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_SWAP_32BIT 0x8 814c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse/* this object requires a surface when mapped - i.e. front buffer */ 815c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_SURFACE 0x10 816c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_MICRO_SQUARE 0x20 817c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_BANKW_SHIFT 8 818c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_BANKW_MASK 0xf 819c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_BANKH_SHIFT 12 820c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_BANKH_MASK 0xf 821c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 822c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 823c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 824c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 825c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 826c51f7f0e460dcadb9f1a56ecf1615810877c33c8Jerome Glisse#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 8272b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8282b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_set_tiling { 8292b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 8302b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t tiling_flags; 8312b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t pitch; 8322b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 8332b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8342b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_get_tiling { 8352b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 8362b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t tiling_flags; 8372b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t pitch; 8382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 8392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_mmap { 8412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 8422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t pad; 8432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t offset; 8442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t size; 8452b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t addr_ptr; 8462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 8472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8482b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_set_domain { 8492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 8502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t read_domains; 8512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t write_domain; 8522b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 8532b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_wait_idle { 8552b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 8562b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t pad; 8572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 8582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_busy { 8602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 8612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t domain; 8622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 8632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_pread { 8652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /** Handle for the object being read. */ 8662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 8672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t pad; 8682b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /** Offset into the object to read from */ 8692b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t offset; 8702b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /** Length of data to read */ 8712b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t size; 8722b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /** Pointer to write the data into. */ 8732b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* void *, but pointers are not 32/64 compatible */ 8742b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t data_ptr; 8752b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 8762b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8772b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_gem_pwrite { 8782b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /** Handle for the object being written to. */ 8792b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 8802b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t pad; 8812b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /** Offset into the object to write to */ 8822b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t offset; 8832b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /** Length of data to write */ 8842b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t size; 8852b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /** Pointer to read the data from. */ 8862b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* void *, but pointers are not 32/64 compatible */ 8872b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t data_ptr; 8882b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 8892b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 8904e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák/* Sets or returns a value associated with a buffer. */ 8914e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšákstruct drm_radeon_gem_op { 8924e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák uint32_t handle; /* buffer */ 8934e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák uint32_t op; /* RADEON_GEM_OP_* */ 8944e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák uint64_t value; /* input or return value */ 8954e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák}; 8964e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák 8974e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 8984e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1 8994e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák 900309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VA_MAP 1 901309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VA_UNMAP 2 902309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse 903309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VA_RESULT_OK 0 904309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VA_RESULT_ERROR 1 905309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VA_RESULT_VA_EXIST 2 906309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse 907309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VM_PAGE_VALID (1 << 0) 908309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VM_PAGE_READABLE (1 << 1) 909309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VM_PAGE_WRITEABLE (1 << 2) 910309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VM_PAGE_SYSTEM (1 << 3) 911309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_VM_PAGE_SNOOPED (1 << 4) 912309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse 913309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glissestruct drm_radeon_gem_va { 914309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse uint32_t handle; 915309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse uint32_t operation; 916309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse uint32_t vm_id; 917309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse uint32_t flags; 918309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse uint64_t offset; 919309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse}; 920309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse 9212b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CHUNK_ID_RELOCS 0x01 9222b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_CHUNK_ID_IB 0x02 923309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_CHUNK_ID_FLAGS 0x03 924309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_CHUNK_ID_CONST_IB 0x04 925309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse 926309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ 927309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_CS_KEEP_TILING_FLAGS 0x01 928309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_CS_USE_VM 0x02 929309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */ 930309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ 931309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_CS_RING_GFX 0 932309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_CS_RING_COMPUTE 1 933309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_CS_RING_DMA 2 934309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_CS_RING_UVD 3 9354e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_CS_RING_VCE 4 936309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ 937309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* 0 = normal, + = higher priority, - = lower priority */ 9382b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 9392b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_cs_chunk { 9402b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t chunk_id; 9412b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t length_dw; 9422b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t chunk_data; 9432b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 9442b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 945309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* drm_radeon_cs_reloc.flags */ 946309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse 9472b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_cs_reloc { 9482b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t handle; 9492b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t read_domains; 9502b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t write_domain; 9512b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t flags; 9522b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 9532b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 9542b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_cs { 9552b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t num_chunks; 9562b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t cs_id; 9572b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* this points to uint64_t * which point to cs chunks */ 9582b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t chunks; 9592b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg /* updates to the limits after this CS ioctl */ 9602b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t gart_limit; 9612b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t vram_limit; 9622b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 9632b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 9642b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_INFO_DEVICE_ID 0x00 9652b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_INFO_NUM_GB_PIPES 0x01 9662b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_INFO_NUM_Z_PIPES 0x02 9672b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#define RADEON_INFO_ACCEL_WORKING 0x03 968431f7f00db844534dbcf9a63da0d2832a3d91bffDave Airlie#define RADEON_INFO_CRTC_FROM_ID 0x04 969431f7f00db844534dbcf9a63da0d2832a3d91bffDave Airlie#define RADEON_INFO_ACCEL_WORKING2 0x05 970431f7f00db844534dbcf9a63da0d2832a3d91bffDave Airlie#define RADEON_INFO_TILING_CONFIG 0x06 971431f7f00db844534dbcf9a63da0d2832a3d91bffDave Airlie#define RADEON_INFO_WANT_HYPERZ 0x07 972309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ 973309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ 974309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ 975309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ 976309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ 977309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ 978309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* virtual address start, va < start are reserved by the kernel */ 979309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_VA_START 0x0e 980309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* maximum size of ib using the virtual memory cs */ 981309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 982309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* max pipes - needed for compute shaders */ 983309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_MAX_PIPES 0x10 984309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ 985309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_TIMESTAMP 0x11 986309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* max shader engines (SE) - needed for geometry shaders, etc. */ 987309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_MAX_SE 0x12 988309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* max SH per SE */ 989309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_MAX_SH_PER_SE 0x13 990309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* fast fb access is enabled */ 991309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_FASTFB_WORKING 0x14 992309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* query if a RADEON_CS_RING_* submission is supported */ 993309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_RING_WORKING 0x15 994309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* SI tile mode array */ 995309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 99667d92404d62044972599dcef3011d17fca46eed5Marek Olšák/* query if CP DMA is supported on the compute ring */ 99767d92404d62044972599dcef3011d17fca46eed5Marek Olšák#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 99867d92404d62044972599dcef3011d17fca46eed5Marek Olšák/* CIK macrotile mode array */ 99967d92404d62044972599dcef3011d17fca46eed5Marek Olšák#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 10004e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák/* query the number of render backends */ 10014e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 10024e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák/* max engine clock - needed for OpenCL */ 10034e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_INFO_MAX_SCLK 0x1a 10044e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák/* version of VCE firmware */ 10054e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_INFO_VCE_FW_VERSION 0x1b 10064e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák/* version of VCE feedback */ 10074e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_INFO_VCE_FB_VERSION 0x1c 10084e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_INFO_NUM_BYTES_MOVED 0x1d 10094e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_INFO_VRAM_USAGE 0x1e 10104e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák#define RADEON_INFO_GTT_USAGE 0x1f 10114e77991424cc505b0cf98db29737bc9d501a4d32Marek Olšák 10122b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 10132b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsbergstruct drm_radeon_info { 10142b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t request; 10152b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint32_t pad; 10162b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg uint64_t value; 10172b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg}; 10182b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg 1019309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse/* Those correspond to the tile index to use, this is to explicitly state 1020309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse * the API that is implicitly defined by the tile mode array. 1021309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse */ 1022309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 1023309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_COLOR_1D 13 1024309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_COLOR_1D_SCANOUT 9 1025309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_COLOR_2D_8BPP 14 1026309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_COLOR_2D_16BPP 15 1027309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_COLOR_2D_32BPP 16 1028309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_COLOR_2D_64BPP 17 1029309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 1030309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 1031309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_DEPTH_STENCIL_1D 4 1032309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_DEPTH_STENCIL_2D 0 1033309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 1034309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 1035309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 1036309cb649a380d25a0eced4f3a0edb55d6b577099Jerome Glisse 103767d92404d62044972599dcef3011d17fca46eed5Marek Olšák#define CIK_TILE_MODE_COLOR_2D 14 103867d92404d62044972599dcef3011d17fca46eed5Marek Olšák#define CIK_TILE_MODE_COLOR_2D_SCANOUT 10 103967d92404d62044972599dcef3011d17fca46eed5Marek Olšák#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64 0 104067d92404d62044972599dcef3011d17fca46eed5Marek Olšák#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128 1 104167d92404d62044972599dcef3011d17fca46eed5Marek Olšák#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256 2 104267d92404d62044972599dcef3011d17fca46eed5Marek Olšák#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512 3 104367d92404d62044972599dcef3011d17fca46eed5Marek Olšák#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4 1044a48d6e5621fea701e36724cc144d9fe293332824Michel Dänzer#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 1045a48d6e5621fea701e36724cc144d9fe293332824Michel Dänzer 10462b42af9a2fd8e35e920d61a212ce6b9c85354289Kristian Høgsberg#endif 1047