ArchSpec.cpp revision 224c4cc1585f6f7539771be2a8fa2e7ef7ccf08d
1//===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "lldb/Core/ArchSpec.h" 11 12#include <stdio.h> 13 14#include <string> 15 16#include "llvm/Support/ELF.h" 17#include "llvm/Support/MachO.h" 18 19using namespace lldb; 20using namespace lldb_private; 21 22#define ARCH_SPEC_SEPARATOR_CHAR '-' 23 24 25//---------------------------------------------------------------------- 26// A structure that describes all of the information we want to know 27// about each architecture. 28//---------------------------------------------------------------------- 29struct ArchDefinition 30{ 31 uint32_t cpu; 32 uint32_t sub; 33 const char *name; 34}; 35 36 37static const char *g_arch_type_strings[] = 38{ 39 "invalid", 40 "mach-o", 41 "elf" 42}; 43 44#define CPU_ANY (UINT32_MAX) 45 46//---------------------------------------------------------------------- 47// A table that gets searched linearly for matches. This table is used 48// to convert cpu type and subtypes to architecture names, and to 49// convert architecture names to cpu types and subtypes. The ordering 50// is important and allows the precedence to be set when the table is 51// built. 52//---------------------------------------------------------------------- 53static ArchDefinition g_mach_arch_defs[] = 54{ 55 { CPU_ANY, CPU_ANY , "all" }, 56 { llvm::MachO::CPUTypeARM, CPU_ANY , "arm" }, 57 { llvm::MachO::CPUTypeARM, 0 , "arm" }, 58 { llvm::MachO::CPUTypeARM, 5 , "armv4" }, 59 { llvm::MachO::CPUTypeARM, 6 , "armv6" }, 60 { llvm::MachO::CPUTypeARM, 7 , "armv5" }, 61 { llvm::MachO::CPUTypeARM, 8 , "xscale" }, 62 { llvm::MachO::CPUTypeARM, 9 , "armv7" }, 63 { llvm::MachO::CPUTypePowerPC, CPU_ANY , "ppc" }, 64 { llvm::MachO::CPUTypePowerPC, 0 , "ppc" }, 65 { llvm::MachO::CPUTypePowerPC, 1 , "ppc601" }, 66 { llvm::MachO::CPUTypePowerPC, 2 , "ppc602" }, 67 { llvm::MachO::CPUTypePowerPC, 3 , "ppc603" }, 68 { llvm::MachO::CPUTypePowerPC, 4 , "ppc603e" }, 69 { llvm::MachO::CPUTypePowerPC, 5 , "ppc603ev" }, 70 { llvm::MachO::CPUTypePowerPC, 6 , "ppc604" }, 71 { llvm::MachO::CPUTypePowerPC, 7 , "ppc604e" }, 72 { llvm::MachO::CPUTypePowerPC, 8 , "ppc620" }, 73 { llvm::MachO::CPUTypePowerPC, 9 , "ppc750" }, 74 { llvm::MachO::CPUTypePowerPC, 10 , "ppc7400" }, 75 { llvm::MachO::CPUTypePowerPC, 11 , "ppc7450" }, 76 { llvm::MachO::CPUTypePowerPC, 100 , "ppc970" }, 77 { llvm::MachO::CPUTypePowerPC64, 0 , "ppc64" }, 78 { llvm::MachO::CPUTypePowerPC64, 100 , "ppc970-64" }, 79 { llvm::MachO::CPUTypeI386, 3 , "i386" }, 80 { llvm::MachO::CPUTypeI386, 4 , "i486" }, 81 { llvm::MachO::CPUTypeI386, 0x84 , "i486sx" }, 82 { llvm::MachO::CPUTypeI386, CPU_ANY , "i386" }, 83 { llvm::MachO::CPUTypeX86_64, 3 , "x86_64" }, 84 { llvm::MachO::CPUTypeX86_64, CPU_ANY , "x86_64" }, 85 86 // TODO: when we get a platform that knows more about the host OS we should 87 // let it call some accessor funcitons to set the default system arch for 88 // the default, 32 and 64 bit cases instead of hard coding it in this 89 // table. 90 91#if defined (__i386__) || defined(__x86_64__) 92 { llvm::MachO::CPUTypeX86_64, 3 , LLDB_ARCH_DEFAULT }, 93 { llvm::MachO::CPUTypeI386, 3 , LLDB_ARCH_DEFAULT_32BIT }, 94 { llvm::MachO::CPUTypeX86_64, 3 , LLDB_ARCH_DEFAULT_64BIT }, 95#elif defined (__arm__) 96 { llvm::MachO::CPUTypeARM, 6 , LLDB_ARCH_DEFAULT }, 97 { llvm::MachO::CPUTypeARM, 6 , LLDB_ARCH_DEFAULT_32BIT }, 98#elif defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__) 99 { llvm::MachO::CPUTypePowerPC, 10 , LLDB_ARCH_DEFAULT }, 100 { llvm::MachO::CPUTypePowerPC, 10 , LLDB_ARCH_DEFAULT_32BIT }, 101 { llvm::MachO::CPUTypePowerPC64, 100 , LLDB_ARCH_DEFAULT_64BIT }, 102#endif 103}; 104 105//---------------------------------------------------------------------- 106// Figure out how many architecture definitions we have 107//---------------------------------------------------------------------- 108const size_t k_num_mach_arch_defs = sizeof(g_mach_arch_defs)/sizeof(ArchDefinition); 109 110 111 112//---------------------------------------------------------------------- 113// A table that gets searched linearly for matches. This table is used 114// to convert cpu type and subtypes to architecture names, and to 115// convert architecture names to cpu types and subtypes. The ordering 116// is important and allows the precedence to be set when the table is 117// built. 118//---------------------------------------------------------------------- 119static ArchDefinition g_elf_arch_defs[] = 120{ 121 { llvm::ELF::EM_M32 , 0, "m32" }, // AT&T WE 32100 122 { llvm::ELF::EM_SPARC , 0, "sparc" }, // AT&T WE 32100 123 { llvm::ELF::EM_386 , 0, "i386" }, // Intel 80386 124 { llvm::ELF::EM_68K , 0, "68k" }, // Motorola 68000 125 { llvm::ELF::EM_88K , 0, "88k" }, // Motorola 88000 126 { llvm::ELF::EM_486 , 0, "i486" }, // Intel 486 (deprecated) 127 { llvm::ELF::EM_860 , 0, "860" }, // Intel 80860 128 { llvm::ELF::EM_MIPS , 0, "rs3000" }, // MIPS RS3000 129 { llvm::ELF::EM_PPC , 0, "ppc" }, // PowerPC 130 { 21 , 0, "ppc64" }, // PowerPC64 131 { llvm::ELF::EM_ARM , 0, "arm" }, // ARM 132 { llvm::ELF::EM_ALPHA , 0, "alpha" }, // DEC Alpha 133 { llvm::ELF::EM_SPARCV9, 0, "sparc9" }, // SPARC V9 134 { llvm::ELF::EM_X86_64 , 0, "x86_64" }, // AMD64 135 136#if defined (__i386__) || defined(__x86_64__) 137 { llvm::ELF::EM_X86_64 , 0, LLDB_ARCH_DEFAULT }, 138 { llvm::ELF::EM_386 , 0, LLDB_ARCH_DEFAULT_32BIT }, 139 { llvm::ELF::EM_X86_64 , 0, LLDB_ARCH_DEFAULT_64BIT }, 140#elif defined (__arm__) 141 { llvm::ELF::EM_ARM , 0, LLDB_ARCH_DEFAULT }, 142 { llvm::ELF::EM_ARM , 0, LLDB_ARCH_DEFAULT_32BIT }, 143#elif defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__) 144 { llvm::ELF::EM_PPC , 0, LLDB_ARCH_DEFAULT }, 145 { llvm::ELF::EM_PPC , 0, LLDB_ARCH_DEFAULT_32BIT }, 146 { llvm::ELF::EM_PPC64 , 0, LLDB_ARCH_DEFAULT_64BIT }, 147#endif 148}; 149 150//---------------------------------------------------------------------- 151// Figure out how many architecture definitions we have 152//---------------------------------------------------------------------- 153const size_t k_num_elf_arch_defs = sizeof(g_elf_arch_defs)/sizeof(ArchDefinition); 154 155//---------------------------------------------------------------------- 156// Default constructor 157//---------------------------------------------------------------------- 158ArchSpec::ArchSpec() : 159 m_type (eArchTypeMachO), // Use the most complete arch definition which will always be translatable to any other ArchitectureType values 160 m_cpu (LLDB_INVALID_CPUTYPE), 161 m_sub (0) 162{ 163} 164 165//---------------------------------------------------------------------- 166// Constructor that initializes the object with supplied cpu and 167// subtypes. 168//---------------------------------------------------------------------- 169ArchSpec::ArchSpec (lldb::ArchitectureType arch_type, uint32_t cpu, uint32_t sub) : 170 m_type (arch_type), 171 m_cpu (cpu), 172 m_sub (sub) 173{ 174} 175 176//---------------------------------------------------------------------- 177// Constructor that initializes the object with supplied 178// architecture name. There are also predefined values in 179// Defines.h: 180// liblldb_ARCH_DEFAULT 181// The arch the current system defaults to when a program is 182// launched without any extra attributes or settings. 183// 184// liblldb_ARCH_DEFAULT_32BIT 185// The 32 bit arch the current system defaults to (if any) 186// 187// liblldb_ARCH_DEFAULT_32BIT 188// The 64 bit arch the current system defaults to (if any) 189//---------------------------------------------------------------------- 190ArchSpec::ArchSpec (const char *arch_name) : 191 m_type (eArchTypeMachO), // Use the most complete arch definition which will always be translatable to any other ArchitectureType values 192 m_cpu (LLDB_INVALID_CPUTYPE), 193 m_sub (0) 194{ 195 if (arch_name) 196 SetArch (arch_name); 197} 198 199//---------------------------------------------------------------------- 200// Destructor 201//---------------------------------------------------------------------- 202ArchSpec::~ArchSpec() 203{ 204} 205 206//---------------------------------------------------------------------- 207// Assignment operator 208//---------------------------------------------------------------------- 209const ArchSpec& 210ArchSpec::operator= (const ArchSpec& rhs) 211{ 212 if (this != &rhs) 213 { 214 m_type = rhs.m_type; 215 m_cpu = rhs.m_cpu; 216 m_sub = rhs.m_sub; 217 } 218 return *this; 219} 220 221//---------------------------------------------------------------------- 222// Get a C string representation of the current architecture 223//---------------------------------------------------------------------- 224const char * 225ArchSpec::AsCString() const 226{ 227 return ArchSpec::AsCString(m_type, m_cpu, m_sub); 228} 229 230//---------------------------------------------------------------------- 231// Class function to get a C string representation given a CPU type 232// and subtype. 233//---------------------------------------------------------------------- 234const char * 235ArchSpec::AsCString (lldb::ArchitectureType arch_type, uint32_t cpu, uint32_t sub) 236{ 237 if (arch_type >= kNumArchTypes) 238 return NULL; 239 240 switch (arch_type) 241 { 242 case eArchTypeInvalid: 243 break; 244 245 case eArchTypeMachO: 246 for (uint32_t i=0; i<k_num_mach_arch_defs; i++) 247 { 248 if (cpu == g_mach_arch_defs[i].cpu) 249 { 250 if (sub == g_mach_arch_defs[i].sub) 251 return g_mach_arch_defs[i].name; 252 else if (sub != CPU_ANY && sub != LLDB_INVALID_CPUTYPE) 253 { 254 if ((sub & 0x00ffffff) == g_mach_arch_defs[i].sub) 255 return g_mach_arch_defs[i].name; 256 } 257 } 258 } 259 break; 260 261 case eArchTypeELF: 262 for (uint32_t i=0; i<k_num_elf_arch_defs; i++) 263 { 264 if (cpu == g_elf_arch_defs[i].cpu) 265 { 266 if (sub == g_elf_arch_defs[i].sub) 267 return g_elf_arch_defs[i].name; 268 } 269 } 270 break; 271 } 272 273 const char *arch_type_cstr = g_arch_type_strings[arch_type]; 274 275 static char s_cpu_hex_str[128]; 276 ::snprintf(s_cpu_hex_str, 277 sizeof(s_cpu_hex_str), 278 "%s%c%u%c%u", 279 arch_type_cstr, 280 ARCH_SPEC_SEPARATOR_CHAR, 281 cpu, 282 ARCH_SPEC_SEPARATOR_CHAR, 283 sub); 284 return s_cpu_hex_str; 285} 286 287//---------------------------------------------------------------------- 288// Clears the object contents back to a default invalid state. 289//---------------------------------------------------------------------- 290void 291ArchSpec::Clear() 292{ 293 m_type = eArchTypeInvalid; 294 m_cpu = LLDB_INVALID_CPUTYPE; 295 m_sub = 0; 296} 297 298 299 300 301//---------------------------------------------------------------------- 302// CPU subtype get accessor. 303//---------------------------------------------------------------------- 304uint32_t 305ArchSpec::GetCPUSubtype() const 306{ 307 if (m_type == eArchTypeMachO) 308 { 309 if (m_sub == CPU_ANY || m_sub == LLDB_INVALID_CPUTYPE) 310 return m_sub; 311 return m_sub & 0xffffff; 312 } 313 return 0; 314} 315 316 317//---------------------------------------------------------------------- 318// CPU type get accessor. 319//---------------------------------------------------------------------- 320uint32_t 321ArchSpec::GetCPUType() const 322{ 323 return m_cpu; 324} 325 326//---------------------------------------------------------------------- 327// This function is designed to abstract us from having to know any 328// details about the current m_type, m_cpu, and m_sub values and 329// translate the result into a generic CPU type so LLDB core code can 330// detect any CPUs that it supports. 331//---------------------------------------------------------------------- 332ArchSpec::CPU 333ArchSpec::GetGenericCPUType () const 334{ 335 switch (m_type) 336 { 337 case eArchTypeInvalid: 338 break; 339 340 case eArchTypeMachO: 341 switch (m_cpu) 342 { 343 case llvm::MachO::CPUTypeARM: return eCPU_arm; 344 case llvm::MachO::CPUTypeI386: return eCPU_i386; 345 case llvm::MachO::CPUTypeX86_64: return eCPU_x86_64; 346 case llvm::MachO::CPUTypePowerPC: return eCPU_ppc; 347 case llvm::MachO::CPUTypePowerPC64: return eCPU_ppc64; 348 case llvm::MachO::CPUTypeSPARC: return eCPU_sparc; 349 } 350 break; 351 352 case eArchTypeELF: 353 switch (m_cpu) 354 { 355 case llvm::ELF::EM_ARM: return eCPU_arm; 356 case llvm::ELF::EM_386: return eCPU_i386; 357 case llvm::ELF::EM_X86_64: return eCPU_x86_64; 358 case llvm::ELF::EM_PPC: return eCPU_ppc; 359 case 21: return eCPU_ppc64; 360 case llvm::ELF::EM_SPARC: return eCPU_sparc; 361 } 362 break; 363 } 364 365 return eCPU_Unknown; 366} 367 368 369 370 371//---------------------------------------------------------------------- 372// Feature flags get accessor. 373//---------------------------------------------------------------------- 374uint32_t 375ArchSpec::GetFeatureFlags() const 376{ 377 if (m_type == eArchTypeMachO) 378 { 379 if (m_sub == CPU_ANY || m_sub == LLDB_INVALID_CPUTYPE) 380 return 0; 381 return m_sub & 0xff000000; 382 } 383 return 0; 384} 385 386 387static const char * g_i386_dwarf_reg_names[] = 388{ 389 "eax", 390 "ecx", 391 "edx", 392 "ebx", 393 "esp", 394 "ebp", 395 "esi", 396 "edi", 397 "eip", 398 "eflags" 399}; 400 401static const char * g_i386_gcc_reg_names[] = 402{ 403 "eax", 404 "ecx", 405 "edx", 406 "ebx", 407 "ebp", 408 "esp", 409 "esi", 410 "edi", 411 "eip", 412 "eflags" 413}; 414 415static const char * g_x86_64_dwarf_and_gcc_reg_names[] = { 416 "rax", 417 "rdx", 418 "rcx", 419 "rbx", 420 "rsi", 421 "rdi", 422 "rbp", 423 "rsp", 424 "r8", 425 "r9", 426 "r10", 427 "r11", 428 "r12", 429 "r13", 430 "r14", 431 "r15", 432 "rip" 433}; 434 435// Values take from: 436// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040a/IHI0040A_aadwarf.pdf 437 438enum 439{ 440 eRegNumARM_DWARF_r0 = 0, 441 eRegNumARM_DWARF_r1 = 1, 442 eRegNumARM_DWARF_r2 = 2, 443 eRegNumARM_DWARF_r3 = 3, 444 eRegNumARM_DWARF_r4 = 4, 445 eRegNumARM_DWARF_r5 = 5, 446 eRegNumARM_DWARF_r6 = 6, 447 eRegNumARM_DWARF_r7 = 7, 448 eRegNumARM_DWARF_r8 = 8, 449 eRegNumARM_DWARF_r9 = 9, 450 eRegNumARM_DWARF_r10 = 10, 451 eRegNumARM_DWARF_r11 = 11, 452 eRegNumARM_DWARF_r12 = 12, 453 eRegNumARM_DWARF_r13 = 13, // SP 454 eRegNumARM_DWARF_r14 = 14, // LR 455 eRegNumARM_DWARF_r15 = 15, // PC 456 457 eRegNumARM_DWARF_f0_obsolete= 16, 458 eRegNumARM_DWARF_f1_obsolete, 459 eRegNumARM_DWARF_f2_obsolete, 460 eRegNumARM_DWARF_f3_obsolete, 461 eRegNumARM_DWARF_f4_obsolete, 462 eRegNumARM_DWARF_f5_obsolete, 463 eRegNumARM_DWARF_f6_obsolete, 464 eRegNumARM_DWARF_f7_obsolete, 465 466 eRegNumARM_DWARF_s0_obsolete = 16, 467 eRegNumARM_DWARF_s1_obsolete, 468 eRegNumARM_DWARF_s2_obsolete, 469 eRegNumARM_DWARF_s3_obsolete, 470 eRegNumARM_DWARF_s4_obsolete, 471 eRegNumARM_DWARF_s5_obsolete, 472 eRegNumARM_DWARF_s6_obsolete, 473 eRegNumARM_DWARF_s7_obsolete, 474 eRegNumARM_DWARF_s8_obsolete, 475 eRegNumARM_DWARF_s9_obsolete, 476 eRegNumARM_DWARF_s10_obsolete, 477 eRegNumARM_DWARF_s11_obsolete, 478 eRegNumARM_DWARF_s12_obsolete, 479 eRegNumARM_DWARF_s13_obsolete, 480 eRegNumARM_DWARF_s14_obsolete, 481 eRegNumARM_DWARF_s15_obsolete, 482 eRegNumARM_DWARF_s16_obsolete, 483 eRegNumARM_DWARF_s17_obsolete, 484 eRegNumARM_DWARF_s18_obsolete, 485 eRegNumARM_DWARF_s19_obsolete, 486 eRegNumARM_DWARF_s20_obsolete, 487 eRegNumARM_DWARF_s21_obsolete, 488 eRegNumARM_DWARF_s22_obsolete, 489 eRegNumARM_DWARF_s23_obsolete, 490 eRegNumARM_DWARF_s24_obsolete, 491 eRegNumARM_DWARF_s25_obsolete, 492 eRegNumARM_DWARF_s26_obsolete, 493 eRegNumARM_DWARF_s27_obsolete, 494 eRegNumARM_DWARF_s28_obsolete, 495 eRegNumARM_DWARF_s29_obsolete, 496 eRegNumARM_DWARF_s30_obsolete, 497 eRegNumARM_DWARF_s31_obsolete, 498 499 eRegNumARM_DWARF_s0 = 64, 500 eRegNumARM_DWARF_s1, 501 eRegNumARM_DWARF_s2, 502 eRegNumARM_DWARF_s3, 503 eRegNumARM_DWARF_s4, 504 eRegNumARM_DWARF_s5, 505 eRegNumARM_DWARF_s6, 506 eRegNumARM_DWARF_s7, 507 eRegNumARM_DWARF_s8, 508 eRegNumARM_DWARF_s9, 509 eRegNumARM_DWARF_s10, 510 eRegNumARM_DWARF_s11, 511 eRegNumARM_DWARF_s12, 512 eRegNumARM_DWARF_s13, 513 eRegNumARM_DWARF_s14, 514 eRegNumARM_DWARF_s15, 515 eRegNumARM_DWARF_s16, 516 eRegNumARM_DWARF_s17, 517 eRegNumARM_DWARF_s18, 518 eRegNumARM_DWARF_s19, 519 eRegNumARM_DWARF_s20, 520 eRegNumARM_DWARF_s21, 521 eRegNumARM_DWARF_s22, 522 eRegNumARM_DWARF_s23, 523 eRegNumARM_DWARF_s24, 524 eRegNumARM_DWARF_s25, 525 eRegNumARM_DWARF_s26, 526 eRegNumARM_DWARF_s27, 527 eRegNumARM_DWARF_s28, 528 eRegNumARM_DWARF_s29, 529 eRegNumARM_DWARF_s30, 530 eRegNumARM_DWARF_s31, 531 532 eRegNumARM_DWARF_f0 = 96, 533 eRegNumARM_DWARF_f1, 534 eRegNumARM_DWARF_f2, 535 eRegNumARM_DWARF_f3, 536 eRegNumARM_DWARF_f4, 537 eRegNumARM_DWARF_f5, 538 eRegNumARM_DWARF_f6, 539 eRegNumARM_DWARF_f7, 540 541 eRegNumARM_DWARF_ACC0 = 104, 542 eRegNumARM_DWARF_ACC1, 543 eRegNumARM_DWARF_ACC2, 544 eRegNumARM_DWARF_ACC3, 545 eRegNumARM_DWARF_ACC4, 546 eRegNumARM_DWARF_ACC5, 547 eRegNumARM_DWARF_ACC6, 548 eRegNumARM_DWARF_ACC7, 549 550 eRegNumARM_DWARF_wCGR0 = 104, // These overlap with ACC0-ACC7 551 eRegNumARM_DWARF_wCGR1, 552 eRegNumARM_DWARF_wCGR2, 553 eRegNumARM_DWARF_wCGR3, 554 eRegNumARM_DWARF_wCGR4, 555 eRegNumARM_DWARF_wCGR5, 556 eRegNumARM_DWARF_wCGR6, 557 eRegNumARM_DWARF_wCGR7, 558 559 eRegNumARM_DWARF_wR0 = 112, 560 eRegNumARM_DWARF_wR1, 561 eRegNumARM_DWARF_wR2, 562 eRegNumARM_DWARF_wR3, 563 eRegNumARM_DWARF_wR4, 564 eRegNumARM_DWARF_wR5, 565 eRegNumARM_DWARF_wR6, 566 eRegNumARM_DWARF_wR7, 567 eRegNumARM_DWARF_wR8, 568 eRegNumARM_DWARF_wR9, 569 eRegNumARM_DWARF_wR10, 570 eRegNumARM_DWARF_wR11, 571 eRegNumARM_DWARF_wR12, 572 eRegNumARM_DWARF_wR13, 573 eRegNumARM_DWARF_wR14, 574 eRegNumARM_DWARF_wR15, 575 576 eRegNumARM_DWARF_spsr = 128, 577 eRegNumARM_DWARF_spsr_fiq, 578 eRegNumARM_DWARF_spsr_irq, 579 eRegNumARM_DWARF_spsr_abt, 580 eRegNumARM_DWARF_spsr_und, 581 eRegNumARM_DWARF_spsr_svc, 582 583 eRegNumARM_DWARF_r8_usr = 144, 584 eRegNumARM_DWARF_r9_usr, 585 eRegNumARM_DWARF_r10_usr, 586 eRegNumARM_DWARF_r11_usr, 587 eRegNumARM_DWARF_r12_usr, 588 eRegNumARM_DWARF_r13_usr, 589 eRegNumARM_DWARF_r14_usr, 590 591 eRegNumARM_DWARF_r8_fiq = 151, 592 eRegNumARM_DWARF_r9_fiq, 593 eRegNumARM_DWARF_r10_fiq, 594 eRegNumARM_DWARF_r11_fiq, 595 eRegNumARM_DWARF_r12_fiq, 596 eRegNumARM_DWARF_r13_fiq, 597 eRegNumARM_DWARF_r14_fiq, 598 599 eRegNumARM_DWARF_r13_irq, 600 eRegNumARM_DWARF_r14_irq, 601 602 eRegNumARM_DWARF_r13_abt, 603 eRegNumARM_DWARF_r14_abt, 604 605 eRegNumARM_DWARF_r13_und, 606 eRegNumARM_DWARF_r14_und, 607 608 eRegNumARM_DWARF_r13_svc, 609 eRegNumARM_DWARF_r14_svc, 610 611 eRegNumARM_DWARF_wC0 = 192, 612 eRegNumARM_DWARF_wC1, 613 eRegNumARM_DWARF_wC2, 614 eRegNumARM_DWARF_wC3, 615 eRegNumARM_DWARF_wC4, 616 eRegNumARM_DWARF_wC5, 617 eRegNumARM_DWARF_wC6, 618 eRegNumARM_DWARF_wC7, 619 620 eRegNumARM_DWARF_d0 = 256, // VFP-v3/NEON D0-D31 (32 64 bit registers) 621 eRegNumARM_DWARF_d1, 622 eRegNumARM_DWARF_d2, 623 eRegNumARM_DWARF_d3, 624 eRegNumARM_DWARF_d4, 625 eRegNumARM_DWARF_d5, 626 eRegNumARM_DWARF_d6, 627 eRegNumARM_DWARF_d7, 628 eRegNumARM_DWARF_d8, 629 eRegNumARM_DWARF_d9, 630 eRegNumARM_DWARF_d10, 631 eRegNumARM_DWARF_d11, 632 eRegNumARM_DWARF_d12, 633 eRegNumARM_DWARF_d13, 634 eRegNumARM_DWARF_d14, 635 eRegNumARM_DWARF_d15, 636 eRegNumARM_DWARF_d16, 637 eRegNumARM_DWARF_d17, 638 eRegNumARM_DWARF_d18, 639 eRegNumARM_DWARF_d19, 640 eRegNumARM_DWARF_d20, 641 eRegNumARM_DWARF_d21, 642 eRegNumARM_DWARF_d22, 643 eRegNumARM_DWARF_d23, 644 eRegNumARM_DWARF_d24, 645 eRegNumARM_DWARF_d25, 646 eRegNumARM_DWARF_d26, 647 eRegNumARM_DWARF_d27, 648 eRegNumARM_DWARF_d28, 649 eRegNumARM_DWARF_d29, 650 eRegNumARM_DWARF_d30, 651 eRegNumARM_DWARF_d31 652}; 653 654// Register numbering definitions for 32 and 64 bit ppc for RegisterNumberingType::Dwarf 655enum 656{ 657 eRegNumPPC_DWARF_r0 = 0, 658 eRegNumPPC_DWARF_r1 = 1, 659 eRegNumPPC_DWARF_r2 = 2, 660 eRegNumPPC_DWARF_r3 = 3, 661 eRegNumPPC_DWARF_r4 = 4, 662 eRegNumPPC_DWARF_r5 = 5, 663 eRegNumPPC_DWARF_r6 = 6, 664 eRegNumPPC_DWARF_r7 = 7, 665 eRegNumPPC_DWARF_r8 = 8, 666 eRegNumPPC_DWARF_r9 = 9, 667 eRegNumPPC_DWARF_r10 = 10, 668 eRegNumPPC_DWARF_r11 = 11, 669 eRegNumPPC_DWARF_r12 = 12, 670 eRegNumPPC_DWARF_r13 = 13, 671 eRegNumPPC_DWARF_r14 = 14, 672 eRegNumPPC_DWARF_r15 = 15, 673 eRegNumPPC_DWARF_r16 = 16, 674 eRegNumPPC_DWARF_r17 = 17, 675 eRegNumPPC_DWARF_r18 = 18, 676 eRegNumPPC_DWARF_r19 = 19, 677 eRegNumPPC_DWARF_r20 = 20, 678 eRegNumPPC_DWARF_r21 = 21, 679 eRegNumPPC_DWARF_r22 = 22, 680 eRegNumPPC_DWARF_r23 = 23, 681 eRegNumPPC_DWARF_r24 = 24, 682 eRegNumPPC_DWARF_r25 = 25, 683 eRegNumPPC_DWARF_r26 = 26, 684 eRegNumPPC_DWARF_r27 = 27, 685 eRegNumPPC_DWARF_r28 = 28, 686 eRegNumPPC_DWARF_r29 = 29, 687 eRegNumPPC_DWARF_r30 = 30, 688 eRegNumPPC_DWARF_r31 = 31, 689 690 eRegNumPPC_DWARF_fr0 = 32, 691 eRegNumPPC_DWARF_fr1 = 33, 692 eRegNumPPC_DWARF_fr2 = 34, 693 eRegNumPPC_DWARF_fr3 = 35, 694 eRegNumPPC_DWARF_fr4 = 36, 695 eRegNumPPC_DWARF_fr5 = 37, 696 eRegNumPPC_DWARF_fr6 = 38, 697 eRegNumPPC_DWARF_fr7 = 39, 698 eRegNumPPC_DWARF_fr8 = 40, 699 eRegNumPPC_DWARF_fr9 = 41, 700 eRegNumPPC_DWARF_fr10 = 42, 701 eRegNumPPC_DWARF_fr11 = 43, 702 eRegNumPPC_DWARF_fr12 = 44, 703 eRegNumPPC_DWARF_fr13 = 45, 704 eRegNumPPC_DWARF_fr14 = 46, 705 eRegNumPPC_DWARF_fr15 = 47, 706 eRegNumPPC_DWARF_fr16 = 48, 707 eRegNumPPC_DWARF_fr17 = 49, 708 eRegNumPPC_DWARF_fr18 = 50, 709 eRegNumPPC_DWARF_fr19 = 51, 710 eRegNumPPC_DWARF_fr20 = 52, 711 eRegNumPPC_DWARF_fr21 = 53, 712 eRegNumPPC_DWARF_fr22 = 54, 713 eRegNumPPC_DWARF_fr23 = 55, 714 eRegNumPPC_DWARF_fr24 = 56, 715 eRegNumPPC_DWARF_fr25 = 57, 716 eRegNumPPC_DWARF_fr26 = 58, 717 eRegNumPPC_DWARF_fr27 = 59, 718 eRegNumPPC_DWARF_fr28 = 60, 719 eRegNumPPC_DWARF_fr29 = 61, 720 eRegNumPPC_DWARF_fr30 = 62, 721 eRegNumPPC_DWARF_fr31 = 63, 722 723 eRegNumPPC_DWARF_cr = 64, 724 eRegNumPPC_DWARF_fpscr = 65, 725 eRegNumPPC_DWARF_msr = 66, 726 eRegNumPPC_DWARF_vscr = 67, 727 728 eRegNumPPC_DWARF_sr0 = 70, 729 eRegNumPPC_DWARF_sr1, 730 eRegNumPPC_DWARF_sr2, 731 eRegNumPPC_DWARF_sr3, 732 eRegNumPPC_DWARF_sr4, 733 eRegNumPPC_DWARF_sr5, 734 eRegNumPPC_DWARF_sr6, 735 eRegNumPPC_DWARF_sr7, 736 eRegNumPPC_DWARF_sr8, 737 eRegNumPPC_DWARF_sr9, 738 eRegNumPPC_DWARF_sr10, 739 eRegNumPPC_DWARF_sr11, 740 eRegNumPPC_DWARF_sr12, 741 eRegNumPPC_DWARF_sr13, 742 eRegNumPPC_DWARF_sr14, 743 eRegNumPPC_DWARF_sr15, 744 745 746 eRegNumPPC_DWARF_acc = 99, 747 eRegNumPPC_DWARF_mq = 100, 748 eRegNumPPC_DWARF_xer = 101, 749 eRegNumPPC_DWARF_rtcu = 104, 750 eRegNumPPC_DWARF_rtcl = 105, 751 752 eRegNumPPC_DWARF_lr = 108, 753 eRegNumPPC_DWARF_ctr = 109, 754 755 eRegNumPPC_DWARF_dsisr = 118, 756 eRegNumPPC_DWARF_dar = 119, 757 eRegNumPPC_DWARF_dec = 122, 758 eRegNumPPC_DWARF_sdr1 = 125, 759 eRegNumPPC_DWARF_srr0 = 126, 760 eRegNumPPC_DWARF_srr1 = 127, 761 762 eRegNumPPC_DWARF_vrsave = 356, 763 eRegNumPPC_DWARF_sprg0 = 372, 764 eRegNumPPC_DWARF_sprg1, 765 eRegNumPPC_DWARF_sprg2, 766 eRegNumPPC_DWARF_sprg3, 767 768 eRegNumPPC_DWARF_asr = 380, 769 eRegNumPPC_DWARF_ear = 382, 770 eRegNumPPC_DWARF_tb = 384, 771 eRegNumPPC_DWARF_tbu = 385, 772 eRegNumPPC_DWARF_pvr = 387, 773 774 eRegNumPPC_DWARF_spefscr = 612, 775 776 eRegNumPPC_DWARF_ibat0u = 628, 777 eRegNumPPC_DWARF_ibat0l = 629, 778 eRegNumPPC_DWARF_ibat1u = 630, 779 eRegNumPPC_DWARF_ibat1l = 631, 780 eRegNumPPC_DWARF_ibat2u = 632, 781 eRegNumPPC_DWARF_ibat2l = 633, 782 eRegNumPPC_DWARF_ibat3u = 634, 783 eRegNumPPC_DWARF_ibat3l = 635, 784 eRegNumPPC_DWARF_dbat0u = 636, 785 eRegNumPPC_DWARF_dbat0l = 637, 786 eRegNumPPC_DWARF_dbat1u = 638, 787 eRegNumPPC_DWARF_dbat1l = 639, 788 eRegNumPPC_DWARF_dbat2u = 640, 789 eRegNumPPC_DWARF_dbat2l = 641, 790 eRegNumPPC_DWARF_dbat3u = 642, 791 eRegNumPPC_DWARF_dbat3l = 643, 792 793 eRegNumPPC_DWARF_hid0 = 1108, 794 eRegNumPPC_DWARF_hid1, 795 eRegNumPPC_DWARF_hid2, 796 eRegNumPPC_DWARF_hid3, 797 eRegNumPPC_DWARF_hid4, 798 eRegNumPPC_DWARF_hid5, 799 eRegNumPPC_DWARF_hid6, 800 eRegNumPPC_DWARF_hid7, 801 eRegNumPPC_DWARF_hid8, 802 eRegNumPPC_DWARF_hid9, 803 eRegNumPPC_DWARF_hid10, 804 eRegNumPPC_DWARF_hid11, 805 eRegNumPPC_DWARF_hid12, 806 eRegNumPPC_DWARF_hid13, 807 eRegNumPPC_DWARF_hid14, 808 eRegNumPPC_DWARF_hid15, 809 810 eRegNumPPC_DWARF_vr0 = 1124, 811 eRegNumPPC_DWARF_vr1, 812 eRegNumPPC_DWARF_vr2, 813 eRegNumPPC_DWARF_vr3, 814 eRegNumPPC_DWARF_vr4, 815 eRegNumPPC_DWARF_vr5, 816 eRegNumPPC_DWARF_vr6, 817 eRegNumPPC_DWARF_vr7, 818 eRegNumPPC_DWARF_vr8, 819 eRegNumPPC_DWARF_vr9, 820 eRegNumPPC_DWARF_vr10, 821 eRegNumPPC_DWARF_vr11, 822 eRegNumPPC_DWARF_vr12, 823 eRegNumPPC_DWARF_vr13, 824 eRegNumPPC_DWARF_vr14, 825 eRegNumPPC_DWARF_vr15, 826 eRegNumPPC_DWARF_vr16, 827 eRegNumPPC_DWARF_vr17, 828 eRegNumPPC_DWARF_vr18, 829 eRegNumPPC_DWARF_vr19, 830 eRegNumPPC_DWARF_vr20, 831 eRegNumPPC_DWARF_vr21, 832 eRegNumPPC_DWARF_vr22, 833 eRegNumPPC_DWARF_vr23, 834 eRegNumPPC_DWARF_vr24, 835 eRegNumPPC_DWARF_vr25, 836 eRegNumPPC_DWARF_vr26, 837 eRegNumPPC_DWARF_vr27, 838 eRegNumPPC_DWARF_vr28, 839 eRegNumPPC_DWARF_vr29, 840 eRegNumPPC_DWARF_vr30, 841 eRegNumPPC_DWARF_vr31, 842 843 eRegNumPPC_DWARF_ev0 = 1200, 844 eRegNumPPC_DWARF_ev1, 845 eRegNumPPC_DWARF_ev2, 846 eRegNumPPC_DWARF_ev3, 847 eRegNumPPC_DWARF_ev4, 848 eRegNumPPC_DWARF_ev5, 849 eRegNumPPC_DWARF_ev6, 850 eRegNumPPC_DWARF_ev7, 851 eRegNumPPC_DWARF_ev8, 852 eRegNumPPC_DWARF_ev9, 853 eRegNumPPC_DWARF_ev10, 854 eRegNumPPC_DWARF_ev11, 855 eRegNumPPC_DWARF_ev12, 856 eRegNumPPC_DWARF_ev13, 857 eRegNumPPC_DWARF_ev14, 858 eRegNumPPC_DWARF_ev15, 859 eRegNumPPC_DWARF_ev16, 860 eRegNumPPC_DWARF_ev17, 861 eRegNumPPC_DWARF_ev18, 862 eRegNumPPC_DWARF_ev19, 863 eRegNumPPC_DWARF_ev20, 864 eRegNumPPC_DWARF_ev21, 865 eRegNumPPC_DWARF_ev22, 866 eRegNumPPC_DWARF_ev23, 867 eRegNumPPC_DWARF_ev24, 868 eRegNumPPC_DWARF_ev25, 869 eRegNumPPC_DWARF_ev26, 870 eRegNumPPC_DWARF_ev27, 871 eRegNumPPC_DWARF_ev28, 872 eRegNumPPC_DWARF_ev29, 873 eRegNumPPC_DWARF_ev30, 874 eRegNumPPC_DWARF_ev31 875}; 876 877// Register numbering definitions for 32 and 64 bit ppc for RegisterNumberingType::GCC 878enum 879{ 880 eRegNumPPC_GCC_r0 = 0, 881 eRegNumPPC_GCC_r1 = 1, 882 eRegNumPPC_GCC_r2 = 2, 883 eRegNumPPC_GCC_r3 = 3, 884 eRegNumPPC_GCC_r4 = 4, 885 eRegNumPPC_GCC_r5 = 5, 886 eRegNumPPC_GCC_r6 = 6, 887 eRegNumPPC_GCC_r7 = 7, 888 eRegNumPPC_GCC_r8 = 8, 889 eRegNumPPC_GCC_r9 = 9, 890 eRegNumPPC_GCC_r10 = 10, 891 eRegNumPPC_GCC_r11 = 11, 892 eRegNumPPC_GCC_r12 = 12, 893 eRegNumPPC_GCC_r13 = 13, 894 eRegNumPPC_GCC_r14 = 14, 895 eRegNumPPC_GCC_r15 = 15, 896 eRegNumPPC_GCC_r16 = 16, 897 eRegNumPPC_GCC_r17 = 17, 898 eRegNumPPC_GCC_r18 = 18, 899 eRegNumPPC_GCC_r19 = 19, 900 eRegNumPPC_GCC_r20 = 20, 901 eRegNumPPC_GCC_r21 = 21, 902 eRegNumPPC_GCC_r22 = 22, 903 eRegNumPPC_GCC_r23 = 23, 904 eRegNumPPC_GCC_r24 = 24, 905 eRegNumPPC_GCC_r25 = 25, 906 eRegNumPPC_GCC_r26 = 26, 907 eRegNumPPC_GCC_r27 = 27, 908 eRegNumPPC_GCC_r28 = 28, 909 eRegNumPPC_GCC_r29 = 29, 910 eRegNumPPC_GCC_r30 = 30, 911 eRegNumPPC_GCC_r31 = 31, 912 eRegNumPPC_GCC_fr0 = 32, 913 eRegNumPPC_GCC_fr1 = 33, 914 eRegNumPPC_GCC_fr2 = 34, 915 eRegNumPPC_GCC_fr3 = 35, 916 eRegNumPPC_GCC_fr4 = 36, 917 eRegNumPPC_GCC_fr5 = 37, 918 eRegNumPPC_GCC_fr6 = 38, 919 eRegNumPPC_GCC_fr7 = 39, 920 eRegNumPPC_GCC_fr8 = 40, 921 eRegNumPPC_GCC_fr9 = 41, 922 eRegNumPPC_GCC_fr10 = 42, 923 eRegNumPPC_GCC_fr11 = 43, 924 eRegNumPPC_GCC_fr12 = 44, 925 eRegNumPPC_GCC_fr13 = 45, 926 eRegNumPPC_GCC_fr14 = 46, 927 eRegNumPPC_GCC_fr15 = 47, 928 eRegNumPPC_GCC_fr16 = 48, 929 eRegNumPPC_GCC_fr17 = 49, 930 eRegNumPPC_GCC_fr18 = 50, 931 eRegNumPPC_GCC_fr19 = 51, 932 eRegNumPPC_GCC_fr20 = 52, 933 eRegNumPPC_GCC_fr21 = 53, 934 eRegNumPPC_GCC_fr22 = 54, 935 eRegNumPPC_GCC_fr23 = 55, 936 eRegNumPPC_GCC_fr24 = 56, 937 eRegNumPPC_GCC_fr25 = 57, 938 eRegNumPPC_GCC_fr26 = 58, 939 eRegNumPPC_GCC_fr27 = 59, 940 eRegNumPPC_GCC_fr28 = 60, 941 eRegNumPPC_GCC_fr29 = 61, 942 eRegNumPPC_GCC_fr30 = 62, 943 eRegNumPPC_GCC_fr31 = 63, 944 eRegNumPPC_GCC_mq = 64, 945 eRegNumPPC_GCC_lr = 65, 946 eRegNumPPC_GCC_ctr = 66, 947 eRegNumPPC_GCC_ap = 67, 948 eRegNumPPC_GCC_cr0 = 68, 949 eRegNumPPC_GCC_cr1 = 69, 950 eRegNumPPC_GCC_cr2 = 70, 951 eRegNumPPC_GCC_cr3 = 71, 952 eRegNumPPC_GCC_cr4 = 72, 953 eRegNumPPC_GCC_cr5 = 73, 954 eRegNumPPC_GCC_cr6 = 74, 955 eRegNumPPC_GCC_cr7 = 75, 956 eRegNumPPC_GCC_xer = 76, 957 eRegNumPPC_GCC_v0 = 77, 958 eRegNumPPC_GCC_v1 = 78, 959 eRegNumPPC_GCC_v2 = 79, 960 eRegNumPPC_GCC_v3 = 80, 961 eRegNumPPC_GCC_v4 = 81, 962 eRegNumPPC_GCC_v5 = 82, 963 eRegNumPPC_GCC_v6 = 83, 964 eRegNumPPC_GCC_v7 = 84, 965 eRegNumPPC_GCC_v8 = 85, 966 eRegNumPPC_GCC_v9 = 86, 967 eRegNumPPC_GCC_v10 = 87, 968 eRegNumPPC_GCC_v11 = 88, 969 eRegNumPPC_GCC_v12 = 89, 970 eRegNumPPC_GCC_v13 = 90, 971 eRegNumPPC_GCC_v14 = 91, 972 eRegNumPPC_GCC_v15 = 92, 973 eRegNumPPC_GCC_v16 = 93, 974 eRegNumPPC_GCC_v17 = 94, 975 eRegNumPPC_GCC_v18 = 95, 976 eRegNumPPC_GCC_v19 = 96, 977 eRegNumPPC_GCC_v20 = 97, 978 eRegNumPPC_GCC_v21 = 98, 979 eRegNumPPC_GCC_v22 = 99, 980 eRegNumPPC_GCC_v23 = 100, 981 eRegNumPPC_GCC_v24 = 101, 982 eRegNumPPC_GCC_v25 = 102, 983 eRegNumPPC_GCC_v26 = 103, 984 eRegNumPPC_GCC_v27 = 104, 985 eRegNumPPC_GCC_v28 = 105, 986 eRegNumPPC_GCC_v29 = 106, 987 eRegNumPPC_GCC_v30 = 107, 988 eRegNumPPC_GCC_v31 = 108, 989 eRegNumPPC_GCC_vrsave = 109, 990 eRegNumPPC_GCC_vscr = 110, 991 eRegNumPPC_GCC_spe_acc = 111, 992 eRegNumPPC_GCC_spefscr = 112, 993 eRegNumPPC_GCC_sfp = 113, 994}; 995 996static const char * g_arm_gcc_reg_names[] = { 997 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 998 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 999 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1000 "cc", "sfp", "afp", 1001 "mv0", "mv1", "mv2", "mv3", "mv4", "mv5", "mv6", "mv7", 1002 "mv8", "mv9", "mv10", "mv11", "mv12", "mv13", "mv14", "mv15", 1003 "wcgr0","wcgr1","wcgr2","wcgr3", 1004 "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 1005 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15", 1006 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1007 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1008 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1009 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1010 "vfpcc" 1011}; 1012 1013//---------------------------------------------------------------------- 1014// Get register names for the current object architecture given 1015// a register number, and a reg_kind for that register number. 1016//---------------------------------------------------------------------- 1017const char * 1018ArchSpec::GetRegisterName(uint32_t reg_num, uint32_t reg_kind) const 1019{ 1020 return ArchSpec::GetRegisterName(m_type, m_cpu, m_sub, reg_num, reg_kind); 1021} 1022 1023 1024//---------------------------------------------------------------------- 1025// Get register names for the specified CPU type and subtype given 1026// a register number, and a reg_kind for that register number. 1027//---------------------------------------------------------------------- 1028const char * 1029ArchSpec::GetRegisterName (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype, uint32_t reg_num, uint32_t reg_kind) 1030{ 1031 if ((arch_type == eArchTypeMachO && cpu == llvm::MachO::CPUTypeI386) || 1032 (arch_type == eArchTypeELF && cpu == llvm::ELF::EM_386)) 1033 { 1034 switch (reg_kind) 1035 { 1036 case eRegisterKindGCC: 1037 if (reg_num < sizeof(g_i386_gcc_reg_names)/sizeof(const char *)) 1038 return g_i386_gcc_reg_names[reg_num]; 1039 break; 1040 case eRegisterKindDWARF: 1041 if (reg_num < sizeof(g_i386_dwarf_reg_names)/sizeof(const char *)) 1042 return g_i386_dwarf_reg_names[reg_num]; 1043 break; 1044 default: 1045 break; 1046 } 1047 } 1048 else if ((arch_type == eArchTypeMachO && cpu == llvm::MachO::CPUTypeX86_64) || 1049 (arch_type == eArchTypeELF && cpu == llvm::ELF::EM_X86_64)) 1050 { 1051 switch (reg_kind) 1052 { 1053 case eRegisterKindGCC: 1054 case eRegisterKindDWARF: 1055 if (reg_num < sizeof(g_x86_64_dwarf_and_gcc_reg_names)/sizeof(const char *)) 1056 return g_x86_64_dwarf_and_gcc_reg_names[reg_num]; 1057 break; 1058 default: 1059 break; 1060 } 1061 } 1062 else if ((arch_type == eArchTypeMachO && cpu == llvm::MachO::CPUTypeARM) || 1063 (arch_type == eArchTypeELF && cpu == llvm::ELF::EM_ARM)) 1064 { 1065 switch (reg_kind) 1066 { 1067 case eRegisterKindGCC: 1068 if (reg_num < sizeof(g_arm_gcc_reg_names)/sizeof(const char *)) 1069 return g_arm_gcc_reg_names[reg_num]; 1070 break; 1071 1072 case eRegisterKindDWARF: 1073 switch (reg_num) 1074 { 1075 case eRegNumARM_DWARF_r0: return "r0"; 1076 case eRegNumARM_DWARF_r1: return "r1"; 1077 case eRegNumARM_DWARF_r2: return "r2"; 1078 case eRegNumARM_DWARF_r3: return "r3"; 1079 case eRegNumARM_DWARF_r4: return "r4"; 1080 case eRegNumARM_DWARF_r5: return "r5"; 1081 case eRegNumARM_DWARF_r6: return "r6"; 1082 case eRegNumARM_DWARF_r7: return "r7"; 1083 case eRegNumARM_DWARF_r8: return "r8"; 1084 case eRegNumARM_DWARF_r9: return "r9"; 1085 case eRegNumARM_DWARF_r10: return "r10"; 1086 case eRegNumARM_DWARF_r11: return "r11"; 1087 case eRegNumARM_DWARF_r12: return "r12"; 1088 case eRegNumARM_DWARF_r13: return "sp"; 1089 case eRegNumARM_DWARF_r14: return "lr"; 1090 case eRegNumARM_DWARF_r15: return "pc"; 1091 case eRegNumARM_DWARF_s0_obsolete: case eRegNumARM_DWARF_s0: return "s0"; 1092 case eRegNumARM_DWARF_s1_obsolete: case eRegNumARM_DWARF_s1: return "s1"; 1093 case eRegNumARM_DWARF_s2_obsolete: case eRegNumARM_DWARF_s2: return "s2"; 1094 case eRegNumARM_DWARF_s3_obsolete: case eRegNumARM_DWARF_s3: return "s3"; 1095 case eRegNumARM_DWARF_s4_obsolete: case eRegNumARM_DWARF_s4: return "s4"; 1096 case eRegNumARM_DWARF_s5_obsolete: case eRegNumARM_DWARF_s5: return "s5"; 1097 case eRegNumARM_DWARF_s6_obsolete: case eRegNumARM_DWARF_s6: return "s6"; 1098 case eRegNumARM_DWARF_s7_obsolete: case eRegNumARM_DWARF_s7: return "s7"; 1099 case eRegNumARM_DWARF_s8_obsolete: case eRegNumARM_DWARF_s8: return "s8"; 1100 case eRegNumARM_DWARF_s9_obsolete: case eRegNumARM_DWARF_s9: return "s9"; 1101 case eRegNumARM_DWARF_s10_obsolete: case eRegNumARM_DWARF_s10: return "s10"; 1102 case eRegNumARM_DWARF_s11_obsolete: case eRegNumARM_DWARF_s11: return "s11"; 1103 case eRegNumARM_DWARF_s12_obsolete: case eRegNumARM_DWARF_s12: return "s12"; 1104 case eRegNumARM_DWARF_s13_obsolete: case eRegNumARM_DWARF_s13: return "s13"; 1105 case eRegNumARM_DWARF_s14_obsolete: case eRegNumARM_DWARF_s14: return "s14"; 1106 case eRegNumARM_DWARF_s15_obsolete: case eRegNumARM_DWARF_s15: return "s15"; 1107 case eRegNumARM_DWARF_s16_obsolete: case eRegNumARM_DWARF_s16: return "s16"; 1108 case eRegNumARM_DWARF_s17_obsolete: case eRegNumARM_DWARF_s17: return "s17"; 1109 case eRegNumARM_DWARF_s18_obsolete: case eRegNumARM_DWARF_s18: return "s18"; 1110 case eRegNumARM_DWARF_s19_obsolete: case eRegNumARM_DWARF_s19: return "s19"; 1111 case eRegNumARM_DWARF_s20_obsolete: case eRegNumARM_DWARF_s20: return "s20"; 1112 case eRegNumARM_DWARF_s21_obsolete: case eRegNumARM_DWARF_s21: return "s21"; 1113 case eRegNumARM_DWARF_s22_obsolete: case eRegNumARM_DWARF_s22: return "s22"; 1114 case eRegNumARM_DWARF_s23_obsolete: case eRegNumARM_DWARF_s23: return "s23"; 1115 case eRegNumARM_DWARF_s24_obsolete: case eRegNumARM_DWARF_s24: return "s24"; 1116 case eRegNumARM_DWARF_s25_obsolete: case eRegNumARM_DWARF_s25: return "s25"; 1117 case eRegNumARM_DWARF_s26_obsolete: case eRegNumARM_DWARF_s26: return "s26"; 1118 case eRegNumARM_DWARF_s27_obsolete: case eRegNumARM_DWARF_s27: return "s27"; 1119 case eRegNumARM_DWARF_s28_obsolete: case eRegNumARM_DWARF_s28: return "s28"; 1120 case eRegNumARM_DWARF_s29_obsolete: case eRegNumARM_DWARF_s29: return "s29"; 1121 case eRegNumARM_DWARF_s30_obsolete: case eRegNumARM_DWARF_s30: return "s30"; 1122 case eRegNumARM_DWARF_s31_obsolete: case eRegNumARM_DWARF_s31: return "s31"; 1123 case eRegNumARM_DWARF_f0: return "f0"; 1124 case eRegNumARM_DWARF_f1: return "f1"; 1125 case eRegNumARM_DWARF_f2: return "f2"; 1126 case eRegNumARM_DWARF_f3: return "f3"; 1127 case eRegNumARM_DWARF_f4: return "f4"; 1128 case eRegNumARM_DWARF_f5: return "f5"; 1129 case eRegNumARM_DWARF_f6: return "f6"; 1130 case eRegNumARM_DWARF_f7: return "f7"; 1131 case eRegNumARM_DWARF_wCGR0: return "wCGR0/ACC0"; 1132 case eRegNumARM_DWARF_wCGR1: return "wCGR1/ACC1"; 1133 case eRegNumARM_DWARF_wCGR2: return "wCGR2/ACC2"; 1134 case eRegNumARM_DWARF_wCGR3: return "wCGR3/ACC3"; 1135 case eRegNumARM_DWARF_wCGR4: return "wCGR4/ACC4"; 1136 case eRegNumARM_DWARF_wCGR5: return "wCGR5/ACC5"; 1137 case eRegNumARM_DWARF_wCGR6: return "wCGR6/ACC6"; 1138 case eRegNumARM_DWARF_wCGR7: return "wCGR7/ACC7"; 1139 case eRegNumARM_DWARF_wR0: return "wR0"; 1140 case eRegNumARM_DWARF_wR1: return "wR1"; 1141 case eRegNumARM_DWARF_wR2: return "wR2"; 1142 case eRegNumARM_DWARF_wR3: return "wR3"; 1143 case eRegNumARM_DWARF_wR4: return "wR4"; 1144 case eRegNumARM_DWARF_wR5: return "wR5"; 1145 case eRegNumARM_DWARF_wR6: return "wR6"; 1146 case eRegNumARM_DWARF_wR7: return "wR7"; 1147 case eRegNumARM_DWARF_wR8: return "wR8"; 1148 case eRegNumARM_DWARF_wR9: return "wR9"; 1149 case eRegNumARM_DWARF_wR10: return "wR10"; 1150 case eRegNumARM_DWARF_wR11: return "wR11"; 1151 case eRegNumARM_DWARF_wR12: return "wR12"; 1152 case eRegNumARM_DWARF_wR13: return "wR13"; 1153 case eRegNumARM_DWARF_wR14: return "wR14"; 1154 case eRegNumARM_DWARF_wR15: return "wR15"; 1155 case eRegNumARM_DWARF_spsr: return "spsr"; 1156 case eRegNumARM_DWARF_spsr_fiq: return "spsr_fiq"; 1157 case eRegNumARM_DWARF_spsr_irq: return "spsr_irq"; 1158 case eRegNumARM_DWARF_spsr_abt: return "spsr_abt"; 1159 case eRegNumARM_DWARF_spsr_und: return "spsr_und"; 1160 case eRegNumARM_DWARF_spsr_svc: return "spsr_svc"; 1161 case eRegNumARM_DWARF_r8_usr: return "r8_usr"; 1162 case eRegNumARM_DWARF_r9_usr: return "r9_usr"; 1163 case eRegNumARM_DWARF_r10_usr: return "r10_usr"; 1164 case eRegNumARM_DWARF_r11_usr: return "r11_usr"; 1165 case eRegNumARM_DWARF_r12_usr: return "r12_usr"; 1166 case eRegNumARM_DWARF_r13_usr: return "sp_usr"; 1167 case eRegNumARM_DWARF_r14_usr: return "lr_usr"; 1168 case eRegNumARM_DWARF_r8_fiq: return "r8_fiq"; 1169 case eRegNumARM_DWARF_r9_fiq: return "r9_fiq"; 1170 case eRegNumARM_DWARF_r10_fiq: return "r10_fiq"; 1171 case eRegNumARM_DWARF_r11_fiq: return "r11_fiq"; 1172 case eRegNumARM_DWARF_r12_fiq: return "r12_fiq"; 1173 case eRegNumARM_DWARF_r13_fiq: return "sp_fiq"; 1174 case eRegNumARM_DWARF_r14_fiq: return "lr_fiq"; 1175 case eRegNumARM_DWARF_r13_irq: return "sp_irq"; 1176 case eRegNumARM_DWARF_r14_irq: return "lr_irq"; 1177 case eRegNumARM_DWARF_r13_abt: return "sp_abt"; 1178 case eRegNumARM_DWARF_r14_abt: return "lr_abt"; 1179 case eRegNumARM_DWARF_r13_und: return "sp_und"; 1180 case eRegNumARM_DWARF_r14_und: return "lr_und"; 1181 case eRegNumARM_DWARF_r13_svc: return "sp_svc"; 1182 case eRegNumARM_DWARF_r14_svc: return "lr_svc"; 1183 case eRegNumARM_DWARF_wC0: return "wC0"; 1184 case eRegNumARM_DWARF_wC1: return "wC1"; 1185 case eRegNumARM_DWARF_wC2: return "wC2"; 1186 case eRegNumARM_DWARF_wC3: return "wC3"; 1187 case eRegNumARM_DWARF_wC4: return "wC4"; 1188 case eRegNumARM_DWARF_wC5: return "wC5"; 1189 case eRegNumARM_DWARF_wC6: return "wC6"; 1190 case eRegNumARM_DWARF_wC7: return "wC7"; 1191 case eRegNumARM_DWARF_d0: return "d0"; 1192 case eRegNumARM_DWARF_d1: return "d1"; 1193 case eRegNumARM_DWARF_d2: return "d2"; 1194 case eRegNumARM_DWARF_d3: return "d3"; 1195 case eRegNumARM_DWARF_d4: return "d4"; 1196 case eRegNumARM_DWARF_d5: return "d5"; 1197 case eRegNumARM_DWARF_d6: return "d6"; 1198 case eRegNumARM_DWARF_d7: return "d7"; 1199 case eRegNumARM_DWARF_d8: return "d8"; 1200 case eRegNumARM_DWARF_d9: return "d9"; 1201 case eRegNumARM_DWARF_d10: return "d10"; 1202 case eRegNumARM_DWARF_d11: return "d11"; 1203 case eRegNumARM_DWARF_d12: return "d12"; 1204 case eRegNumARM_DWARF_d13: return "d13"; 1205 case eRegNumARM_DWARF_d14: return "d14"; 1206 case eRegNumARM_DWARF_d15: return "d15"; 1207 case eRegNumARM_DWARF_d16: return "d16"; 1208 case eRegNumARM_DWARF_d17: return "d17"; 1209 case eRegNumARM_DWARF_d18: return "d18"; 1210 case eRegNumARM_DWARF_d19: return "d19"; 1211 case eRegNumARM_DWARF_d20: return "d20"; 1212 case eRegNumARM_DWARF_d21: return "d21"; 1213 case eRegNumARM_DWARF_d22: return "d22"; 1214 case eRegNumARM_DWARF_d23: return "d23"; 1215 case eRegNumARM_DWARF_d24: return "d24"; 1216 case eRegNumARM_DWARF_d25: return "d25"; 1217 case eRegNumARM_DWARF_d26: return "d26"; 1218 case eRegNumARM_DWARF_d27: return "d27"; 1219 case eRegNumARM_DWARF_d28: return "d28"; 1220 case eRegNumARM_DWARF_d29: return "d29"; 1221 case eRegNumARM_DWARF_d30: return "d30"; 1222 case eRegNumARM_DWARF_d31: return "d31"; 1223 } 1224 break; 1225 default: 1226 break; 1227 } 1228 } 1229 else if ((arch_type == eArchTypeMachO && (cpu == llvm::MachO::CPUTypePowerPC || cpu == llvm::MachO::CPUTypePowerPC64)) || 1230 (arch_type == eArchTypeELF && cpu == llvm::ELF::EM_PPC)) 1231 { 1232 switch (reg_kind) 1233 { 1234 case eRegisterKindGCC: 1235 switch (reg_num) 1236 { 1237 case eRegNumPPC_GCC_r0: return "r0"; 1238 case eRegNumPPC_GCC_r1: return "r1"; 1239 case eRegNumPPC_GCC_r2: return "r2"; 1240 case eRegNumPPC_GCC_r3: return "r3"; 1241 case eRegNumPPC_GCC_r4: return "r4"; 1242 case eRegNumPPC_GCC_r5: return "r5"; 1243 case eRegNumPPC_GCC_r6: return "r6"; 1244 case eRegNumPPC_GCC_r7: return "r7"; 1245 case eRegNumPPC_GCC_r8: return "r8"; 1246 case eRegNumPPC_GCC_r9: return "r9"; 1247 case eRegNumPPC_GCC_r10: return "r10"; 1248 case eRegNumPPC_GCC_r11: return "r11"; 1249 case eRegNumPPC_GCC_r12: return "r12"; 1250 case eRegNumPPC_GCC_r13: return "r13"; 1251 case eRegNumPPC_GCC_r14: return "r14"; 1252 case eRegNumPPC_GCC_r15: return "r15"; 1253 case eRegNumPPC_GCC_r16: return "r16"; 1254 case eRegNumPPC_GCC_r17: return "r17"; 1255 case eRegNumPPC_GCC_r18: return "r18"; 1256 case eRegNumPPC_GCC_r19: return "r19"; 1257 case eRegNumPPC_GCC_r20: return "r20"; 1258 case eRegNumPPC_GCC_r21: return "r21"; 1259 case eRegNumPPC_GCC_r22: return "r22"; 1260 case eRegNumPPC_GCC_r23: return "r23"; 1261 case eRegNumPPC_GCC_r24: return "r24"; 1262 case eRegNumPPC_GCC_r25: return "r25"; 1263 case eRegNumPPC_GCC_r26: return "r26"; 1264 case eRegNumPPC_GCC_r27: return "r27"; 1265 case eRegNumPPC_GCC_r28: return "r28"; 1266 case eRegNumPPC_GCC_r29: return "r29"; 1267 case eRegNumPPC_GCC_r30: return "r30"; 1268 case eRegNumPPC_GCC_r31: return "r31"; 1269 case eRegNumPPC_GCC_fr0: return "fr0"; 1270 case eRegNumPPC_GCC_fr1: return "fr1"; 1271 case eRegNumPPC_GCC_fr2: return "fr2"; 1272 case eRegNumPPC_GCC_fr3: return "fr3"; 1273 case eRegNumPPC_GCC_fr4: return "fr4"; 1274 case eRegNumPPC_GCC_fr5: return "fr5"; 1275 case eRegNumPPC_GCC_fr6: return "fr6"; 1276 case eRegNumPPC_GCC_fr7: return "fr7"; 1277 case eRegNumPPC_GCC_fr8: return "fr8"; 1278 case eRegNumPPC_GCC_fr9: return "fr9"; 1279 case eRegNumPPC_GCC_fr10: return "fr10"; 1280 case eRegNumPPC_GCC_fr11: return "fr11"; 1281 case eRegNumPPC_GCC_fr12: return "fr12"; 1282 case eRegNumPPC_GCC_fr13: return "fr13"; 1283 case eRegNumPPC_GCC_fr14: return "fr14"; 1284 case eRegNumPPC_GCC_fr15: return "fr15"; 1285 case eRegNumPPC_GCC_fr16: return "fr16"; 1286 case eRegNumPPC_GCC_fr17: return "fr17"; 1287 case eRegNumPPC_GCC_fr18: return "fr18"; 1288 case eRegNumPPC_GCC_fr19: return "fr19"; 1289 case eRegNumPPC_GCC_fr20: return "fr20"; 1290 case eRegNumPPC_GCC_fr21: return "fr21"; 1291 case eRegNumPPC_GCC_fr22: return "fr22"; 1292 case eRegNumPPC_GCC_fr23: return "fr23"; 1293 case eRegNumPPC_GCC_fr24: return "fr24"; 1294 case eRegNumPPC_GCC_fr25: return "fr25"; 1295 case eRegNumPPC_GCC_fr26: return "fr26"; 1296 case eRegNumPPC_GCC_fr27: return "fr27"; 1297 case eRegNumPPC_GCC_fr28: return "fr28"; 1298 case eRegNumPPC_GCC_fr29: return "fr29"; 1299 case eRegNumPPC_GCC_fr30: return "fr30"; 1300 case eRegNumPPC_GCC_fr31: return "fr31"; 1301 case eRegNumPPC_GCC_mq: return "mq"; 1302 case eRegNumPPC_GCC_lr: return "lr"; 1303 case eRegNumPPC_GCC_ctr: return "ctr"; 1304 case eRegNumPPC_GCC_ap: return "ap"; 1305 case eRegNumPPC_GCC_cr0: return "cr0"; 1306 case eRegNumPPC_GCC_cr1: return "cr1"; 1307 case eRegNumPPC_GCC_cr2: return "cr2"; 1308 case eRegNumPPC_GCC_cr3: return "cr3"; 1309 case eRegNumPPC_GCC_cr4: return "cr4"; 1310 case eRegNumPPC_GCC_cr5: return "cr5"; 1311 case eRegNumPPC_GCC_cr6: return "cr6"; 1312 case eRegNumPPC_GCC_cr7: return "cr7"; 1313 case eRegNumPPC_GCC_xer: return "xer"; 1314 case eRegNumPPC_GCC_v0: return "v0"; 1315 case eRegNumPPC_GCC_v1: return "v1"; 1316 case eRegNumPPC_GCC_v2: return "v2"; 1317 case eRegNumPPC_GCC_v3: return "v3"; 1318 case eRegNumPPC_GCC_v4: return "v4"; 1319 case eRegNumPPC_GCC_v5: return "v5"; 1320 case eRegNumPPC_GCC_v6: return "v6"; 1321 case eRegNumPPC_GCC_v7: return "v7"; 1322 case eRegNumPPC_GCC_v8: return "v8"; 1323 case eRegNumPPC_GCC_v9: return "v9"; 1324 case eRegNumPPC_GCC_v10: return "v10"; 1325 case eRegNumPPC_GCC_v11: return "v11"; 1326 case eRegNumPPC_GCC_v12: return "v12"; 1327 case eRegNumPPC_GCC_v13: return "v13"; 1328 case eRegNumPPC_GCC_v14: return "v14"; 1329 case eRegNumPPC_GCC_v15: return "v15"; 1330 case eRegNumPPC_GCC_v16: return "v16"; 1331 case eRegNumPPC_GCC_v17: return "v17"; 1332 case eRegNumPPC_GCC_v18: return "v18"; 1333 case eRegNumPPC_GCC_v19: return "v19"; 1334 case eRegNumPPC_GCC_v20: return "v20"; 1335 case eRegNumPPC_GCC_v21: return "v21"; 1336 case eRegNumPPC_GCC_v22: return "v22"; 1337 case eRegNumPPC_GCC_v23: return "v23"; 1338 case eRegNumPPC_GCC_v24: return "v24"; 1339 case eRegNumPPC_GCC_v25: return "v25"; 1340 case eRegNumPPC_GCC_v26: return "v26"; 1341 case eRegNumPPC_GCC_v27: return "v27"; 1342 case eRegNumPPC_GCC_v28: return "v28"; 1343 case eRegNumPPC_GCC_v29: return "v29"; 1344 case eRegNumPPC_GCC_v30: return "v30"; 1345 case eRegNumPPC_GCC_v31: return "v31"; 1346 case eRegNumPPC_GCC_vrsave: return "vrsave"; 1347 case eRegNumPPC_GCC_vscr: return "vscr"; 1348 case eRegNumPPC_GCC_spe_acc: return "spe_acc"; 1349 case eRegNumPPC_GCC_spefscr: return "spefscr"; 1350 case eRegNumPPC_GCC_sfp: return "sfp"; 1351 default: 1352 break; 1353 } 1354 break; 1355 1356 case eRegisterKindDWARF: 1357 switch (reg_num) 1358 { 1359 case eRegNumPPC_DWARF_r0: return "r0"; 1360 case eRegNumPPC_DWARF_r1: return "r1"; 1361 case eRegNumPPC_DWARF_r2: return "r2"; 1362 case eRegNumPPC_DWARF_r3: return "r3"; 1363 case eRegNumPPC_DWARF_r4: return "r4"; 1364 case eRegNumPPC_DWARF_r5: return "r5"; 1365 case eRegNumPPC_DWARF_r6: return "r6"; 1366 case eRegNumPPC_DWARF_r7: return "r7"; 1367 case eRegNumPPC_DWARF_r8: return "r8"; 1368 case eRegNumPPC_DWARF_r9: return "r9"; 1369 case eRegNumPPC_DWARF_r10: return "r10"; 1370 case eRegNumPPC_DWARF_r11: return "r11"; 1371 case eRegNumPPC_DWARF_r12: return "r12"; 1372 case eRegNumPPC_DWARF_r13: return "r13"; 1373 case eRegNumPPC_DWARF_r14: return "r14"; 1374 case eRegNumPPC_DWARF_r15: return "r15"; 1375 case eRegNumPPC_DWARF_r16: return "r16"; 1376 case eRegNumPPC_DWARF_r17: return "r17"; 1377 case eRegNumPPC_DWARF_r18: return "r18"; 1378 case eRegNumPPC_DWARF_r19: return "r19"; 1379 case eRegNumPPC_DWARF_r20: return "r20"; 1380 case eRegNumPPC_DWARF_r21: return "r21"; 1381 case eRegNumPPC_DWARF_r22: return "r22"; 1382 case eRegNumPPC_DWARF_r23: return "r23"; 1383 case eRegNumPPC_DWARF_r24: return "r24"; 1384 case eRegNumPPC_DWARF_r25: return "r25"; 1385 case eRegNumPPC_DWARF_r26: return "r26"; 1386 case eRegNumPPC_DWARF_r27: return "r27"; 1387 case eRegNumPPC_DWARF_r28: return "r28"; 1388 case eRegNumPPC_DWARF_r29: return "r29"; 1389 case eRegNumPPC_DWARF_r30: return "r30"; 1390 case eRegNumPPC_DWARF_r31: return "r31"; 1391 1392 case eRegNumPPC_DWARF_fr0: return "fr0"; 1393 case eRegNumPPC_DWARF_fr1: return "fr1"; 1394 case eRegNumPPC_DWARF_fr2: return "fr2"; 1395 case eRegNumPPC_DWARF_fr3: return "fr3"; 1396 case eRegNumPPC_DWARF_fr4: return "fr4"; 1397 case eRegNumPPC_DWARF_fr5: return "fr5"; 1398 case eRegNumPPC_DWARF_fr6: return "fr6"; 1399 case eRegNumPPC_DWARF_fr7: return "fr7"; 1400 case eRegNumPPC_DWARF_fr8: return "fr8"; 1401 case eRegNumPPC_DWARF_fr9: return "fr9"; 1402 case eRegNumPPC_DWARF_fr10: return "fr10"; 1403 case eRegNumPPC_DWARF_fr11: return "fr11"; 1404 case eRegNumPPC_DWARF_fr12: return "fr12"; 1405 case eRegNumPPC_DWARF_fr13: return "fr13"; 1406 case eRegNumPPC_DWARF_fr14: return "fr14"; 1407 case eRegNumPPC_DWARF_fr15: return "fr15"; 1408 case eRegNumPPC_DWARF_fr16: return "fr16"; 1409 case eRegNumPPC_DWARF_fr17: return "fr17"; 1410 case eRegNumPPC_DWARF_fr18: return "fr18"; 1411 case eRegNumPPC_DWARF_fr19: return "fr19"; 1412 case eRegNumPPC_DWARF_fr20: return "fr20"; 1413 case eRegNumPPC_DWARF_fr21: return "fr21"; 1414 case eRegNumPPC_DWARF_fr22: return "fr22"; 1415 case eRegNumPPC_DWARF_fr23: return "fr23"; 1416 case eRegNumPPC_DWARF_fr24: return "fr24"; 1417 case eRegNumPPC_DWARF_fr25: return "fr25"; 1418 case eRegNumPPC_DWARF_fr26: return "fr26"; 1419 case eRegNumPPC_DWARF_fr27: return "fr27"; 1420 case eRegNumPPC_DWARF_fr28: return "fr28"; 1421 case eRegNumPPC_DWARF_fr29: return "fr29"; 1422 case eRegNumPPC_DWARF_fr30: return "fr30"; 1423 case eRegNumPPC_DWARF_fr31: return "fr31"; 1424 1425 case eRegNumPPC_DWARF_cr: return "cr"; 1426 case eRegNumPPC_DWARF_fpscr: return "fpscr"; 1427 case eRegNumPPC_DWARF_msr: return "msr"; 1428 case eRegNumPPC_DWARF_vscr: return "vscr"; 1429 1430 case eRegNumPPC_DWARF_sr0: return "sr0"; 1431 case eRegNumPPC_DWARF_sr1: return "sr1"; 1432 case eRegNumPPC_DWARF_sr2: return "sr2"; 1433 case eRegNumPPC_DWARF_sr3: return "sr3"; 1434 case eRegNumPPC_DWARF_sr4: return "sr4"; 1435 case eRegNumPPC_DWARF_sr5: return "sr5"; 1436 case eRegNumPPC_DWARF_sr6: return "sr6"; 1437 case eRegNumPPC_DWARF_sr7: return "sr7"; 1438 case eRegNumPPC_DWARF_sr8: return "sr8"; 1439 case eRegNumPPC_DWARF_sr9: return "sr9"; 1440 case eRegNumPPC_DWARF_sr10: return "sr10"; 1441 case eRegNumPPC_DWARF_sr11: return "sr11"; 1442 case eRegNumPPC_DWARF_sr12: return "sr12"; 1443 case eRegNumPPC_DWARF_sr13: return "sr13"; 1444 case eRegNumPPC_DWARF_sr14: return "sr14"; 1445 case eRegNumPPC_DWARF_sr15: return "sr15"; 1446 1447 case eRegNumPPC_DWARF_acc: return "acc"; 1448 case eRegNumPPC_DWARF_mq: return "mq"; 1449 case eRegNumPPC_DWARF_xer: return "xer"; 1450 case eRegNumPPC_DWARF_rtcu: return "rtcu"; 1451 case eRegNumPPC_DWARF_rtcl: return "rtcl"; 1452 1453 case eRegNumPPC_DWARF_lr: return "lr"; 1454 case eRegNumPPC_DWARF_ctr: return "ctr"; 1455 1456 case eRegNumPPC_DWARF_dsisr: return "dsisr"; 1457 case eRegNumPPC_DWARF_dar: return "dar"; 1458 case eRegNumPPC_DWARF_dec: return "dec"; 1459 case eRegNumPPC_DWARF_sdr1: return "sdr1"; 1460 case eRegNumPPC_DWARF_srr0: return "srr0"; 1461 case eRegNumPPC_DWARF_srr1: return "srr1"; 1462 1463 case eRegNumPPC_DWARF_vrsave: return "vrsave"; 1464 1465 case eRegNumPPC_DWARF_sprg0: return "sprg0"; 1466 case eRegNumPPC_DWARF_sprg1: return "sprg1"; 1467 case eRegNumPPC_DWARF_sprg2: return "sprg2"; 1468 case eRegNumPPC_DWARF_sprg3: return "sprg3"; 1469 1470 case eRegNumPPC_DWARF_asr: return "asr"; 1471 case eRegNumPPC_DWARF_ear: return "ear"; 1472 case eRegNumPPC_DWARF_tb: return "tb"; 1473 case eRegNumPPC_DWARF_tbu: return "tbu"; 1474 case eRegNumPPC_DWARF_pvr: return "pvr"; 1475 1476 case eRegNumPPC_DWARF_spefscr: return "spefscr"; 1477 1478 case eRegNumPPC_DWARF_ibat0u: return "ibat0u"; 1479 case eRegNumPPC_DWARF_ibat0l: return "ibat0l"; 1480 case eRegNumPPC_DWARF_ibat1u: return "ibat1u"; 1481 case eRegNumPPC_DWARF_ibat1l: return "ibat1l"; 1482 case eRegNumPPC_DWARF_ibat2u: return "ibat2u"; 1483 case eRegNumPPC_DWARF_ibat2l: return "ibat2l"; 1484 case eRegNumPPC_DWARF_ibat3u: return "ibat3u"; 1485 case eRegNumPPC_DWARF_ibat3l: return "ibat3l"; 1486 case eRegNumPPC_DWARF_dbat0u: return "dbat0u"; 1487 case eRegNumPPC_DWARF_dbat0l: return "dbat0l"; 1488 case eRegNumPPC_DWARF_dbat1u: return "dbat1u"; 1489 case eRegNumPPC_DWARF_dbat1l: return "dbat1l"; 1490 case eRegNumPPC_DWARF_dbat2u: return "dbat2u"; 1491 case eRegNumPPC_DWARF_dbat2l: return "dbat2l"; 1492 case eRegNumPPC_DWARF_dbat3u: return "dbat3u"; 1493 case eRegNumPPC_DWARF_dbat3l: return "dbat3l"; 1494 1495 case eRegNumPPC_DWARF_hid0: return "hid0"; 1496 case eRegNumPPC_DWARF_hid1: return "hid1"; 1497 case eRegNumPPC_DWARF_hid2: return "hid2"; 1498 case eRegNumPPC_DWARF_hid3: return "hid3"; 1499 case eRegNumPPC_DWARF_hid4: return "hid4"; 1500 case eRegNumPPC_DWARF_hid5: return "hid5"; 1501 case eRegNumPPC_DWARF_hid6: return "hid6"; 1502 case eRegNumPPC_DWARF_hid7: return "hid7"; 1503 case eRegNumPPC_DWARF_hid8: return "hid8"; 1504 case eRegNumPPC_DWARF_hid9: return "hid9"; 1505 case eRegNumPPC_DWARF_hid10: return "hid10"; 1506 case eRegNumPPC_DWARF_hid11: return "hid11"; 1507 case eRegNumPPC_DWARF_hid12: return "hid12"; 1508 case eRegNumPPC_DWARF_hid13: return "hid13"; 1509 case eRegNumPPC_DWARF_hid14: return "hid14"; 1510 case eRegNumPPC_DWARF_hid15: return "hid15"; 1511 1512 case eRegNumPPC_DWARF_vr0: return "vr0"; 1513 case eRegNumPPC_DWARF_vr1: return "vr1"; 1514 case eRegNumPPC_DWARF_vr2: return "vr2"; 1515 case eRegNumPPC_DWARF_vr3: return "vr3"; 1516 case eRegNumPPC_DWARF_vr4: return "vr4"; 1517 case eRegNumPPC_DWARF_vr5: return "vr5"; 1518 case eRegNumPPC_DWARF_vr6: return "vr6"; 1519 case eRegNumPPC_DWARF_vr7: return "vr7"; 1520 case eRegNumPPC_DWARF_vr8: return "vr8"; 1521 case eRegNumPPC_DWARF_vr9: return "vr9"; 1522 case eRegNumPPC_DWARF_vr10: return "vr10"; 1523 case eRegNumPPC_DWARF_vr11: return "vr11"; 1524 case eRegNumPPC_DWARF_vr12: return "vr12"; 1525 case eRegNumPPC_DWARF_vr13: return "vr13"; 1526 case eRegNumPPC_DWARF_vr14: return "vr14"; 1527 case eRegNumPPC_DWARF_vr15: return "vr15"; 1528 case eRegNumPPC_DWARF_vr16: return "vr16"; 1529 case eRegNumPPC_DWARF_vr17: return "vr17"; 1530 case eRegNumPPC_DWARF_vr18: return "vr18"; 1531 case eRegNumPPC_DWARF_vr19: return "vr19"; 1532 case eRegNumPPC_DWARF_vr20: return "vr20"; 1533 case eRegNumPPC_DWARF_vr21: return "vr21"; 1534 case eRegNumPPC_DWARF_vr22: return "vr22"; 1535 case eRegNumPPC_DWARF_vr23: return "vr23"; 1536 case eRegNumPPC_DWARF_vr24: return "vr24"; 1537 case eRegNumPPC_DWARF_vr25: return "vr25"; 1538 case eRegNumPPC_DWARF_vr26: return "vr26"; 1539 case eRegNumPPC_DWARF_vr27: return "vr27"; 1540 case eRegNumPPC_DWARF_vr28: return "vr28"; 1541 case eRegNumPPC_DWARF_vr29: return "vr29"; 1542 case eRegNumPPC_DWARF_vr30: return "vr30"; 1543 case eRegNumPPC_DWARF_vr31: return "vr31"; 1544 1545 case eRegNumPPC_DWARF_ev0: return "ev0"; 1546 case eRegNumPPC_DWARF_ev1: return "ev1"; 1547 case eRegNumPPC_DWARF_ev2: return "ev2"; 1548 case eRegNumPPC_DWARF_ev3: return "ev3"; 1549 case eRegNumPPC_DWARF_ev4: return "ev4"; 1550 case eRegNumPPC_DWARF_ev5: return "ev5"; 1551 case eRegNumPPC_DWARF_ev6: return "ev6"; 1552 case eRegNumPPC_DWARF_ev7: return "ev7"; 1553 case eRegNumPPC_DWARF_ev8: return "ev8"; 1554 case eRegNumPPC_DWARF_ev9: return "ev9"; 1555 case eRegNumPPC_DWARF_ev10: return "ev10"; 1556 case eRegNumPPC_DWARF_ev11: return "ev11"; 1557 case eRegNumPPC_DWARF_ev12: return "ev12"; 1558 case eRegNumPPC_DWARF_ev13: return "ev13"; 1559 case eRegNumPPC_DWARF_ev14: return "ev14"; 1560 case eRegNumPPC_DWARF_ev15: return "ev15"; 1561 case eRegNumPPC_DWARF_ev16: return "ev16"; 1562 case eRegNumPPC_DWARF_ev17: return "ev17"; 1563 case eRegNumPPC_DWARF_ev18: return "ev18"; 1564 case eRegNumPPC_DWARF_ev19: return "ev19"; 1565 case eRegNumPPC_DWARF_ev20: return "ev20"; 1566 case eRegNumPPC_DWARF_ev21: return "ev21"; 1567 case eRegNumPPC_DWARF_ev22: return "ev22"; 1568 case eRegNumPPC_DWARF_ev23: return "ev23"; 1569 case eRegNumPPC_DWARF_ev24: return "ev24"; 1570 case eRegNumPPC_DWARF_ev25: return "ev25"; 1571 case eRegNumPPC_DWARF_ev26: return "ev26"; 1572 case eRegNumPPC_DWARF_ev27: return "ev27"; 1573 case eRegNumPPC_DWARF_ev28: return "ev28"; 1574 case eRegNumPPC_DWARF_ev29: return "ev29"; 1575 case eRegNumPPC_DWARF_ev30: return "ev30"; 1576 case eRegNumPPC_DWARF_ev31: return "ev31"; 1577 default: 1578 break; 1579 } 1580 break; 1581 default: 1582 break; 1583 } 1584 1585 } 1586 return NULL; 1587} 1588 1589//---------------------------------------------------------------------- 1590// Returns true if this object contains a valid architecture, false 1591// otherwise. 1592//---------------------------------------------------------------------- 1593bool 1594ArchSpec::IsValid() const 1595{ 1596 return !(m_cpu == LLDB_INVALID_CPUTYPE); 1597} 1598 1599//---------------------------------------------------------------------- 1600// Returns true if this architecture is 64 bit, otherwise 32 bit is 1601// assumed and false is returned. 1602//---------------------------------------------------------------------- 1603uint32_t 1604ArchSpec::GetAddressByteSize() const 1605{ 1606 switch (m_type) 1607 { 1608 case eArchTypeInvalid: 1609 break; 1610 1611 case eArchTypeMachO: 1612 if (GetCPUType() & llvm::MachO::CPUArchABI64) 1613 return 8; 1614 else 1615 return 4; 1616 break; 1617 1618 case eArchTypeELF: 1619 switch (m_cpu) 1620 { 1621 case llvm::ELF::EM_M32: 1622 case llvm::ELF::EM_SPARC: 1623 case llvm::ELF::EM_386: 1624 case llvm::ELF::EM_68K: 1625 case llvm::ELF::EM_88K: 1626 case llvm::ELF::EM_486: 1627 case llvm::ELF::EM_860: 1628 case llvm::ELF::EM_MIPS: 1629 case llvm::ELF::EM_PPC: 1630 case llvm::ELF::EM_ARM: 1631 case llvm::ELF::EM_ALPHA: 1632 case llvm::ELF::EM_SPARCV9: 1633 return 4; 1634 case llvm::ELF::EM_X86_64: 1635 return 8; 1636 } 1637 break; 1638 } 1639 1640 return 0; 1641} 1642 1643//---------------------------------------------------------------------- 1644// Returns the number of bytes that this object takes when an 1645// instance exists in memory. 1646//---------------------------------------------------------------------- 1647size_t 1648ArchSpec::MemorySize() const 1649{ 1650 return sizeof(ArchSpec); 1651} 1652 1653bool 1654ArchSpec::SetArchFromTargetTriple (const char *target_triple) 1655{ 1656 if (target_triple) 1657 { 1658 const char *hyphen = strchr(target_triple, '-'); 1659 if (hyphen) 1660 { 1661 std::string arch_only (target_triple, hyphen); 1662 return SetArch (arch_only.c_str()); 1663 } 1664 } 1665 return SetArch (target_triple); 1666} 1667 1668//---------------------------------------------------------------------- 1669// Change the CPU type and subtype given an architecture name. 1670//---------------------------------------------------------------------- 1671bool 1672ArchSpec::SetArch (const char *arch_name) 1673{ 1674 if (arch_name && arch_name[0] != '\0') 1675 { 1676 size_t i; 1677 1678 switch (m_type) 1679 { 1680 case eArchTypeInvalid: 1681 case eArchTypeMachO: 1682 for (i=0; i<k_num_mach_arch_defs; i++) 1683 { 1684 if (strcasecmp(arch_name, g_mach_arch_defs[i].name) == 0) 1685 { 1686 m_type = eArchTypeMachO; 1687 m_cpu = g_mach_arch_defs[i].cpu; 1688 m_sub = g_mach_arch_defs[i].sub; 1689 return true; 1690 } 1691 } 1692 break; 1693 1694 case eArchTypeELF: 1695 for (i=0; i<k_num_elf_arch_defs; i++) 1696 { 1697 if (strcasecmp(arch_name, g_elf_arch_defs[i].name) == 0) 1698 { 1699 m_cpu = g_elf_arch_defs[i].cpu; 1700 m_sub = g_elf_arch_defs[i].sub; 1701 return true; 1702 } 1703 } 1704 break; 1705 } 1706 1707 const char *str = arch_name; 1708 // Check for a numeric cpu followed by an optional separator char and numeric subtype. 1709 // This allows for support of new cpu type/subtypes without having to have 1710 // a recompiled debug core. 1711 // Examples: 1712 // "12.6" is armv6 1713 // "0x0000000c-0x00000006" is also armv6 1714 1715 m_type = eArchTypeInvalid; 1716 for (i=1; i<kNumArchTypes; ++i) 1717 { 1718 const char *arch_type_cstr = g_arch_type_strings[i]; 1719 if (strstr(str, arch_type_cstr)) 1720 { 1721 m_type = (ArchitectureType)i; 1722 str += strlen(arch_type_cstr) + 1; // Also skip separator char 1723 } 1724 } 1725 1726 if (m_type != eArchTypeInvalid) 1727 { 1728 char *end = NULL; 1729 m_cpu = ::strtoul (str, &end, 0); 1730 if (str != end) 1731 { 1732 if (*end == ARCH_SPEC_SEPARATOR_CHAR) 1733 { 1734 // We have a cputype.cpusubtype format 1735 str = end + 1; 1736 if (*str != '\0') 1737 { 1738 m_sub = strtoul(str, &end, 0); 1739 if (*end == '\0') 1740 { 1741 // We consumed the entire string and got a cpu type and subtype 1742 return true; 1743 } 1744 } 1745 } 1746 1747 // If we reach this point we have a valid cpu type, but no cpu subtype. 1748 // Search for the first matching cpu type and use the corresponding cpu 1749 // subtype. This setting should typically be the _ALL variant and should 1750 // appear first in the list for each cpu type in the g_mach_arch_defs 1751 // structure. 1752 for (i=0; i<k_num_mach_arch_defs; ++i) 1753 { 1754 if (m_cpu == g_mach_arch_defs[i].cpu) 1755 { 1756 m_sub = g_mach_arch_defs[i].sub; 1757 return true; 1758 } 1759 } 1760 1761 // Default the cpu subtype to zero when we don't have a matching 1762 // cpu type in our architecture defs structure (g_mach_arch_defs). 1763 m_sub = 0; 1764 return true; 1765 1766 } 1767 } 1768 } 1769 Clear(); 1770 return false; 1771} 1772 1773//---------------------------------------------------------------------- 1774// CPU type and subtype set accessor. 1775//---------------------------------------------------------------------- 1776void 1777ArchSpec::SetArch (uint32_t cpu_type, uint32_t cpu_subtype) 1778{ 1779 m_cpu = cpu_type; 1780 m_sub = cpu_subtype; 1781} 1782 1783//---------------------------------------------------------------------- 1784// CPU type set accessor. 1785//---------------------------------------------------------------------- 1786void 1787ArchSpec::SetCPUType (uint32_t cpu) 1788{ 1789 m_cpu = cpu; 1790} 1791 1792//---------------------------------------------------------------------- 1793// CPU subtype set accessor. 1794//---------------------------------------------------------------------- 1795void 1796ArchSpec::SetCPUSubtype (uint32_t subtype) 1797{ 1798 m_sub = subtype; 1799} 1800 1801ByteOrder 1802ArchSpec::GetDefaultEndian () const 1803{ 1804 switch (m_cpu) 1805 { 1806 case llvm::MachO::CPUTypePowerPC: 1807 case llvm::MachO::CPUTypePowerPC64: 1808 return eByteOrderBig; 1809 1810 case llvm::MachO::CPUTypeARM: 1811 case llvm::MachO::CPUTypeI386: 1812 case llvm::MachO::CPUTypeX86_64: 1813 return eByteOrderLittle; 1814 1815 default: 1816 break; 1817 } 1818 return eByteOrderInvalid; 1819} 1820 1821//---------------------------------------------------------------------- 1822// Equal operator 1823//---------------------------------------------------------------------- 1824bool 1825lldb_private::operator== (const ArchSpec& lhs, const ArchSpec& rhs) 1826{ 1827 uint32_t lhs_cpu = lhs.GetCPUType(); 1828 uint32_t rhs_cpu = rhs.GetCPUType(); 1829 1830 if (lhs_cpu == CPU_ANY || rhs_cpu == CPU_ANY) 1831 return true; 1832 1833 else if (lhs_cpu == rhs_cpu) 1834 { 1835 uint32_t lhs_subtype = lhs.GetCPUSubtype(); 1836 uint32_t rhs_subtype = rhs.GetCPUSubtype(); 1837 if (lhs_subtype == CPU_ANY || rhs_subtype == CPU_ANY) 1838 return true; 1839 return lhs_subtype == rhs_subtype; 1840 } 1841 return false; 1842} 1843 1844 1845//---------------------------------------------------------------------- 1846// Not Equal operator 1847//---------------------------------------------------------------------- 1848bool 1849lldb_private::operator!= (const ArchSpec& lhs, const ArchSpec& rhs) 1850{ 1851 return !(lhs == rhs); 1852} 1853 1854//---------------------------------------------------------------------- 1855// Less than operator 1856//---------------------------------------------------------------------- 1857bool 1858lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs) 1859{ 1860 uint32_t lhs_cpu = lhs.GetCPUType(); 1861 uint32_t rhs_cpu = rhs.GetCPUType(); 1862 1863 if (lhs_cpu == rhs_cpu) 1864 return lhs.GetCPUSubtype() < rhs.GetCPUSubtype(); 1865 1866 return lhs_cpu < rhs_cpu; 1867} 1868 1869