1//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subtarget options of a Target machine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15#define LLVM_TARGET_TARGETSUBTARGETINFO_H
16
17#include "llvm/CodeGen/PBQPRAConstraint.h"
18#include "llvm/MC/MCSubtargetInfo.h"
19#include "llvm/Support/CodeGen.h"
20
21namespace llvm {
22
23class DataLayout;
24class MachineFunction;
25class MachineInstr;
26class SDep;
27class SUnit;
28class TargetFrameLowering;
29class TargetInstrInfo;
30class TargetLowering;
31class TargetRegisterClass;
32class TargetRegisterInfo;
33class TargetSchedModel;
34class TargetSelectionDAGInfo;
35struct MachineSchedPolicy;
36template <typename T> class SmallVectorImpl;
37
38//===----------------------------------------------------------------------===//
39///
40/// TargetSubtargetInfo - Generic base class for all target subtargets.  All
41/// Target-specific options that control code generation and printing should
42/// be exposed through a TargetSubtargetInfo-derived class.
43///
44class TargetSubtargetInfo : public MCSubtargetInfo {
45  TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
46  void operator=(const TargetSubtargetInfo &) = delete;
47
48protected: // Can only create subclasses...
49  TargetSubtargetInfo();
50
51public:
52  // AntiDepBreakMode - Type of anti-dependence breaking that should
53  // be performed before post-RA scheduling.
54  typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
55  typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector;
56
57  virtual ~TargetSubtargetInfo();
58
59  // Interfaces to the major aspects of target machine information:
60  //
61  // -- Instruction opcode and operand information
62  // -- Pipelines and scheduling information
63  // -- Stack frame information
64  // -- Selection DAG lowering information
65  //
66  // N.B. These objects may change during compilation. It's not safe to cache
67  // them between functions.
68  virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
69  virtual const TargetFrameLowering *getFrameLowering() const {
70    return nullptr;
71  }
72  virtual const TargetLowering *getTargetLowering() const { return nullptr; }
73  virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
74    return nullptr;
75  }
76
77  /// getRegisterInfo - If register information is available, return it.  If
78  /// not, return null.  This is kept separate from RegInfo until RegInfo has
79  /// details of graph coloring register allocation removed from it.
80  ///
81  virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
82
83  /// getInstrItineraryData - Returns instruction itinerary data for the target
84  /// or specific subtarget.
85  ///
86  virtual const InstrItineraryData *getInstrItineraryData() const {
87    return nullptr;
88  }
89
90  /// Resolve a SchedClass at runtime, where SchedClass identifies an
91  /// MCSchedClassDesc with the isVariant property. This may return the ID of
92  /// another variant SchedClass, but repeated invocation must quickly terminate
93  /// in a nonvariant SchedClass.
94  virtual unsigned resolveSchedClass(unsigned SchedClass,
95                                     const MachineInstr *MI,
96                                     const TargetSchedModel *SchedModel) const {
97    return 0;
98  }
99
100  /// \brief True if the subtarget should run MachineScheduler after aggressive
101  /// coalescing.
102  ///
103  /// This currently replaces the SelectionDAG scheduler with the "source" order
104  /// scheduler (though see below for an option to turn this off and use the
105  /// TargetLowering preference). It does not yet disable the postRA scheduler.
106  virtual bool enableMachineScheduler() const;
107
108  /// \brief True if the machine scheduler should disable the TLI preference
109  /// for preRA scheduling with the source level scheduler.
110  virtual bool enableMachineSchedDefaultSched() const { return true; }
111
112  /// \brief True if the subtarget should enable joining global copies.
113  ///
114  /// By default this is enabled if the machine scheduler is enabled, but
115  /// can be overridden.
116  virtual bool enableJoinGlobalCopies() const;
117
118  /// \brief True if the subtarget should run PostMachineScheduler.
119  ///
120  /// This only takes effect if the target has configured the
121  /// PostMachineScheduler pass to run, or if the global cl::opt flag,
122  /// MISchedPostRA, is set.
123  virtual bool enablePostMachineScheduler() const;
124
125  /// \brief True if the subtarget should run the atomic expansion pass.
126  virtual bool enableAtomicExpand() const;
127
128  /// \brief Override generic scheduling policy within a region.
129  ///
130  /// This is a convenient way for targets that don't provide any custom
131  /// scheduling heuristics (no custom MachineSchedStrategy) to make
132  /// changes to the generic scheduling policy.
133  virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
134                                   MachineInstr *begin, MachineInstr *end,
135                                   unsigned NumRegionInstrs) const {}
136
137  // \brief Perform target specific adjustments to the latency of a schedule
138  // dependency.
139  virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
140
141  // For use with PostRAScheduling: get the anti-dependence breaking that should
142  // be performed before post-RA scheduling.
143  virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
144
145  // For use with PostRAScheduling: in CriticalPathRCs, return any register
146  // classes that should only be considered for anti-dependence breaking if they
147  // are on the critical path.
148  virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
149    return CriticalPathRCs.clear();
150  }
151
152  // For use with PostRAScheduling: get the minimum optimization level needed
153  // to enable post-RA scheduling.
154  virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
155    return CodeGenOpt::Default;
156  }
157
158  /// \brief True if the subtarget should run the local reassignment
159  /// heuristic of the register allocator.
160  /// This heuristic may be compile time intensive, \p OptLevel provides
161  /// a finer grain to tune the register allocator.
162  virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
163
164  /// \brief Enable use of alias analysis during code generation (during MI
165  /// scheduling, DAGCombine, etc.).
166  virtual bool useAA() const;
167
168  /// \brief Enable the use of the early if conversion pass.
169  virtual bool enableEarlyIfConversion() const { return false; }
170
171  /// \brief Return PBQPConstraint(s) for the target.
172  ///
173  /// Override to provide custom PBQP constraints.
174  virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
175    return nullptr;
176  }
177
178  /// Enable tracking of subregister liveness in register allocator.
179  virtual bool enableSubRegLiveness() const { return false; }
180};
181
182} // End llvm namespace
183
184#endif
185