LegalizeIntegerTypes.cpp revision 28dc98f7521933872b93156e3ebf5c9f8327b2b3
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDValue Result = SDValue(); 35 36 // See if the target wants to custom expand this node. 37 if (CustomLowerResults(N, ResNo)) 38 return; 39 40 switch (N->getOpcode()) { 41 default: 42#ifndef NDEBUG 43 cerr << "PromoteIntegerResult #" << ResNo << ": "; 44 N->dump(&DAG); cerr << "\n"; 45#endif 46 assert(0 && "Do not know how to promote this operator!"); 47 abort(); 48 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break; 49 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break; 50 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 51 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break; 52 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 53 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 54 case ISD::CONVERT_RNDSAT: 55 Result = PromoteIntRes_CONVERT_RNDSAT(N); break; 56 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 57 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 58 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 59 case ISD::EXTRACT_VECTOR_ELT: 60 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 61 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 62 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 63 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 64 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 65 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 66 case ISD::SIGN_EXTEND_INREG: 67 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 68 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 69 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 70 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 71 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 72 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break; 73 74 case ISD::SIGN_EXTEND: 75 case ISD::ZERO_EXTEND: 76 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 77 78 case ISD::FP_TO_SINT: 79 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 80 81 case ISD::AND: 82 case ISD::OR: 83 case ISD::XOR: 84 case ISD::ADD: 85 case ISD::SUB: 86 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 87 88 case ISD::SDIV: 89 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 90 91 case ISD::UDIV: 92 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 93 94 case ISD::SADDO: 95 case ISD::SSUBO: Result = PromoteIntRes_SADDSUBO(N, ResNo); break; 96 case ISD::UADDO: 97 case ISD::USUBO: Result = PromoteIntRes_UADDSUBO(N, ResNo); break; 98 case ISD::SMULO: 99 case ISD::UMULO: Result = PromoteIntRes_XMULO(N, ResNo); break; 100 101 case ISD::ATOMIC_LOAD_ADD_8: 102 case ISD::ATOMIC_LOAD_SUB_8: 103 case ISD::ATOMIC_LOAD_AND_8: 104 case ISD::ATOMIC_LOAD_OR_8: 105 case ISD::ATOMIC_LOAD_XOR_8: 106 case ISD::ATOMIC_LOAD_NAND_8: 107 case ISD::ATOMIC_LOAD_MIN_8: 108 case ISD::ATOMIC_LOAD_MAX_8: 109 case ISD::ATOMIC_LOAD_UMIN_8: 110 case ISD::ATOMIC_LOAD_UMAX_8: 111 case ISD::ATOMIC_SWAP_8: 112 case ISD::ATOMIC_LOAD_ADD_16: 113 case ISD::ATOMIC_LOAD_SUB_16: 114 case ISD::ATOMIC_LOAD_AND_16: 115 case ISD::ATOMIC_LOAD_OR_16: 116 case ISD::ATOMIC_LOAD_XOR_16: 117 case ISD::ATOMIC_LOAD_NAND_16: 118 case ISD::ATOMIC_LOAD_MIN_16: 119 case ISD::ATOMIC_LOAD_MAX_16: 120 case ISD::ATOMIC_LOAD_UMIN_16: 121 case ISD::ATOMIC_LOAD_UMAX_16: 122 case ISD::ATOMIC_SWAP_16: 123 case ISD::ATOMIC_LOAD_ADD_32: 124 case ISD::ATOMIC_LOAD_SUB_32: 125 case ISD::ATOMIC_LOAD_AND_32: 126 case ISD::ATOMIC_LOAD_OR_32: 127 case ISD::ATOMIC_LOAD_XOR_32: 128 case ISD::ATOMIC_LOAD_NAND_32: 129 case ISD::ATOMIC_LOAD_MIN_32: 130 case ISD::ATOMIC_LOAD_MAX_32: 131 case ISD::ATOMIC_LOAD_UMIN_32: 132 case ISD::ATOMIC_LOAD_UMAX_32: 133 case ISD::ATOMIC_SWAP_32: 134 case ISD::ATOMIC_LOAD_ADD_64: 135 case ISD::ATOMIC_LOAD_SUB_64: 136 case ISD::ATOMIC_LOAD_AND_64: 137 case ISD::ATOMIC_LOAD_OR_64: 138 case ISD::ATOMIC_LOAD_XOR_64: 139 case ISD::ATOMIC_LOAD_NAND_64: 140 case ISD::ATOMIC_LOAD_MIN_64: 141 case ISD::ATOMIC_LOAD_MAX_64: 142 case ISD::ATOMIC_LOAD_UMIN_64: 143 case ISD::ATOMIC_LOAD_UMAX_64: 144 case ISD::ATOMIC_SWAP_64: 145 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 146 147 case ISD::ATOMIC_CMP_SWAP_8: 148 case ISD::ATOMIC_CMP_SWAP_16: 149 case ISD::ATOMIC_CMP_SWAP_32: 150 case ISD::ATOMIC_CMP_SWAP_64: 151 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 152 } 153 154 // If Result is null, the sub-method took care of registering the result. 155 if (Result.getNode()) 156 SetPromotedInteger(SDValue(N, ResNo), Result); 157} 158 159SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 160 // Sign-extend the new bits, and continue the assertion. 161 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 162 return DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, N->getOperand(1)); 163} 164 165SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 166 // Zero the new bits, and continue the assertion. 167 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 168 return DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, N->getOperand(1)); 169} 170 171SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 172 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 173 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 174 Op2, N->getSrcValue(), N->getAlignment()); 175 // Legalized the chain result - switch anything that used the old chain to 176 // use the new one. 177 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 178 return Res; 179} 180 181SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 182 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 183 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 184 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 185 Op2, Op3, N->getSrcValue(), N->getAlignment()); 186 // Legalized the chain result - switch anything that used the old chain to 187 // use the new one. 188 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 189 return Res; 190} 191 192SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 193 SDValue InOp = N->getOperand(0); 194 MVT InVT = InOp.getValueType(); 195 MVT NInVT = TLI.getTypeToTransformTo(InVT); 196 MVT OutVT = N->getValueType(0); 197 MVT NOutVT = TLI.getTypeToTransformTo(OutVT); 198 199 switch (getTypeAction(InVT)) { 200 default: 201 assert(false && "Unknown type action!"); 202 break; 203 case Legal: 204 break; 205 case PromoteInteger: 206 if (NOutVT.bitsEq(NInVT)) 207 // The input promotes to the same size. Convert the promoted value. 208 return DAG.getNode(ISD::BIT_CONVERT, NOutVT, GetPromotedInteger(InOp)); 209 break; 210 case SoftenFloat: 211 // Promote the integer operand by hand. 212 return DAG.getNode(ISD::ANY_EXTEND, NOutVT, GetSoftenedFloat(InOp)); 213 case ExpandInteger: 214 case ExpandFloat: 215 break; 216 case ScalarizeVector: 217 // Convert the element to an integer and promote it by hand. 218 return DAG.getNode(ISD::ANY_EXTEND, NOutVT, 219 BitConvertToInteger(GetScalarizedVector(InOp))); 220 case SplitVector: 221 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 222 // pieces of the input into integers and reassemble in the final type. 223 SDValue Lo, Hi; 224 GetSplitVector(N->getOperand(0), Lo, Hi); 225 Lo = BitConvertToInteger(Lo); 226 Hi = BitConvertToInteger(Hi); 227 228 if (TLI.isBigEndian()) 229 std::swap(Lo, Hi); 230 231 InOp = DAG.getNode(ISD::ANY_EXTEND, 232 MVT::getIntegerVT(NOutVT.getSizeInBits()), 233 JoinIntegers(Lo, Hi)); 234 return DAG.getNode(ISD::BIT_CONVERT, NOutVT, InOp); 235 } 236 237 // Otherwise, lower the bit-convert to a store/load from the stack. 238 239 // Create the stack frame object. Make sure it is aligned for both 240 // the source and destination types. 241 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT); 242 243 // Emit a store to the stack slot. 244 SDValue Store = DAG.getStore(DAG.getEntryNode(), InOp, FIPtr, NULL, 0); 245 246 // Result is an extending load from the stack slot. 247 return DAG.getExtLoad(ISD::EXTLOAD, NOutVT, Store, FIPtr, NULL, 0, OutVT); 248} 249 250SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 251 SDValue Op = GetPromotedInteger(N->getOperand(0)); 252 MVT OVT = N->getValueType(0); 253 MVT NVT = Op.getValueType(); 254 255 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 256 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op), 257 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 258} 259 260SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 261 // The pair element type may be legal, or may not promote to the same type as 262 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 263 return DAG.getNode(ISD::ANY_EXTEND, 264 TLI.getTypeToTransformTo(N->getValueType(0)), 265 JoinIntegers(N->getOperand(0), N->getOperand(1))); 266} 267 268SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 269 MVT VT = N->getValueType(0); 270 // Zero extend things like i1, sign extend everything else. It shouldn't 271 // matter in theory which one we pick, but this tends to give better code? 272 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 273 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 274 SDValue(N, 0)); 275 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 276 return Result; 277} 278 279SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 280 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 281 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 282 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 283 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 284 "can only promote integers"); 285 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 286 return DAG.getConvertRndSat(OutVT, N->getOperand(0), 287 N->getOperand(1), N->getOperand(2), 288 N->getOperand(3), N->getOperand(4), CvtCode); 289} 290 291SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 292 // Zero extend to the promoted type and do the count there. 293 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 294 MVT OVT = N->getValueType(0); 295 MVT NVT = Op.getValueType(); 296 Op = DAG.getNode(ISD::CTLZ, NVT, Op); 297 // Subtract off the extra leading bits in the bigger type. 298 return DAG.getNode(ISD::SUB, NVT, Op, 299 DAG.getConstant(NVT.getSizeInBits() - 300 OVT.getSizeInBits(), NVT)); 301} 302 303SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 304 // Zero extend to the promoted type and do the count there. 305 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 306 return DAG.getNode(ISD::CTPOP, Op.getValueType(), Op); 307} 308 309SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 310 SDValue Op = GetPromotedInteger(N->getOperand(0)); 311 MVT OVT = N->getValueType(0); 312 MVT NVT = Op.getValueType(); 313 // The count is the same in the promoted type except if the original 314 // value was zero. This can be handled by setting the bit just off 315 // the top of the original type. 316 APInt TopBit(NVT.getSizeInBits(), 0); 317 TopBit.set(OVT.getSizeInBits()); 318 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); 319 return DAG.getNode(ISD::CTTZ, NVT, Op); 320} 321 322SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 323 MVT OldVT = N->getValueType(0); 324 SDValue OldVec = N->getOperand(0); 325 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 326 327 if (OldElts == 1) { 328 assert(!isTypeLegal(OldVec.getValueType()) && 329 "Legal one-element vector of a type needing promotion!"); 330 // It is tempting to follow GetScalarizedVector by a call to 331 // GetPromotedInteger, but this would be wrong because the 332 // scalarized value may not yet have been processed. 333 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 334 GetScalarizedVector(OldVec)); 335 } 336 337 // Convert to a vector half as long with an element type of twice the width, 338 // for example <4 x i16> -> <2 x i32>. 339 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 340 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 341 assert(OldVT.isSimple() && NewVT.isSimple()); 342 343 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, 344 MVT::getVectorVT(NewVT, OldElts / 2), 345 OldVec); 346 347 // Extract the element at OldIdx / 2 from the new vector. 348 SDValue OldIdx = N->getOperand(1); 349 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 350 DAG.getConstant(1, TLI.getShiftAmountTy())); 351 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 352 353 // Select the appropriate half of the element: Lo if OldIdx was even, 354 // Hi if it was odd. 355 SDValue Lo = Elt; 356 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 357 DAG.getConstant(OldVT.getSizeInBits(), 358 TLI.getShiftAmountTy())); 359 if (TLI.isBigEndian()) 360 std::swap(Lo, Hi); 361 362 // Signed extend to the promoted type. 363 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx); 364 SDValue Res = DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 365 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), Res); 366} 367 368SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 369 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 370 unsigned NewOpc = N->getOpcode(); 371 372 // If we're promoting a UINT to a larger size, check to see if the new node 373 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 374 // we can use that instead. This allows us to generate better code for 375 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 376 // legal, such as PowerPC. 377 if (N->getOpcode() == ISD::FP_TO_UINT && 378 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 379 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) 380 NewOpc = ISD::FP_TO_SINT; 381 382 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0)); 383 384 // Assert that the converted value fits in the original type. If it doesn't 385 // (eg: because the value being converted is too big), then the result of the 386 // original operation was undefined anyway, so the assert is still correct. 387 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 388 ISD::AssertZext : ISD::AssertSext, 389 NVT, Res, DAG.getValueType(N->getValueType(0))); 390} 391 392SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 393 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 394 395 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 396 SDValue Res = GetPromotedInteger(N->getOperand(0)); 397 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 398 399 // If the result and operand types are the same after promotion, simplify 400 // to an in-register extension. 401 if (NVT == Res.getValueType()) { 402 // The high bits are not guaranteed to be anything. Insert an extend. 403 if (N->getOpcode() == ISD::SIGN_EXTEND) 404 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 405 DAG.getValueType(N->getOperand(0).getValueType())); 406 if (N->getOpcode() == ISD::ZERO_EXTEND) 407 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 408 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 409 return Res; 410 } 411 } 412 413 // Otherwise, just extend the original operand all the way to the larger type. 414 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 415} 416 417SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 418 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 419 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 420 ISD::LoadExtType ExtType = 421 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 422 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 423 N->getSrcValue(), N->getSrcValueOffset(), 424 N->getMemoryVT(), N->isVolatile(), 425 N->getAlignment()); 426 427 // Legalized the chain result - switch anything that used the old chain to 428 // use the new one. 429 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 430 return Res; 431} 432 433/// Promote the overflow flag of an overflowing arithmetic node. 434SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 435 // Simply change the return type of the boolean result. 436 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); 437 MVT ValueVTs[] = { N->getValueType(0), NVT }; 438 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 439 SDValue Res = DAG.getNode(N->getOpcode(), DAG.getVTList(ValueVTs, 2), Ops, 2); 440 441 // Modified the sum result - switch anything that used the old sum to use 442 // the new one. 443 ReplaceValueWith(SDValue(N, 0), Res); 444 445 return SDValue(Res.getNode(), 1); 446} 447 448SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 449 if (ResNo == 1) 450 return PromoteIntRes_Overflow(N); 451 452 // The operation overflowed iff the result in the larger type is not the 453 // sign extension of its truncation to the original type. 454 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 455 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 456 MVT OVT = N->getOperand(0).getValueType(); 457 MVT NVT = LHS.getValueType(); 458 459 // Do the arithmetic in the larger type. 460 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 461 SDValue Res = DAG.getNode(Opcode, NVT, LHS, RHS); 462 463 // Calculate the overflow flag: sign extend the arithmetic result from 464 // the original type. 465 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 466 DAG.getValueType(OVT)); 467 // Overflowed if and only if this is not equal to Res. 468 Ofl = DAG.getSetCC(N->getValueType(1), Ofl, Res, ISD::SETNE); 469 470 // Use the calculated overflow everywhere. 471 ReplaceValueWith(SDValue(N, 1), Ofl); 472 473 return Res; 474} 475 476SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 477 // Sign extend the input. 478 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 479 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 480 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 481} 482 483SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 484 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 485 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 486 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 487} 488 489SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 490 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 491 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 492 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 493 N->getOperand(1), LHS, RHS, N->getOperand(4)); 494} 495 496SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 497 MVT SVT = TLI.getSetCCResultType(N->getOperand(0)); 498 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 499 500 // Get the SETCC result using the canonical SETCC type. 501 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0), 502 N->getOperand(1), N->getOperand(2)); 503 504 // Convert to the expected type. 505 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 506 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 507 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC); 508} 509 510SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 511 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 512 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 513} 514 515SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 516 SDValue Op = GetPromotedInteger(N->getOperand(0)); 517 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 518 N->getOperand(1)); 519} 520 521SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 522 // The input may have strange things in the top bits of the registers, but 523 // these operations don't care. They may have weird bits going out, but 524 // that too is okay if they are integer operations. 525 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 526 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 527 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 528} 529 530SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 531 // The input value must be properly sign extended. 532 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 533 return DAG.getNode(ISD::SRA, Res.getValueType(), Res, N->getOperand(1)); 534} 535 536SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 537 // The input value must be properly zero extended. 538 MVT VT = N->getValueType(0); 539 MVT NVT = TLI.getTypeToTransformTo(VT); 540 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 541 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 542} 543 544SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 545 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 546 SDValue Res; 547 548 switch (getTypeAction(N->getOperand(0).getValueType())) { 549 default: assert(0 && "Unknown type action!"); 550 case Legal: 551 case ExpandInteger: 552 Res = N->getOperand(0); 553 break; 554 case PromoteInteger: 555 Res = GetPromotedInteger(N->getOperand(0)); 556 break; 557 } 558 559 // Truncate to NVT instead of VT 560 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 561} 562 563SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 564 if (ResNo == 1) 565 return PromoteIntRes_Overflow(N); 566 567 // The operation overflowed iff the result in the larger type is not the 568 // zero extension of its truncation to the original type. 569 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 570 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 571 MVT OVT = N->getOperand(0).getValueType(); 572 MVT NVT = LHS.getValueType(); 573 574 // Do the arithmetic in the larger type. 575 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 576 SDValue Res = DAG.getNode(Opcode, NVT, LHS, RHS); 577 578 // Calculate the overflow flag: zero extend the arithmetic result from 579 // the original type. 580 SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT); 581 // Overflowed if and only if this is not equal to Res. 582 Ofl = DAG.getSetCC(N->getValueType(1), Ofl, Res, ISD::SETNE); 583 584 // Use the calculated overflow everywhere. 585 ReplaceValueWith(SDValue(N, 1), Ofl); 586 587 return Res; 588} 589 590SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 591 // Zero extend the input. 592 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 593 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 594 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 595} 596 597SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 598 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 599} 600 601SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 602 SDValue Chain = N->getOperand(0); // Get the chain. 603 SDValue Ptr = N->getOperand(1); // Get the pointer. 604 MVT VT = N->getValueType(0); 605 606 MVT RegVT = TLI.getRegisterType(VT); 607 unsigned NumRegs = TLI.getNumRegisters(VT); 608 // The argument is passed as NumRegs registers of type RegVT. 609 610 SmallVector<SDValue, 8> Parts(NumRegs); 611 for (unsigned i = 0; i < NumRegs; ++i) { 612 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); 613 Chain = Parts[i].getValue(1); 614 } 615 616 // Handle endianness of the load. 617 if (TLI.isBigEndian()) 618 std::reverse(Parts.begin(), Parts.end()); 619 620 // Assemble the parts in the promoted type. 621 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 622 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]); 623 for (unsigned i = 1; i < NumRegs; ++i) { 624 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]); 625 // Shift it to the right position and "or" it in. 626 Part = DAG.getNode(ISD::SHL, NVT, Part, 627 DAG.getConstant(i * RegVT.getSizeInBits(), 628 TLI.getShiftAmountTy())); 629 Res = DAG.getNode(ISD::OR, NVT, Res, Part); 630 } 631 632 // Modified the chain result - switch anything that used the old chain to 633 // use the new one. 634 ReplaceValueWith(SDValue(N, 1), Chain); 635 636 return Res; 637} 638 639SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 640 assert(ResNo == 1 && "Only boolean result promotion currently supported!"); 641 return PromoteIntRes_Overflow(N); 642} 643 644//===----------------------------------------------------------------------===// 645// Integer Operand Promotion 646//===----------------------------------------------------------------------===// 647 648/// PromoteIntegerOperand - This method is called when the specified operand of 649/// the specified node is found to need promotion. At this point, all of the 650/// result types of the node are known to be legal, but other operands of the 651/// node may need promotion or expansion as well as the specified one. 652bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 653 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 654 SDValue Res = SDValue(); 655 656 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 657 == TargetLowering::Custom) 658 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 659 660 if (Res.getNode() == 0) { 661 switch (N->getOpcode()) { 662 default: 663 #ifndef NDEBUG 664 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 665 N->dump(&DAG); cerr << "\n"; 666 #endif 667 assert(0 && "Do not know how to promote this operator's operand!"); 668 abort(); 669 670 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 671 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 672 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 673 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 674 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 675 case ISD::CONVERT_RNDSAT: 676 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 677 case ISD::INSERT_VECTOR_ELT: 678 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 679 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 680 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 681 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 682 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 683 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 684 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 685 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 686 OpNo); break; 687 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 688 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 689 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 690 } 691 } 692 693 // If the result is null, the sub-method took care of registering results etc. 694 if (!Res.getNode()) return false; 695 696 // If the result is N, the sub-method updated N in place. Tell the legalizer 697 // core about this. 698 if (Res.getNode() == N) 699 return true; 700 701 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 702 "Invalid operand expansion"); 703 704 ReplaceValueWith(SDValue(N, 0), Res); 705 return false; 706} 707 708/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 709/// shared among BR_CC, SELECT_CC, and SETCC handlers. 710void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 711 ISD::CondCode CCCode) { 712 // We have to insert explicit sign or zero extends. Note that we could 713 // insert sign extends for ALL conditions, but zero extend is cheaper on 714 // many machines (an AND instead of two shifts), so prefer it. 715 switch (CCCode) { 716 default: assert(0 && "Unknown integer comparison!"); 717 case ISD::SETEQ: 718 case ISD::SETNE: 719 case ISD::SETUGE: 720 case ISD::SETUGT: 721 case ISD::SETULE: 722 case ISD::SETULT: 723 // ALL of these operations will work if we either sign or zero extend 724 // the operands (including the unsigned comparisons!). Zero extend is 725 // usually a simpler/cheaper operation, so prefer it. 726 NewLHS = ZExtPromotedInteger(NewLHS); 727 NewRHS = ZExtPromotedInteger(NewRHS); 728 break; 729 case ISD::SETGE: 730 case ISD::SETGT: 731 case ISD::SETLT: 732 case ISD::SETLE: 733 NewLHS = SExtPromotedInteger(NewLHS); 734 NewRHS = SExtPromotedInteger(NewRHS); 735 break; 736 } 737} 738 739SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 740 SDValue Op = GetPromotedInteger(N->getOperand(0)); 741 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 742} 743 744SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 745 assert(OpNo == 2 && "Don't know how to promote this operand!"); 746 747 SDValue LHS = N->getOperand(2); 748 SDValue RHS = N->getOperand(3); 749 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 750 751 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 752 // legal types. 753 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 754 N->getOperand(1), LHS, RHS, N->getOperand(4)); 755} 756 757SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 758 assert(OpNo == 1 && "only know how to promote condition"); 759 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 760 761 // Make sure the extra bits coming from type promotion conform to 762 // getBooleanContents. 763 unsigned CondBits = Cond.getValueSizeInBits(); 764 switch (TLI.getBooleanContents()) { 765 default: 766 assert(false && "Unknown BooleanContent!"); 767 case TargetLowering::UndefinedBooleanContent: 768 // The promoted value, which may contain rubbish in the upper bits, is fine. 769 break; 770 case TargetLowering::ZeroOrOneBooleanContent: 771 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 772 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 773 break; 774 case TargetLowering::ZeroOrNegativeOneBooleanContent: 775 if (DAG.ComputeNumSignBits(Cond) != CondBits) 776 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond, 777 DAG.getValueType(MVT::i1)); 778 break; 779 } 780 781 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 782 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 783 N->getOperand(2)); 784} 785 786SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 787 // Since the result type is legal, the operands must promote to it. 788 MVT OVT = N->getOperand(0).getValueType(); 789 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 790 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 791 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 792 793 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 794 DAG.getConstant(OVT.getSizeInBits(), 795 TLI.getShiftAmountTy())); 796 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 797} 798 799SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 800 // The vector type is legal but the element type is not. This implies 801 // that the vector is a power-of-two in length and that the element 802 // type does not have a strange size (eg: it is not i1). 803 MVT VecVT = N->getValueType(0); 804 unsigned NumElts = VecVT.getVectorNumElements(); 805 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 806 807 // Build a vector of half the length out of elements of twice the bitwidth. 808 // For example <4 x i16> -> <2 x i32>. 809 MVT OldVT = N->getOperand(0).getValueType(); 810 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 811 assert(OldVT.isSimple() && NewVT.isSimple()); 812 813 std::vector<SDValue> NewElts; 814 NewElts.reserve(NumElts/2); 815 816 for (unsigned i = 0; i < NumElts; i += 2) { 817 // Combine two successive elements into one promoted element. 818 SDValue Lo = N->getOperand(i); 819 SDValue Hi = N->getOperand(i+1); 820 if (TLI.isBigEndian()) 821 std::swap(Lo, Hi); 822 NewElts.push_back(JoinIntegers(Lo, Hi)); 823 } 824 825 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, 826 MVT::getVectorVT(NewVT, NewElts.size()), 827 &NewElts[0], NewElts.size()); 828 829 // Convert the new vector to the old vector type. 830 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 831} 832 833SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 834 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 835 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 836 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 837 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 838 "can only promote integer arguments"); 839 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 840 return DAG.getConvertRndSat(N->getValueType(0), InOp, 841 N->getOperand(1), N->getOperand(2), 842 N->getOperand(3), N->getOperand(4), CvtCode); 843} 844 845SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 846 unsigned OpNo) { 847 if (OpNo == 1) { 848 // Promote the inserted value. This is valid because the type does not 849 // have to match the vector element type. 850 851 // Check that any extra bits introduced will be truncated away. 852 assert(N->getOperand(1).getValueType().getSizeInBits() >= 853 N->getValueType(0).getVectorElementType().getSizeInBits() && 854 "Type of inserted value narrower than vector element type!"); 855 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 856 GetPromotedInteger(N->getOperand(1)), 857 N->getOperand(2)); 858 } 859 860 assert(OpNo == 2 && "Different operand and result vector types?"); 861 862 // Promote the index. 863 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 864 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 865 N->getOperand(1), Idx); 866} 867 868SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 869 SDValue NewOps[6]; 870 NewOps[0] = N->getOperand(0); 871 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 872 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 873 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 874 } 875 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 876 array_lengthof(NewOps)); 877} 878 879SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 880 assert(OpNo == 0 && "Only know how to promote condition"); 881 SDValue Cond = GetPromotedInteger(N->getOperand(0)); 882 883 // Promote all the way up to SVT, the canonical SetCC type. 884 // FIXME: Not clear what value to pass to getSetCCResultType. 885 // [This only matters for CellSPU since all other targets 886 // ignore the argument.] We used to pass Cond, resulting in 887 // SVT = MVT::i8, but CellSPU has no select patterns for i8, 888 // causing an abort later. Passing the result type works 889 // around the problem. 890 MVT SVT = TLI.getSetCCResultType(N->getOperand(1)); 891 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 892 assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!"); 893 894 // Make sure the extra bits conform to getBooleanContents. There are 895 // two sets of extra bits: those in Cond, which come from type promotion, 896 // and those we need to add to have the final type be SVT (for most targets 897 // this last set of bits is empty). 898 unsigned CondBits = Cond.getValueSizeInBits(); 899 ISD::NodeType ExtendCode; 900 switch (TLI.getBooleanContents()) { 901 default: 902 assert(false && "Unknown BooleanContent!"); 903 case TargetLowering::UndefinedBooleanContent: 904 // Extend to SVT by adding rubbish. 905 ExtendCode = ISD::ANY_EXTEND; 906 break; 907 case TargetLowering::ZeroOrOneBooleanContent: 908 ExtendCode = ISD::ZERO_EXTEND; 909 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 910 // All extra bits need to be cleared. Do this by zero extending the 911 // original condition value all the way to SVT. 912 Cond = N->getOperand(0); 913 break; 914 case TargetLowering::ZeroOrNegativeOneBooleanContent: { 915 ExtendCode = ISD::SIGN_EXTEND; 916 unsigned SignBits = DAG.ComputeNumSignBits(Cond); 917 if (SignBits != CondBits) 918 // All extra bits need to be sign extended. Do this by sign extending the 919 // original condition value all the way to SVT. 920 Cond = N->getOperand(0); 921 break; 922 } 923 } 924 Cond = DAG.getNode(ExtendCode, SVT, Cond); 925 926 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 927 N->getOperand(1), N->getOperand(2)); 928} 929 930SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 931 assert(OpNo == 0 && "Don't know how to promote this operand!"); 932 933 SDValue LHS = N->getOperand(0); 934 SDValue RHS = N->getOperand(1); 935 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 936 937 // The CC (#4) and the possible return values (#2 and #3) have legal types. 938 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 939 N->getOperand(3), N->getOperand(4)); 940} 941 942SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 943 assert(OpNo == 0 && "Don't know how to promote this operand!"); 944 945 SDValue LHS = N->getOperand(0); 946 SDValue RHS = N->getOperand(1); 947 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 948 949 // The CC (#2) is always legal. 950 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 951} 952 953SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 954 SDValue Op = GetPromotedInteger(N->getOperand(0)); 955 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 956 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 957 Op, DAG.getValueType(N->getOperand(0).getValueType())); 958} 959 960SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 961 return DAG.UpdateNodeOperands(SDValue(N, 0), 962 SExtPromotedInteger(N->getOperand(0))); 963} 964 965SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 966 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 967 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 968 int SVOffset = N->getSrcValueOffset(); 969 unsigned Alignment = N->getAlignment(); 970 bool isVolatile = N->isVolatile(); 971 972 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 973 974 // Truncate the value and store the result. 975 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 976 SVOffset, N->getMemoryVT(), 977 isVolatile, Alignment); 978} 979 980SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 981 SDValue Op = GetPromotedInteger(N->getOperand(0)); 982 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 983} 984 985SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 986 return DAG.UpdateNodeOperands(SDValue(N, 0), 987 ZExtPromotedInteger(N->getOperand(0))); 988} 989 990SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 991 SDValue Op = GetPromotedInteger(N->getOperand(0)); 992 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 993 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 994} 995 996 997//===----------------------------------------------------------------------===// 998// Integer Result Expansion 999//===----------------------------------------------------------------------===// 1000 1001/// ExpandIntegerResult - This method is called when the specified result of the 1002/// specified node is found to need expansion. At this point, the node may also 1003/// have invalid operands or may have other results that need promotion, we just 1004/// know that (at least) one result needs expansion. 1005void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 1006 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 1007 SDValue Lo, Hi; 1008 Lo = Hi = SDValue(); 1009 1010 // See if the target wants to custom expand this node. 1011 if (CustomLowerResults(N, ResNo)) 1012 return; 1013 1014 switch (N->getOpcode()) { 1015 default: 1016#ifndef NDEBUG 1017 cerr << "ExpandIntegerResult #" << ResNo << ": "; 1018 N->dump(&DAG); cerr << "\n"; 1019#endif 1020 assert(0 && "Do not know how to expand the result of this operator!"); 1021 abort(); 1022 1023 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 1024 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 1025 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1026 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 1027 1028 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 1029 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 1030 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 1031 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 1032 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 1033 1034 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 1035 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 1036 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 1037 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 1038 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1039 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1040 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1041 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1042 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1043 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1044 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1045 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1046 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1047 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1048 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1049 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1050 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1051 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1052 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1053 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1054 1055 case ISD::AND: 1056 case ISD::OR: 1057 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1058 1059 case ISD::ADD: 1060 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1061 1062 case ISD::ADDC: 1063 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1064 1065 case ISD::ADDE: 1066 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1067 1068 case ISD::SHL: 1069 case ISD::SRA: 1070 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1071 } 1072 1073 // If Lo/Hi is null, the sub-method took care of registering results etc. 1074 if (Lo.getNode()) 1075 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1076} 1077 1078/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1079/// and the shift amount is a constant 'Amt'. Expand the operation. 1080void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1081 SDValue &Lo, SDValue &Hi) { 1082 // Expand the incoming operand to be shifted, so that we have its parts 1083 SDValue InL, InH; 1084 GetExpandedInteger(N->getOperand(0), InL, InH); 1085 1086 MVT NVT = InL.getValueType(); 1087 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1088 unsigned NVTBits = NVT.getSizeInBits(); 1089 MVT ShTy = N->getOperand(1).getValueType(); 1090 1091 if (N->getOpcode() == ISD::SHL) { 1092 if (Amt > VTBits) { 1093 Lo = Hi = DAG.getConstant(0, NVT); 1094 } else if (Amt > NVTBits) { 1095 Lo = DAG.getConstant(0, NVT); 1096 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1097 } else if (Amt == NVTBits) { 1098 Lo = DAG.getConstant(0, NVT); 1099 Hi = InL; 1100 } else if (Amt == 1 && 1101 TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) { 1102 // Emit this X << 1 as X+X. 1103 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1104 SDValue LoOps[2] = { InL, InL }; 1105 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1106 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1107 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1108 } else { 1109 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1110 Hi = DAG.getNode(ISD::OR, NVT, 1111 DAG.getNode(ISD::SHL, NVT, InH, 1112 DAG.getConstant(Amt, ShTy)), 1113 DAG.getNode(ISD::SRL, NVT, InL, 1114 DAG.getConstant(NVTBits-Amt, ShTy))); 1115 } 1116 return; 1117 } 1118 1119 if (N->getOpcode() == ISD::SRL) { 1120 if (Amt > VTBits) { 1121 Lo = DAG.getConstant(0, NVT); 1122 Hi = DAG.getConstant(0, NVT); 1123 } else if (Amt > NVTBits) { 1124 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1125 Hi = DAG.getConstant(0, NVT); 1126 } else if (Amt == NVTBits) { 1127 Lo = InH; 1128 Hi = DAG.getConstant(0, NVT); 1129 } else { 1130 Lo = DAG.getNode(ISD::OR, NVT, 1131 DAG.getNode(ISD::SRL, NVT, InL, 1132 DAG.getConstant(Amt, ShTy)), 1133 DAG.getNode(ISD::SHL, NVT, InH, 1134 DAG.getConstant(NVTBits-Amt, ShTy))); 1135 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1136 } 1137 return; 1138 } 1139 1140 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1141 if (Amt > VTBits) { 1142 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1143 DAG.getConstant(NVTBits-1, ShTy)); 1144 } else if (Amt > NVTBits) { 1145 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1146 DAG.getConstant(Amt-NVTBits, ShTy)); 1147 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1148 DAG.getConstant(NVTBits-1, ShTy)); 1149 } else if (Amt == NVTBits) { 1150 Lo = InH; 1151 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1152 DAG.getConstant(NVTBits-1, ShTy)); 1153 } else { 1154 Lo = DAG.getNode(ISD::OR, NVT, 1155 DAG.getNode(ISD::SRL, NVT, InL, 1156 DAG.getConstant(Amt, ShTy)), 1157 DAG.getNode(ISD::SHL, NVT, InH, 1158 DAG.getConstant(NVTBits-Amt, ShTy))); 1159 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 1160 } 1161} 1162 1163/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1164/// this shift based on knowledge of the high bit of the shift amount. If we 1165/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1166/// shift amount. 1167bool DAGTypeLegalizer:: 1168ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1169 SDValue Amt = N->getOperand(1); 1170 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1171 MVT ShTy = Amt.getValueType(); 1172 unsigned ShBits = ShTy.getSizeInBits(); 1173 unsigned NVTBits = NVT.getSizeInBits(); 1174 assert(isPowerOf2_32(NVTBits) && 1175 "Expanded integer type size not a power of two!"); 1176 1177 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1178 APInt KnownZero, KnownOne; 1179 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1180 1181 // If we don't know anything about the high bits, exit. 1182 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1183 return false; 1184 1185 // Get the incoming operand to be shifted. 1186 SDValue InL, InH; 1187 GetExpandedInteger(N->getOperand(0), InL, InH); 1188 1189 // If we know that any of the high bits of the shift amount are one, then we 1190 // can do this as a couple of simple shifts. 1191 if (KnownOne.intersects(HighBitMask)) { 1192 // Mask out the high bit, which we know is set. 1193 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1194 DAG.getConstant(~HighBitMask, ShTy)); 1195 1196 switch (N->getOpcode()) { 1197 default: assert(0 && "Unknown shift"); 1198 case ISD::SHL: 1199 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1200 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1201 return true; 1202 case ISD::SRL: 1203 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1204 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1205 return true; 1206 case ISD::SRA: 1207 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1208 DAG.getConstant(NVTBits-1, ShTy)); 1209 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1210 return true; 1211 } 1212 } 1213 1214#if 0 1215 // FIXME: This code is broken for shifts with a zero amount! 1216 // If we know that all of the high bits of the shift amount are zero, then we 1217 // can do this as a couple of simple shifts. 1218 if ((KnownZero & HighBitMask) == HighBitMask) { 1219 // Compute 32-amt. 1220 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1221 DAG.getConstant(NVTBits, ShTy), 1222 Amt); 1223 unsigned Op1, Op2; 1224 switch (N->getOpcode()) { 1225 default: assert(0 && "Unknown shift"); 1226 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1227 case ISD::SRL: 1228 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1229 } 1230 1231 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1232 Hi = DAG.getNode(ISD::OR, NVT, 1233 DAG.getNode(Op1, NVT, InH, Amt), 1234 DAG.getNode(Op2, NVT, InL, Amt2)); 1235 return true; 1236 } 1237#endif 1238 1239 return false; 1240} 1241 1242void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1243 SDValue &Lo, SDValue &Hi) { 1244 // Expand the subcomponents. 1245 SDValue LHSL, LHSH, RHSL, RHSH; 1246 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1247 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1248 1249 MVT NVT = LHSL.getValueType(); 1250 SDValue LoOps[2] = { LHSL, RHSL }; 1251 SDValue HiOps[3] = { LHSH, RHSH }; 1252 1253 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1254 // them. TODO: Teach operation legalization how to expand unsupported 1255 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1256 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1257 // generate a value of this type in the expanded code sequence. 1258 bool hasCarry = 1259 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC, 1260 TLI.getTypeToExpandTo(NVT)); 1261 1262 if (hasCarry) { 1263 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1264 if (N->getOpcode() == ISD::ADD) { 1265 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1266 HiOps[2] = Lo.getValue(1); 1267 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1268 } else { 1269 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1270 HiOps[2] = Lo.getValue(1); 1271 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1272 } 1273 } else { 1274 if (N->getOpcode() == ISD::ADD) { 1275 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); 1276 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); 1277 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0], 1278 ISD::SETULT); 1279 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 1280 DAG.getConstant(1, NVT), 1281 DAG.getConstant(0, NVT)); 1282 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1], 1283 ISD::SETULT); 1284 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 1285 DAG.getConstant(1, NVT), Carry1); 1286 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 1287 } else { 1288 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); 1289 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); 1290 SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]), 1291 LoOps[0], LoOps[1], ISD::SETULT); 1292 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 1293 DAG.getConstant(1, NVT), 1294 DAG.getConstant(0, NVT)); 1295 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 1296 } 1297 } 1298} 1299 1300void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1301 SDValue &Lo, SDValue &Hi) { 1302 // Expand the subcomponents. 1303 SDValue LHSL, LHSH, RHSL, RHSH; 1304 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1305 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1306 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1307 SDValue LoOps[2] = { LHSL, RHSL }; 1308 SDValue HiOps[3] = { LHSH, RHSH }; 1309 1310 if (N->getOpcode() == ISD::ADDC) { 1311 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1312 HiOps[2] = Lo.getValue(1); 1313 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1314 } else { 1315 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1316 HiOps[2] = Lo.getValue(1); 1317 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1318 } 1319 1320 // Legalized the flag result - switch anything that used the old flag to 1321 // use the new one. 1322 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1323} 1324 1325void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1326 SDValue &Lo, SDValue &Hi) { 1327 // Expand the subcomponents. 1328 SDValue LHSL, LHSH, RHSL, RHSH; 1329 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1330 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1331 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1332 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1333 SDValue HiOps[3] = { LHSH, RHSH }; 1334 1335 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1336 HiOps[2] = Lo.getValue(1); 1337 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1338 1339 // Legalized the flag result - switch anything that used the old flag to 1340 // use the new one. 1341 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1342} 1343 1344void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1345 SDValue &Lo, SDValue &Hi) { 1346 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1347 SDValue Op = N->getOperand(0); 1348 if (Op.getValueType().bitsLE(NVT)) { 1349 // The low part is any extension of the input (which degenerates to a copy). 1350 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 1351 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 1352 } else { 1353 // For example, extension of an i48 to an i64. The operand type necessarily 1354 // promotes to the result type, so will end up being expanded too. 1355 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1356 "Only know how to promote this result!"); 1357 SDValue Res = GetPromotedInteger(Op); 1358 assert(Res.getValueType() == N->getValueType(0) && 1359 "Operand over promoted?"); 1360 // Split the promoted operand. This will simplify when it is expanded. 1361 SplitInteger(Res, Lo, Hi); 1362 } 1363} 1364 1365void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1366 SDValue &Lo, SDValue &Hi) { 1367 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1368 MVT NVT = Lo.getValueType(); 1369 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1370 unsigned NVTBits = NVT.getSizeInBits(); 1371 unsigned EVTBits = EVT.getSizeInBits(); 1372 1373 if (NVTBits < EVTBits) { 1374 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi, 1375 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1376 } else { 1377 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT)); 1378 // The high part replicates the sign bit of Lo, make it explicit. 1379 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1380 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); 1381 } 1382} 1383 1384void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1385 SDValue &Lo, SDValue &Hi) { 1386 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1387 MVT NVT = Lo.getValueType(); 1388 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1389 unsigned NVTBits = NVT.getSizeInBits(); 1390 unsigned EVTBits = EVT.getSizeInBits(); 1391 1392 if (NVTBits < EVTBits) { 1393 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 1394 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1395 } else { 1396 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 1397 // The high part must be zero, make it explicit. 1398 Hi = DAG.getConstant(0, NVT); 1399 } 1400} 1401 1402void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1403 SDValue &Lo, SDValue &Hi) { 1404 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1405 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1406 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1407} 1408 1409void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1410 SDValue &Lo, SDValue &Hi) { 1411 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1412 unsigned NBitWidth = NVT.getSizeInBits(); 1413 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1414 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1415 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1416} 1417 1418void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1419 SDValue &Lo, SDValue &Hi) { 1420 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1421 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1422 MVT NVT = Lo.getValueType(); 1423 1424 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1425 DAG.getConstant(0, NVT), ISD::SETNE); 1426 1427 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1428 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1429 1430 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1431 DAG.getNode(ISD::ADD, NVT, LoLZ, 1432 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1433 Hi = DAG.getConstant(0, NVT); 1434} 1435 1436void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1437 SDValue &Lo, SDValue &Hi) { 1438 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1439 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1440 MVT NVT = Lo.getValueType(); 1441 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1442 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1443 Hi = DAG.getConstant(0, NVT); 1444} 1445 1446void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1447 SDValue &Lo, SDValue &Hi) { 1448 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1449 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1450 MVT NVT = Lo.getValueType(); 1451 1452 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1453 DAG.getConstant(0, NVT), ISD::SETNE); 1454 1455 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1456 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1457 1458 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1459 DAG.getNode(ISD::ADD, NVT, HiLZ, 1460 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1461 Hi = DAG.getConstant(0, NVT); 1462} 1463 1464void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1465 SDValue &Hi) { 1466 MVT VT = N->getValueType(0); 1467 SDValue Op = N->getOperand(0); 1468 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1469 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1470 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1471} 1472 1473void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1474 SDValue &Hi) { 1475 MVT VT = N->getValueType(0); 1476 SDValue Op = N->getOperand(0); 1477 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1478 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1479 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1480} 1481 1482void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1483 SDValue &Lo, SDValue &Hi) { 1484 if (ISD::isNormalLoad(N)) { 1485 ExpandRes_NormalLoad(N, Lo, Hi); 1486 return; 1487 } 1488 1489 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1490 1491 MVT VT = N->getValueType(0); 1492 MVT NVT = TLI.getTypeToTransformTo(VT); 1493 SDValue Ch = N->getChain(); 1494 SDValue Ptr = N->getBasePtr(); 1495 ISD::LoadExtType ExtType = N->getExtensionType(); 1496 int SVOffset = N->getSrcValueOffset(); 1497 unsigned Alignment = N->getAlignment(); 1498 bool isVolatile = N->isVolatile(); 1499 1500 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1501 1502 if (N->getMemoryVT().bitsLE(NVT)) { 1503 MVT EVT = N->getMemoryVT(); 1504 1505 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1506 isVolatile, Alignment); 1507 1508 // Remember the chain. 1509 Ch = Lo.getValue(1); 1510 1511 if (ExtType == ISD::SEXTLOAD) { 1512 // The high part is obtained by SRA'ing all but one of the bits of the 1513 // lo part. 1514 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1515 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1516 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1517 } else if (ExtType == ISD::ZEXTLOAD) { 1518 // The high part is just a zero. 1519 Hi = DAG.getConstant(0, NVT); 1520 } else { 1521 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1522 // The high part is undefined. 1523 Hi = DAG.getNode(ISD::UNDEF, NVT); 1524 } 1525 } else if (TLI.isLittleEndian()) { 1526 // Little-endian - low bits are at low addresses. 1527 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1528 isVolatile, Alignment); 1529 1530 unsigned ExcessBits = 1531 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1532 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1533 1534 // Increment the pointer to the other half. 1535 unsigned IncrementSize = NVT.getSizeInBits()/8; 1536 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1537 DAG.getIntPtrConstant(IncrementSize)); 1538 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1539 SVOffset+IncrementSize, NEVT, 1540 isVolatile, MinAlign(Alignment, IncrementSize)); 1541 1542 // Build a factor node to remember that this load is independent of the 1543 // other one. 1544 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1545 Hi.getValue(1)); 1546 } else { 1547 // Big-endian - high bits are at low addresses. Favor aligned loads at 1548 // the cost of some bit-fiddling. 1549 MVT EVT = N->getMemoryVT(); 1550 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1551 unsigned IncrementSize = NVT.getSizeInBits()/8; 1552 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1553 1554 // Load both the high bits and maybe some of the low bits. 1555 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1556 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1557 isVolatile, Alignment); 1558 1559 // Increment the pointer to the other half. 1560 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1561 DAG.getIntPtrConstant(IncrementSize)); 1562 // Load the rest of the low bits. 1563 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1564 SVOffset+IncrementSize, 1565 MVT::getIntegerVT(ExcessBits), 1566 isVolatile, MinAlign(Alignment, IncrementSize)); 1567 1568 // Build a factor node to remember that this load is independent of the 1569 // other one. 1570 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1571 Hi.getValue(1)); 1572 1573 if (ExcessBits < NVT.getSizeInBits()) { 1574 // Transfer low bits from the bottom of Hi to the top of Lo. 1575 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1576 DAG.getNode(ISD::SHL, NVT, Hi, 1577 DAG.getConstant(ExcessBits, 1578 TLI.getShiftAmountTy()))); 1579 // Move high bits to the right position in Hi. 1580 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1581 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1582 TLI.getShiftAmountTy())); 1583 } 1584 } 1585 1586 // Legalized the chain result - switch anything that used the old chain to 1587 // use the new one. 1588 ReplaceValueWith(SDValue(N, 1), Ch); 1589} 1590 1591void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1592 SDValue &Lo, SDValue &Hi) { 1593 SDValue LL, LH, RL, RH; 1594 GetExpandedInteger(N->getOperand(0), LL, LH); 1595 GetExpandedInteger(N->getOperand(1), RL, RH); 1596 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1597 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1598} 1599 1600void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1601 SDValue &Lo, SDValue &Hi) { 1602 MVT VT = N->getValueType(0); 1603 MVT NVT = TLI.getTypeToTransformTo(VT); 1604 1605 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1606 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1607 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1608 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1609 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1610 SDValue LL, LH, RL, RH; 1611 GetExpandedInteger(N->getOperand(0), LL, LH); 1612 GetExpandedInteger(N->getOperand(1), RL, RH); 1613 unsigned OuterBitSize = VT.getSizeInBits(); 1614 unsigned InnerBitSize = NVT.getSizeInBits(); 1615 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1616 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1617 1618 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1619 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1620 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1621 // The inputs are both zero-extended. 1622 if (HasUMUL_LOHI) { 1623 // We can emit a umul_lohi. 1624 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1625 Hi = SDValue(Lo.getNode(), 1); 1626 return; 1627 } 1628 if (HasMULHU) { 1629 // We can emit a mulhu+mul. 1630 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1631 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1632 return; 1633 } 1634 } 1635 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1636 // The input values are both sign-extended. 1637 if (HasSMUL_LOHI) { 1638 // We can emit a smul_lohi. 1639 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1640 Hi = SDValue(Lo.getNode(), 1); 1641 return; 1642 } 1643 if (HasMULHS) { 1644 // We can emit a mulhs+mul. 1645 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1646 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1647 return; 1648 } 1649 } 1650 if (HasUMUL_LOHI) { 1651 // Lo,Hi = umul LHS, RHS. 1652 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1653 DAG.getVTList(NVT, NVT), LL, RL); 1654 Lo = UMulLOHI; 1655 Hi = UMulLOHI.getValue(1); 1656 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1657 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1658 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1659 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1660 return; 1661 } 1662 if (HasMULHU) { 1663 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1664 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1665 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1666 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1667 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1668 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1669 return; 1670 } 1671 } 1672 1673 // If nothing else, we can make a libcall. 1674 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1675 if (VT == MVT::i32) 1676 LC = RTLIB::MUL_I32; 1677 else if (VT == MVT::i64) 1678 LC = RTLIB::MUL_I64; 1679 else if (VT == MVT::i128) 1680 LC = RTLIB::MUL_I128; 1681 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1682 1683 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1684 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1685} 1686 1687void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1688 SDValue &Lo, SDValue &Hi) { 1689 MVT VT = N->getValueType(0); 1690 1691 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1692 if (VT == MVT::i32) 1693 LC = RTLIB::SDIV_I32; 1694 else if (VT == MVT::i64) 1695 LC = RTLIB::SDIV_I64; 1696 else if (VT == MVT::i128) 1697 LC = RTLIB::SDIV_I128; 1698 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1699 1700 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1701 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1702} 1703 1704void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1705 SDValue &Lo, SDValue &Hi) { 1706 MVT VT = N->getValueType(0); 1707 1708 // If we can emit an efficient shift operation, do so now. Check to see if 1709 // the RHS is a constant. 1710 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1711 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1712 1713 // If we can determine that the high bit of the shift is zero or one, even if 1714 // the low bits are variable, emit this shift in an optimized form. 1715 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1716 return; 1717 1718 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1719 unsigned PartsOpc; 1720 if (N->getOpcode() == ISD::SHL) { 1721 PartsOpc = ISD::SHL_PARTS; 1722 } else if (N->getOpcode() == ISD::SRL) { 1723 PartsOpc = ISD::SRL_PARTS; 1724 } else { 1725 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1726 PartsOpc = ISD::SRA_PARTS; 1727 } 1728 1729 // Next check to see if the target supports this SHL_PARTS operation or if it 1730 // will custom expand it. 1731 MVT NVT = TLI.getTypeToTransformTo(VT); 1732 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1733 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1734 Action == TargetLowering::Custom) { 1735 // Expand the subcomponents. 1736 SDValue LHSL, LHSH; 1737 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1738 1739 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1740 MVT VT = LHSL.getValueType(); 1741 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1742 Hi = Lo.getValue(1); 1743 return; 1744 } 1745 1746 // Otherwise, emit a libcall. 1747 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1748 bool isSigned; 1749 if (N->getOpcode() == ISD::SHL) { 1750 isSigned = false; /*sign irrelevant*/ 1751 if (VT == MVT::i32) 1752 LC = RTLIB::SHL_I32; 1753 else if (VT == MVT::i64) 1754 LC = RTLIB::SHL_I64; 1755 else if (VT == MVT::i128) 1756 LC = RTLIB::SHL_I128; 1757 } else if (N->getOpcode() == ISD::SRL) { 1758 isSigned = false; 1759 if (VT == MVT::i32) 1760 LC = RTLIB::SRL_I32; 1761 else if (VT == MVT::i64) 1762 LC = RTLIB::SRL_I64; 1763 else if (VT == MVT::i128) 1764 LC = RTLIB::SRL_I128; 1765 } else { 1766 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1767 isSigned = true; 1768 if (VT == MVT::i32) 1769 LC = RTLIB::SRA_I32; 1770 else if (VT == MVT::i64) 1771 LC = RTLIB::SRA_I64; 1772 else if (VT == MVT::i128) 1773 LC = RTLIB::SRA_I128; 1774 } 1775 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1776 1777 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1778 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1779} 1780 1781void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1782 SDValue &Lo, SDValue &Hi) { 1783 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1784 SDValue Op = N->getOperand(0); 1785 if (Op.getValueType().bitsLE(NVT)) { 1786 // The low part is sign extension of the input (degenerates to a copy). 1787 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 1788 // The high part is obtained by SRA'ing all but one of the bits of low part. 1789 unsigned LoSize = NVT.getSizeInBits(); 1790 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1791 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1792 } else { 1793 // For example, extension of an i48 to an i64. The operand type necessarily 1794 // promotes to the result type, so will end up being expanded too. 1795 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1796 "Only know how to promote this result!"); 1797 SDValue Res = GetPromotedInteger(Op); 1798 assert(Res.getValueType() == N->getValueType(0) && 1799 "Operand over promoted?"); 1800 // Split the promoted operand. This will simplify when it is expanded. 1801 SplitInteger(Res, Lo, Hi); 1802 unsigned ExcessBits = 1803 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1804 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1805 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1806 } 1807} 1808 1809void DAGTypeLegalizer:: 1810ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1811 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1812 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1813 1814 if (EVT.bitsLE(Lo.getValueType())) { 1815 // sext_inreg the low part if needed. 1816 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 1817 N->getOperand(1)); 1818 1819 // The high part gets the sign extension from the lo-part. This handles 1820 // things like sextinreg V:i64 from i8. 1821 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 1822 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1823 TLI.getShiftAmountTy())); 1824 } else { 1825 // For example, extension of an i48 to an i64. Leave the low part alone, 1826 // sext_inreg the high part. 1827 unsigned ExcessBits = 1828 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1829 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1830 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1831 } 1832} 1833 1834void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1835 SDValue &Lo, SDValue &Hi) { 1836 MVT VT = N->getValueType(0); 1837 1838 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1839 if (VT == MVT::i32) 1840 LC = RTLIB::SREM_I32; 1841 else if (VT == MVT::i64) 1842 LC = RTLIB::SREM_I64; 1843 else if (VT == MVT::i128) 1844 LC = RTLIB::SREM_I128; 1845 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1846 1847 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1848 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1849} 1850 1851void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1852 SDValue &Lo, SDValue &Hi) { 1853 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1854 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 1855 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 1856 DAG.getConstant(NVT.getSizeInBits(), 1857 TLI.getShiftAmountTy())); 1858 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 1859} 1860 1861void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1862 SDValue &Lo, SDValue &Hi) { 1863 MVT VT = N->getValueType(0); 1864 1865 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1866 if (VT == MVT::i32) 1867 LC = RTLIB::UDIV_I32; 1868 else if (VT == MVT::i64) 1869 LC = RTLIB::UDIV_I64; 1870 else if (VT == MVT::i128) 1871 LC = RTLIB::UDIV_I128; 1872 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1873 1874 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1875 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1876} 1877 1878void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1879 SDValue &Lo, SDValue &Hi) { 1880 MVT VT = N->getValueType(0); 1881 1882 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1883 if (VT == MVT::i32) 1884 LC = RTLIB::UREM_I32; 1885 else if (VT == MVT::i64) 1886 LC = RTLIB::UREM_I64; 1887 else if (VT == MVT::i128) 1888 LC = RTLIB::UREM_I128; 1889 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1890 1891 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1892 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1893} 1894 1895void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1896 SDValue &Lo, SDValue &Hi) { 1897 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1898 SDValue Op = N->getOperand(0); 1899 if (Op.getValueType().bitsLE(NVT)) { 1900 // The low part is zero extension of the input (degenerates to a copy). 1901 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 1902 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1903 } else { 1904 // For example, extension of an i48 to an i64. The operand type necessarily 1905 // promotes to the result type, so will end up being expanded too. 1906 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1907 "Only know how to promote this result!"); 1908 SDValue Res = GetPromotedInteger(Op); 1909 assert(Res.getValueType() == N->getValueType(0) && 1910 "Operand over promoted?"); 1911 // Split the promoted operand. This will simplify when it is expanded. 1912 SplitInteger(Res, Lo, Hi); 1913 unsigned ExcessBits = 1914 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1915 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1916 } 1917} 1918 1919 1920//===----------------------------------------------------------------------===// 1921// Integer Operand Expansion 1922//===----------------------------------------------------------------------===// 1923 1924/// ExpandIntegerOperand - This method is called when the specified operand of 1925/// the specified node is found to need expansion. At this point, all of the 1926/// result types of the node are known to be legal, but other operands of the 1927/// node may need promotion or expansion as well as the specified one. 1928bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1929 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1930 SDValue Res = SDValue(); 1931 1932 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1933 == TargetLowering::Custom) 1934 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 1935 1936 if (Res.getNode() == 0) { 1937 switch (N->getOpcode()) { 1938 default: 1939 #ifndef NDEBUG 1940 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1941 N->dump(&DAG); cerr << "\n"; 1942 #endif 1943 assert(0 && "Do not know how to expand this operator's operand!"); 1944 abort(); 1945 1946 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1947 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1948 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1949 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 1950 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 1951 1952 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1953 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1954 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1955 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1956 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1957 break; 1958 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1959 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1960 } 1961 } 1962 1963 // If the result is null, the sub-method took care of registering results etc. 1964 if (!Res.getNode()) return false; 1965 1966 // If the result is N, the sub-method updated N in place. Tell the legalizer 1967 // core about this. 1968 if (Res.getNode() == N) 1969 return true; 1970 1971 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1972 "Invalid operand expansion"); 1973 1974 ReplaceValueWith(SDValue(N, 0), Res); 1975 return false; 1976} 1977 1978/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1979/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1980void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1981 SDValue &NewRHS, 1982 ISD::CondCode &CCCode) { 1983 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1984 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1985 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1986 1987 MVT VT = NewLHS.getValueType(); 1988 1989 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1990 if (RHSLo == RHSHi) { 1991 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1992 if (RHSCST->isAllOnesValue()) { 1993 // Equality comparison to -1. 1994 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1995 NewRHS = RHSLo; 1996 return; 1997 } 1998 } 1999 } 2000 2001 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 2002 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 2003 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 2004 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2005 return; 2006 } 2007 2008 // If this is a comparison of the sign bit, just look at the top part. 2009 // X > -1, x < 0 2010 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2011 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2012 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2013 NewLHS = LHSHi; 2014 NewRHS = RHSHi; 2015 return; 2016 } 2017 2018 // FIXME: This generated code sucks. 2019 ISD::CondCode LowCC; 2020 switch (CCCode) { 2021 default: assert(0 && "Unknown integer setcc!"); 2022 case ISD::SETLT: 2023 case ISD::SETULT: LowCC = ISD::SETULT; break; 2024 case ISD::SETGT: 2025 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2026 case ISD::SETLE: 2027 case ISD::SETULE: LowCC = ISD::SETULE; break; 2028 case ISD::SETGE: 2029 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2030 } 2031 2032 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2033 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2034 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2035 2036 // NOTE: on targets without efficient SELECT of bools, we can always use 2037 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2038 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 2039 SDValue Tmp1, Tmp2; 2040 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 2041 false, DagCombineInfo); 2042 if (!Tmp1.getNode()) 2043 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 2044 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2045 CCCode, false, DagCombineInfo); 2046 if (!Tmp2.getNode()) 2047 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2048 DAG.getCondCode(CCCode)); 2049 2050 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2051 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2052 if ((Tmp1C && Tmp1C->isNullValue()) || 2053 (Tmp2C && Tmp2C->isNullValue() && 2054 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2055 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2056 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2057 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2058 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2059 // low part is known false, returns high part. 2060 // For LE / GE, if high part is known false, ignore the low part. 2061 // For LT / GT, if high part is known true, ignore the low part. 2062 NewLHS = Tmp2; 2063 NewRHS = SDValue(); 2064 return; 2065 } 2066 2067 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2068 ISD::SETEQ, false, DagCombineInfo); 2069 if (!NewLHS.getNode()) 2070 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2071 ISD::SETEQ); 2072 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 2073 NewLHS, Tmp1, Tmp2); 2074 NewRHS = SDValue(); 2075} 2076 2077SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2078 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2079 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2080 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2081 2082 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2083 // against zero to select between true and false values. 2084 if (NewRHS.getNode() == 0) { 2085 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2086 CCCode = ISD::SETNE; 2087 } 2088 2089 // Update N to have the operands specified. 2090 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2091 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2092 N->getOperand(4)); 2093} 2094 2095SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2096 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2097 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2098 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2099 2100 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2101 // against zero to select between true and false values. 2102 if (NewRHS.getNode() == 0) { 2103 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2104 CCCode = ISD::SETNE; 2105 } 2106 2107 // Update N to have the operands specified. 2108 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2109 N->getOperand(2), N->getOperand(3), 2110 DAG.getCondCode(CCCode)); 2111} 2112 2113SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2114 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2115 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2116 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2117 2118 // If ExpandSetCCOperands returned a scalar, use it. 2119 if (NewRHS.getNode() == 0) { 2120 assert(NewLHS.getValueType() == N->getValueType(0) && 2121 "Unexpected setcc expansion!"); 2122 return NewLHS; 2123 } 2124 2125 // Otherwise, update N to have the operands specified. 2126 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2127 DAG.getCondCode(CCCode)); 2128} 2129 2130SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2131 SDValue Op = N->getOperand(0); 2132 MVT DstVT = N->getValueType(0); 2133 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2134 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2135 "Don't know how to expand this SINT_TO_FP!"); 2136 return MakeLibCall(LC, DstVT, &Op, 1, true); 2137} 2138 2139SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2140 if (ISD::isNormalStore(N)) 2141 return ExpandOp_NormalStore(N, OpNo); 2142 2143 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2144 assert(OpNo == 1 && "Can only expand the stored value so far"); 2145 2146 MVT VT = N->getOperand(1).getValueType(); 2147 MVT NVT = TLI.getTypeToTransformTo(VT); 2148 SDValue Ch = N->getChain(); 2149 SDValue Ptr = N->getBasePtr(); 2150 int SVOffset = N->getSrcValueOffset(); 2151 unsigned Alignment = N->getAlignment(); 2152 bool isVolatile = N->isVolatile(); 2153 SDValue Lo, Hi; 2154 2155 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2156 2157 if (N->getMemoryVT().bitsLE(NVT)) { 2158 GetExpandedInteger(N->getValue(), Lo, Hi); 2159 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2160 N->getMemoryVT(), isVolatile, Alignment); 2161 } else if (TLI.isLittleEndian()) { 2162 // Little-endian - low bits are at low addresses. 2163 GetExpandedInteger(N->getValue(), Lo, Hi); 2164 2165 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2166 isVolatile, Alignment); 2167 2168 unsigned ExcessBits = 2169 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2170 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2171 2172 // Increment the pointer to the other half. 2173 unsigned IncrementSize = NVT.getSizeInBits()/8; 2174 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2175 DAG.getIntPtrConstant(IncrementSize)); 2176 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2177 SVOffset+IncrementSize, NEVT, 2178 isVolatile, MinAlign(Alignment, IncrementSize)); 2179 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2180 } else { 2181 // Big-endian - high bits are at low addresses. Favor aligned stores at 2182 // the cost of some bit-fiddling. 2183 GetExpandedInteger(N->getValue(), Lo, Hi); 2184 2185 MVT EVT = N->getMemoryVT(); 2186 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2187 unsigned IncrementSize = NVT.getSizeInBits()/8; 2188 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2189 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2190 2191 if (ExcessBits < NVT.getSizeInBits()) { 2192 // Transfer high bits from the top of Lo to the bottom of Hi. 2193 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 2194 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2195 TLI.getShiftAmountTy())); 2196 Hi = DAG.getNode(ISD::OR, NVT, Hi, 2197 DAG.getNode(ISD::SRL, NVT, Lo, 2198 DAG.getConstant(ExcessBits, 2199 TLI.getShiftAmountTy()))); 2200 } 2201 2202 // Store both the high bits and maybe some of the low bits. 2203 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2204 SVOffset, HiVT, isVolatile, Alignment); 2205 2206 // Increment the pointer to the other half. 2207 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2208 DAG.getIntPtrConstant(IncrementSize)); 2209 // Store the lowest ExcessBits bits in the second half. 2210 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 2211 SVOffset+IncrementSize, 2212 MVT::getIntegerVT(ExcessBits), 2213 isVolatile, MinAlign(Alignment, IncrementSize)); 2214 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2215 } 2216} 2217 2218SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2219 SDValue InL, InH; 2220 GetExpandedInteger(N->getOperand(0), InL, InH); 2221 // Just truncate the low part of the source. 2222 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 2223} 2224 2225SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2226 SDValue Op = N->getOperand(0); 2227 MVT SrcVT = Op.getValueType(); 2228 MVT DstVT = N->getValueType(0); 2229 2230 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2231 // Do a signed conversion then adjust the result. 2232 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op); 2233 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2234 2235 // The result of the signed conversion needs adjusting if the 'sign bit' of 2236 // the incoming integer was set. To handle this, we dynamically test to see 2237 // if it is set, and, if so, add a fudge factor. 2238 2239 const uint64_t F32TwoE32 = 0x4F800000ULL; 2240 const uint64_t F32TwoE64 = 0x5F800000ULL; 2241 const uint64_t F32TwoE128 = 0x7F800000ULL; 2242 2243 APInt FF(32, 0); 2244 if (SrcVT == MVT::i32) 2245 FF = APInt(32, F32TwoE32); 2246 else if (SrcVT == MVT::i64) 2247 FF = APInt(32, F32TwoE64); 2248 else if (SrcVT == MVT::i128) 2249 FF = APInt(32, F32TwoE128); 2250 else 2251 assert(false && "Unsupported UINT_TO_FP!"); 2252 2253 // Check whether the sign bit is set. 2254 SDValue Lo, Hi; 2255 GetExpandedInteger(Op, Lo, Hi); 2256 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 2257 DAG.getConstant(0, Hi.getValueType()), 2258 ISD::SETLT); 2259 2260 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2261 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2262 TLI.getPointerTy()); 2263 2264 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2265 SDValue Zero = DAG.getIntPtrConstant(0); 2266 SDValue Four = DAG.getIntPtrConstant(4); 2267 if (TLI.isBigEndian()) std::swap(Zero, Four); 2268 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, 2269 Zero, Four); 2270 unsigned Alignment = 2271 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2272 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset); 2273 Alignment = std::min(Alignment, 4u); 2274 2275 // Load the value out, extending it from f32 to the destination float type. 2276 // FIXME: Avoid the extend by constructing the right constant pool? 2277 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(), 2278 FudgePtr, NULL, 0, MVT::f32, 2279 false, Alignment); 2280 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge); 2281 } 2282 2283 // Otherwise, use a libcall. 2284 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2285 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2286 "Don't know how to expand this UINT_TO_FP!"); 2287 return MakeLibCall(LC, DstVT, &Op, 1, true); 2288} 2289