LegalizeIntegerTypes.cpp revision c82bf9b268eb63f7cf6f435d9ea222ddb8e3c5a8
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/CodeGen/PseudoSourceValue.h" 23using namespace llvm; 24 25//===----------------------------------------------------------------------===// 26// Integer Result Promotion 27//===----------------------------------------------------------------------===// 28 29/// PromoteIntegerResult - This method is called when a result of a node is 30/// found to be in need of promotion to a larger type. At this point, the node 31/// may also have invalid operands or may have other results that need 32/// expansion, we just know that (at least) one result needs promotion. 33void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 35 SDValue Res = SDValue(); 36 37 // See if the target wants to custom expand this node. 38 if (CustomLowerResults(N, N->getValueType(ResNo), true)) 39 return; 40 41 switch (N->getOpcode()) { 42 default: 43#ifndef NDEBUG 44 cerr << "PromoteIntegerResult #" << ResNo << ": "; 45 N->dump(&DAG); cerr << "\n"; 46#endif 47 assert(0 && "Do not know how to promote this operator!"); 48 abort(); 49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; 52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 55 case ISD::CONVERT_RNDSAT: 56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 60 case ISD::EXTRACT_VECTOR_ELT: 61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 67 case ISD::SIGN_EXTEND_INREG: 68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 74 75 case ISD::SIGN_EXTEND: 76 case ISD::ZERO_EXTEND: 77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 78 79 case ISD::FP_TO_SINT: 80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 81 82 case ISD::AND: 83 case ISD::OR: 84 case ISD::XOR: 85 case ISD::ADD: 86 case ISD::SUB: 87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 88 89 case ISD::SDIV: 90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 91 92 case ISD::UDIV: 93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 94 95 case ISD::SADDO: 96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 97 case ISD::UADDO: 98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 99 case ISD::SMULO: 100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 101 102 case ISD::ATOMIC_LOAD_ADD: 103 case ISD::ATOMIC_LOAD_SUB: 104 case ISD::ATOMIC_LOAD_AND: 105 case ISD::ATOMIC_LOAD_OR: 106 case ISD::ATOMIC_LOAD_XOR: 107 case ISD::ATOMIC_LOAD_NAND: 108 case ISD::ATOMIC_LOAD_MIN: 109 case ISD::ATOMIC_LOAD_MAX: 110 case ISD::ATOMIC_LOAD_UMIN: 111 case ISD::ATOMIC_LOAD_UMAX: 112 case ISD::ATOMIC_SWAP: 113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 114 115 case ISD::ATOMIC_CMP_SWAP: 116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 117 } 118 119 // If the result is null then the sub-method took care of registering it. 120 if (Res.getNode()) 121 SetPromotedInteger(SDValue(N, ResNo), Res); 122} 123 124SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 125 // Sign-extend the new bits, and continue the assertion. 126 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 128 Op.getValueType(), Op, N->getOperand(1)); 129} 130 131SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 132 // Zero the new bits, and continue the assertion. 133 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 135 Op.getValueType(), Op, N->getOperand(1)); 136} 137 138SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 139 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 141 N->getMemoryVT(), 142 N->getChain(), N->getBasePtr(), 143 Op2, N->getSrcValue(), N->getAlignment()); 144 // Legalized the chain result - switch anything that used the old chain to 145 // use the new one. 146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 147 return Res; 148} 149 150SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 151 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 152 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getMemoryVT(), 154 N->getChain(), N->getBasePtr(), 155 Op2, Op3, N->getSrcValue(), N->getAlignment()); 156 // Legalized the chain result - switch anything that used the old chain to 157 // use the new one. 158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 159 return Res; 160} 161 162SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 163 SDValue InOp = N->getOperand(0); 164 MVT InVT = InOp.getValueType(); 165 MVT NInVT = TLI.getTypeToTransformTo(InVT); 166 MVT OutVT = N->getValueType(0); 167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT); 168 DebugLoc dl = N->getDebugLoc(); 169 170 switch (getTypeAction(InVT)) { 171 default: 172 assert(false && "Unknown type action!"); 173 break; 174 case Legal: 175 break; 176 case PromoteInteger: 177 if (NOutVT.bitsEq(NInVT)) 178 // The input promotes to the same size. Convert the promoted value. 179 return DAG.getNode(ISD::BIT_CONVERT, dl, 180 NOutVT, GetPromotedInteger(InOp)); 181 break; 182 case SoftenFloat: 183 // Promote the integer operand by hand. 184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 185 case ExpandInteger: 186 case ExpandFloat: 187 break; 188 case ScalarizeVector: 189 // Convert the element to an integer and promote it by hand. 190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 191 BitConvertToInteger(GetScalarizedVector(InOp))); 192 case SplitVector: { 193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 194 // pieces of the input into integers and reassemble in the final type. 195 SDValue Lo, Hi; 196 GetSplitVector(N->getOperand(0), Lo, Hi); 197 Lo = BitConvertToInteger(Lo); 198 Hi = BitConvertToInteger(Hi); 199 200 if (TLI.isBigEndian()) 201 std::swap(Lo, Hi); 202 203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 204 MVT::getIntegerVT(NOutVT.getSizeInBits()), 205 JoinIntegers(Lo, Hi)); 206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp); 207 } 208 case WidenVector: 209 if (OutVT.bitsEq(NInVT)) 210 // The input is widened to the same size. Convert to the widened value. 211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp)); 212 } 213 214 // Otherwise, lower the bit-convert to a store/load from the stack. 215 // Create the stack frame object. Make sure it is aligned for both 216 // the source and destination types. 217 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT); 218 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 219 const Value *SV = PseudoSourceValue::getFixedStack(FI); 220 221 // Emit a store to the stack slot. 222 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0); 223 224 // Result is an extending load from the stack slot. 225 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT); 226} 227 228SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 229 SDValue Op = GetPromotedInteger(N->getOperand(0)); 230 MVT OVT = N->getValueType(0); 231 MVT NVT = Op.getValueType(); 232 DebugLoc dl = N->getDebugLoc(); 233 234 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 235 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 236 DAG.getConstant(DiffBits, TLI.getPointerTy())); 237} 238 239SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 240 // The pair element type may be legal, or may not promote to the same type as 241 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 243 TLI.getTypeToTransformTo(N->getValueType(0)), 244 JoinIntegers(N->getOperand(0), N->getOperand(1))); 245} 246 247SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 248 MVT VT = N->getValueType(0); 249 // Zero extend things like i1, sign extend everything else. It shouldn't 250 // matter in theory which one we pick, but this tends to give better code? 251 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 252 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 253 SDValue(N, 0)); 254 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 255 return Result; 256} 257 258SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 259 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 260 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 261 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 262 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 263 "can only promote integers"); 264 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 265 return DAG.getConvertRndSat(OutVT, N->getOperand(0), 266 N->getOperand(1), N->getOperand(2), 267 N->getOperand(3), N->getOperand(4), CvtCode); 268} 269 270SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 271 // Zero extend to the promoted type and do the count there. 272 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 273 MVT OVT = N->getValueType(0); 274 MVT NVT = Op.getValueType(); 275 Op = DAG.getNode(ISD::CTLZ, NVT, Op); 276 // Subtract off the extra leading bits in the bigger type. 277 return DAG.getNode(ISD::SUB, N->getDebugLoc(), NVT, Op, 278 DAG.getConstant(NVT.getSizeInBits() - 279 OVT.getSizeInBits(), NVT)); 280} 281 282SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 283 // Zero extend to the promoted type and do the count there. 284 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 285 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 286} 287 288SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 289 SDValue Op = GetPromotedInteger(N->getOperand(0)); 290 MVT OVT = N->getValueType(0); 291 MVT NVT = Op.getValueType(); 292 DebugLoc dl = N->getDebugLoc(); 293 // The count is the same in the promoted type except if the original 294 // value was zero. This can be handled by setting the bit just off 295 // the top of the original type. 296 APInt TopBit(NVT.getSizeInBits(), 0); 297 TopBit.set(OVT.getSizeInBits()); 298 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 299 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); 300} 301 302SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 303 MVT OldVT = N->getValueType(0); 304 SDValue OldVec = N->getOperand(0); 305 if (getTypeAction(OldVec.getValueType()) == WidenVector) 306 OldVec = GetWidenedVector(N->getOperand(0)); 307 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 308 DebugLoc dl = N->getDebugLoc(); 309 310 if (OldElts == 1) { 311 assert(!isTypeLegal(OldVec.getValueType()) && 312 "Legal one-element vector of a type needing promotion!"); 313 // It is tempting to follow GetScalarizedVector by a call to 314 // GetPromotedInteger, but this would be wrong because the 315 // scalarized value may not yet have been processed. 316 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), 317 GetScalarizedVector(OldVec)); 318 } 319 320 // Convert to a vector half as long with an element type of twice the width, 321 // for example <4 x i16> -> <2 x i32>. 322 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 323 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 324 assert(OldVT.isSimple() && NewVT.isSimple()); 325 326 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, 327 MVT::getVectorVT(NewVT, OldElts / 2), 328 OldVec); 329 330 // Extract the element at OldIdx / 2 from the new vector. 331 SDValue OldIdx = N->getOperand(1); 332 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx, 333 DAG.getConstant(1, TLI.getPointerTy())); 334 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx); 335 336 // Select the appropriate half of the element: Lo if OldIdx was even, 337 // Hi if it was odd. 338 SDValue Lo = Elt; 339 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt, 340 DAG.getConstant(OldVT.getSizeInBits(), 341 TLI.getPointerTy())); 342 if (TLI.isBigEndian()) 343 std::swap(Lo, Hi); 344 345 // Extend to the promoted type. 346 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx); 347 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo); 348 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res); 349} 350 351SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 352 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 353 unsigned NewOpc = N->getOpcode(); 354 DebugLoc dl = N->getDebugLoc(); 355 356 // If we're promoting a UINT to a larger size, check to see if the new node 357 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 358 // we can use that instead. This allows us to generate better code for 359 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 360 // legal, such as PowerPC. 361 if (N->getOpcode() == ISD::FP_TO_UINT && 362 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && 363 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 364 NewOpc = ISD::FP_TO_SINT; 365 366 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 367 368 // Assert that the converted value fits in the original type. If it doesn't 369 // (eg: because the value being converted is too big), then the result of the 370 // original operation was undefined anyway, so the assert is still correct. 371 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 372 ISD::AssertZext : ISD::AssertSext, dl, 373 NVT, Res, DAG.getValueType(N->getValueType(0))); 374} 375 376SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 377 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 378 DebugLoc dl = N->getDebugLoc(); 379 380 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 381 SDValue Res = GetPromotedInteger(N->getOperand(0)); 382 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 383 384 // If the result and operand types are the same after promotion, simplify 385 // to an in-register extension. 386 if (NVT == Res.getValueType()) { 387 // The high bits are not guaranteed to be anything. Insert an extend. 388 if (N->getOpcode() == ISD::SIGN_EXTEND) 389 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 390 DAG.getValueType(N->getOperand(0).getValueType())); 391 if (N->getOpcode() == ISD::ZERO_EXTEND) 392 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 393 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 394 return Res; 395 } 396 } 397 398 // Otherwise, just extend the original operand all the way to the larger type. 399 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 400} 401 402SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 403 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 404 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 405 ISD::LoadExtType ExtType = 406 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 407 DebugLoc dl = N->getDebugLoc(); 408 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 409 N->getSrcValue(), N->getSrcValueOffset(), 410 N->getMemoryVT(), N->isVolatile(), 411 N->getAlignment()); 412 413 // Legalized the chain result - switch anything that used the old chain to 414 // use the new one. 415 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 416 return Res; 417} 418 419/// Promote the overflow flag of an overflowing arithmetic node. 420SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 421 // Simply change the return type of the boolean result. 422 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); 423 MVT ValueVTs[] = { N->getValueType(0), NVT }; 424 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 425 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 426 DAG.getVTList(ValueVTs, 2), Ops, 2); 427 428 // Modified the sum result - switch anything that used the old sum to use 429 // the new one. 430 ReplaceValueWith(SDValue(N, 0), Res); 431 432 return SDValue(Res.getNode(), 1); 433} 434 435SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 436 if (ResNo == 1) 437 return PromoteIntRes_Overflow(N); 438 439 // The operation overflowed iff the result in the larger type is not the 440 // sign extension of its truncation to the original type. 441 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 442 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 443 MVT OVT = N->getOperand(0).getValueType(); 444 MVT NVT = LHS.getValueType(); 445 DebugLoc dl = N->getDebugLoc(); 446 447 // Do the arithmetic in the larger type. 448 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 449 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 450 451 // Calculate the overflow flag: sign extend the arithmetic result from 452 // the original type. 453 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 454 DAG.getValueType(OVT)); 455 // Overflowed if and only if this is not equal to Res. 456 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 457 458 // Use the calculated overflow everywhere. 459 ReplaceValueWith(SDValue(N, 1), Ofl); 460 461 return Res; 462} 463 464SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 465 // Sign extend the input. 466 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 467 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 468 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 469 LHS.getValueType(), LHS, RHS); 470} 471 472SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 473 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 474 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 475 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 476 LHS.getValueType(), N->getOperand(0),LHS,RHS); 477} 478 479SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 480 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 481 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 482 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 483 LHS.getValueType(), N->getOperand(0), 484 N->getOperand(1), LHS, RHS, N->getOperand(4)); 485} 486 487SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 488 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 489 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 490 DebugLoc dl = N->getDebugLoc(); 491 492 // Get the SETCC result using the canonical SETCC type. 493 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), 494 N->getOperand(1), N->getOperand(2)); 495 496 // Convert to the expected type. 497 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 498 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 499 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 500} 501 502SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 503 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 504 TLI.getTypeToTransformTo(N->getValueType(0)), 505 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 506} 507 508SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 509 SDValue Op = GetPromotedInteger(N->getOperand(0)); 510 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 511 Op.getValueType(), Op, N->getOperand(1)); 512} 513 514SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 515 // The input may have strange things in the top bits of the registers, but 516 // these operations don't care. They may have weird bits going out, but 517 // that too is okay if they are integer operations. 518 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 519 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 520 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 521 LHS.getValueType(), LHS, RHS); 522} 523 524SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 525 // The input value must be properly sign extended. 526 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 527 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 528 Res.getValueType(), Res, N->getOperand(1)); 529} 530 531SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 532 // The input value must be properly zero extended. 533 MVT VT = N->getValueType(0); 534 MVT NVT = TLI.getTypeToTransformTo(VT); 535 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 536 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 537} 538 539SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 540 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 541 SDValue Res; 542 543 switch (getTypeAction(N->getOperand(0).getValueType())) { 544 default: assert(0 && "Unknown type action!"); 545 case Legal: 546 case ExpandInteger: 547 Res = N->getOperand(0); 548 break; 549 case PromoteInteger: 550 Res = GetPromotedInteger(N->getOperand(0)); 551 break; 552 } 553 554 // Truncate to NVT instead of VT 555 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); 556} 557 558SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 559 if (ResNo == 1) 560 return PromoteIntRes_Overflow(N); 561 562 // The operation overflowed iff the result in the larger type is not the 563 // zero extension of its truncation to the original type. 564 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 565 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 566 MVT OVT = N->getOperand(0).getValueType(); 567 MVT NVT = LHS.getValueType(); 568 DebugLoc dl = N->getDebugLoc(); 569 570 // Do the arithmetic in the larger type. 571 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 572 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 573 574 // Calculate the overflow flag: zero extend the arithmetic result from 575 // the original type. 576 SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT); 577 // Overflowed if and only if this is not equal to Res. 578 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 579 580 // Use the calculated overflow everywhere. 581 ReplaceValueWith(SDValue(N, 1), Ofl); 582 583 return Res; 584} 585 586SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 587 // Zero extend the input. 588 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 589 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 590 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 591 LHS.getValueType(), LHS, RHS); 592} 593 594SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 595 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), 596 TLI.getTypeToTransformTo(N->getValueType(0))); 597} 598 599SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 600 SDValue Chain = N->getOperand(0); // Get the chain. 601 SDValue Ptr = N->getOperand(1); // Get the pointer. 602 MVT VT = N->getValueType(0); 603 DebugLoc dl = N->getDebugLoc(); 604 605 MVT RegVT = TLI.getRegisterType(VT); 606 unsigned NumRegs = TLI.getNumRegisters(VT); 607 // The argument is passed as NumRegs registers of type RegVT. 608 609 SmallVector<SDValue, 8> Parts(NumRegs); 610 for (unsigned i = 0; i < NumRegs; ++i) { 611 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); 612 Chain = Parts[i].getValue(1); 613 } 614 615 // Handle endianness of the load. 616 if (TLI.isBigEndian()) 617 std::reverse(Parts.begin(), Parts.end()); 618 619 // Assemble the parts in the promoted type. 620 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 621 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 622 for (unsigned i = 1; i < NumRegs; ++i) { 623 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 624 // Shift it to the right position and "or" it in. 625 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 626 DAG.getConstant(i * RegVT.getSizeInBits(), 627 TLI.getPointerTy())); 628 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 629 } 630 631 // Modified the chain result - switch anything that used the old chain to 632 // use the new one. 633 ReplaceValueWith(SDValue(N, 1), Chain); 634 635 return Res; 636} 637 638SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 639 assert(ResNo == 1 && "Only boolean result promotion currently supported!"); 640 return PromoteIntRes_Overflow(N); 641} 642 643//===----------------------------------------------------------------------===// 644// Integer Operand Promotion 645//===----------------------------------------------------------------------===// 646 647/// PromoteIntegerOperand - This method is called when the specified operand of 648/// the specified node is found to need promotion. At this point, all of the 649/// result types of the node are known to be legal, but other operands of the 650/// node may need promotion or expansion as well as the specified one. 651bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 652 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 653 SDValue Res = SDValue(); 654 655 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false)) 656 return false; 657 658 switch (N->getOpcode()) { 659 default: 660 #ifndef NDEBUG 661 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 662 N->dump(&DAG); cerr << "\n"; 663 #endif 664 assert(0 && "Do not know how to promote this operator's operand!"); 665 abort(); 666 667 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 668 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 669 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 670 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 671 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 672 case ISD::CONVERT_RNDSAT: 673 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 674 case ISD::INSERT_VECTOR_ELT: 675 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 676 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 677 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 678 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 679 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 680 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 681 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 682 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 683 OpNo); break; 684 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 685 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 686 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 687 } 688 689 // If the result is null, the sub-method took care of registering results etc. 690 if (!Res.getNode()) return false; 691 692 // If the result is N, the sub-method updated N in place. Tell the legalizer 693 // core about this. 694 if (Res.getNode() == N) 695 return true; 696 697 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 698 "Invalid operand expansion"); 699 700 ReplaceValueWith(SDValue(N, 0), Res); 701 return false; 702} 703 704/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 705/// shared among BR_CC, SELECT_CC, and SETCC handlers. 706void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 707 ISD::CondCode CCCode) { 708 // We have to insert explicit sign or zero extends. Note that we could 709 // insert sign extends for ALL conditions, but zero extend is cheaper on 710 // many machines (an AND instead of two shifts), so prefer it. 711 switch (CCCode) { 712 default: assert(0 && "Unknown integer comparison!"); 713 case ISD::SETEQ: 714 case ISD::SETNE: 715 case ISD::SETUGE: 716 case ISD::SETUGT: 717 case ISD::SETULE: 718 case ISD::SETULT: 719 // ALL of these operations will work if we either sign or zero extend 720 // the operands (including the unsigned comparisons!). Zero extend is 721 // usually a simpler/cheaper operation, so prefer it. 722 NewLHS = ZExtPromotedInteger(NewLHS); 723 NewRHS = ZExtPromotedInteger(NewRHS); 724 break; 725 case ISD::SETGE: 726 case ISD::SETGT: 727 case ISD::SETLT: 728 case ISD::SETLE: 729 NewLHS = SExtPromotedInteger(NewLHS); 730 NewRHS = SExtPromotedInteger(NewRHS); 731 break; 732 } 733} 734 735SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 736 SDValue Op = GetPromotedInteger(N->getOperand(0)); 737 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 738} 739 740SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 741 assert(OpNo == 2 && "Don't know how to promote this operand!"); 742 743 SDValue LHS = N->getOperand(2); 744 SDValue RHS = N->getOperand(3); 745 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 746 747 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 748 // legal types. 749 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 750 N->getOperand(1), LHS, RHS, N->getOperand(4)); 751} 752 753SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 754 assert(OpNo == 1 && "only know how to promote condition"); 755 756 // Promote all the way up to the canonical SetCC type. 757 MVT SVT = TLI.getSetCCResultType(MVT::Other); 758 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 759 760 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 761 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 762 N->getOperand(2)); 763} 764 765SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 766 // Since the result type is legal, the operands must promote to it. 767 MVT OVT = N->getOperand(0).getValueType(); 768 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 769 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 770 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 771 DebugLoc dl = N->getDebugLoc(); 772 773 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 774 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 775 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 776} 777 778SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 779 // The vector type is legal but the element type is not. This implies 780 // that the vector is a power-of-two in length and that the element 781 // type does not have a strange size (eg: it is not i1). 782 MVT VecVT = N->getValueType(0); 783 unsigned NumElts = VecVT.getVectorNumElements(); 784 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 785 DebugLoc dl = N->getDebugLoc(); 786 787 // Build a vector of half the length out of elements of twice the bitwidth. 788 // For example <4 x i16> -> <2 x i32>. 789 MVT OldVT = N->getOperand(0).getValueType(); 790 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 791 assert(OldVT.isSimple() && NewVT.isSimple()); 792 793 std::vector<SDValue> NewElts; 794 NewElts.reserve(NumElts/2); 795 796 for (unsigned i = 0; i < NumElts; i += 2) { 797 // Combine two successive elements into one promoted element. 798 SDValue Lo = N->getOperand(i); 799 SDValue Hi = N->getOperand(i+1); 800 if (TLI.isBigEndian()) 801 std::swap(Lo, Hi); 802 NewElts.push_back(JoinIntegers(Lo, Hi)); 803 } 804 805 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 806 MVT::getVectorVT(NewVT, NewElts.size()), 807 &NewElts[0], NewElts.size()); 808 809 // Convert the new vector to the old vector type. 810 return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec); 811} 812 813SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 814 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 815 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 816 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 817 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 818 "can only promote integer arguments"); 819 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 820 return DAG.getConvertRndSat(N->getValueType(0), InOp, 821 N->getOperand(1), N->getOperand(2), 822 N->getOperand(3), N->getOperand(4), CvtCode); 823} 824 825SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 826 unsigned OpNo) { 827 if (OpNo == 1) { 828 // Promote the inserted value. This is valid because the type does not 829 // have to match the vector element type. 830 831 // Check that any extra bits introduced will be truncated away. 832 assert(N->getOperand(1).getValueType().getSizeInBits() >= 833 N->getValueType(0).getVectorElementType().getSizeInBits() && 834 "Type of inserted value narrower than vector element type!"); 835 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 836 GetPromotedInteger(N->getOperand(1)), 837 N->getOperand(2)); 838 } 839 840 assert(OpNo == 2 && "Different operand and result vector types?"); 841 842 // Promote the index. 843 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 844 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 845 N->getOperand(1), Idx); 846} 847 848SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 849 SDValue NewOps[6]; 850 NewOps[0] = N->getOperand(0); 851 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 852 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 853 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 854 } 855 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 856 array_lengthof(NewOps)); 857} 858 859SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 860 assert(OpNo == 0 && "Only know how to promote condition"); 861 862 // Promote all the way up to the canonical SetCC type. 863 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); 864 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); 865 866 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 867 N->getOperand(1), N->getOperand(2)); 868} 869 870SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 871 assert(OpNo == 0 && "Don't know how to promote this operand!"); 872 873 SDValue LHS = N->getOperand(0); 874 SDValue RHS = N->getOperand(1); 875 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 876 877 // The CC (#4) and the possible return values (#2 and #3) have legal types. 878 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 879 N->getOperand(3), N->getOperand(4)); 880} 881 882SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 883 assert(OpNo == 0 && "Don't know how to promote this operand!"); 884 885 SDValue LHS = N->getOperand(0); 886 SDValue RHS = N->getOperand(1); 887 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 888 889 // The CC (#2) is always legal. 890 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 891} 892 893SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 894 SDValue Op = GetPromotedInteger(N->getOperand(0)); 895 DebugLoc dl = N->getDebugLoc(); 896 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 897 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 898 Op, DAG.getValueType(N->getOperand(0).getValueType())); 899} 900 901SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 902 return DAG.UpdateNodeOperands(SDValue(N, 0), 903 SExtPromotedInteger(N->getOperand(0))); 904} 905 906SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 907 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 908 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 909 int SVOffset = N->getSrcValueOffset(); 910 unsigned Alignment = N->getAlignment(); 911 bool isVolatile = N->isVolatile(); 912 DebugLoc dl = N->getDebugLoc(); 913 914 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 915 916 // Truncate the value and store the result. 917 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(), 918 SVOffset, N->getMemoryVT(), 919 isVolatile, Alignment); 920} 921 922SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 923 SDValue Op = GetPromotedInteger(N->getOperand(0)); 924 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 925} 926 927SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 928 return DAG.UpdateNodeOperands(SDValue(N, 0), 929 ZExtPromotedInteger(N->getOperand(0))); 930} 931 932SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 933 SDValue Op = GetPromotedInteger(N->getOperand(0)); 934 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 935 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 936} 937 938 939//===----------------------------------------------------------------------===// 940// Integer Result Expansion 941//===----------------------------------------------------------------------===// 942 943/// ExpandIntegerResult - This method is called when the specified result of the 944/// specified node is found to need expansion. At this point, the node may also 945/// have invalid operands or may have other results that need promotion, we just 946/// know that (at least) one result needs expansion. 947void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 948 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 949 SDValue Lo, Hi; 950 Lo = Hi = SDValue(); 951 952 // See if the target wants to custom expand this node. 953 if (CustomLowerResults(N, N->getValueType(ResNo), true)) 954 return; 955 956 switch (N->getOpcode()) { 957 default: 958#ifndef NDEBUG 959 cerr << "ExpandIntegerResult #" << ResNo << ": "; 960 N->dump(&DAG); cerr << "\n"; 961#endif 962 assert(0 && "Do not know how to expand the result of this operator!"); 963 abort(); 964 965 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 966 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 967 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 968 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 969 970 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 971 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 972 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 973 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 974 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 975 976 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 977 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 978 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 979 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 980 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 981 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 982 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 983 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 984 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 985 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 986 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 987 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 988 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 989 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 990 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 991 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 992 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 993 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 994 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 995 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 996 997 case ISD::AND: 998 case ISD::OR: 999 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1000 1001 case ISD::ADD: 1002 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1003 1004 case ISD::ADDC: 1005 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1006 1007 case ISD::ADDE: 1008 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1009 1010 case ISD::SHL: 1011 case ISD::SRA: 1012 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1013 } 1014 1015 // If Lo/Hi is null, the sub-method took care of registering results etc. 1016 if (Lo.getNode()) 1017 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1018} 1019 1020/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1021/// and the shift amount is a constant 'Amt'. Expand the operation. 1022void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1023 SDValue &Lo, SDValue &Hi) { 1024 DebugLoc dl = N->getDebugLoc(); 1025 // Expand the incoming operand to be shifted, so that we have its parts 1026 SDValue InL, InH; 1027 GetExpandedInteger(N->getOperand(0), InL, InH); 1028 1029 MVT NVT = InL.getValueType(); 1030 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1031 unsigned NVTBits = NVT.getSizeInBits(); 1032 MVT ShTy = N->getOperand(1).getValueType(); 1033 1034 if (N->getOpcode() == ISD::SHL) { 1035 if (Amt > VTBits) { 1036 Lo = Hi = DAG.getConstant(0, NVT); 1037 } else if (Amt > NVTBits) { 1038 Lo = DAG.getConstant(0, NVT); 1039 Hi = DAG.getNode(ISD::SHL, dl, 1040 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1041 } else if (Amt == NVTBits) { 1042 Lo = DAG.getConstant(0, NVT); 1043 Hi = InL; 1044 } else if (Amt == 1 && 1045 TLI.isOperationLegalOrCustom(ISD::ADDC, 1046 TLI.getTypeToExpandTo(NVT))) { 1047 // Emit this X << 1 as X+X. 1048 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1049 SDValue LoOps[2] = { InL, InL }; 1050 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1051 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1052 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1053 } else { 1054 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)); 1055 Hi = DAG.getNode(ISD::OR, dl, NVT, 1056 DAG.getNode(ISD::SHL, dl, NVT, InH, 1057 DAG.getConstant(Amt, ShTy)), 1058 DAG.getNode(ISD::SRL, dl, NVT, InL, 1059 DAG.getConstant(NVTBits-Amt, ShTy))); 1060 } 1061 return; 1062 } 1063 1064 if (N->getOpcode() == ISD::SRL) { 1065 if (Amt > VTBits) { 1066 Lo = DAG.getConstant(0, NVT); 1067 Hi = DAG.getConstant(0, NVT); 1068 } else if (Amt > NVTBits) { 1069 Lo = DAG.getNode(ISD::SRL, dl, 1070 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1071 Hi = DAG.getConstant(0, NVT); 1072 } else if (Amt == NVTBits) { 1073 Lo = InH; 1074 Hi = DAG.getConstant(0, NVT); 1075 } else { 1076 Lo = DAG.getNode(ISD::OR, dl, NVT, 1077 DAG.getNode(ISD::SRL, dl, NVT, InL, 1078 DAG.getConstant(Amt, ShTy)), 1079 DAG.getNode(ISD::SHL, dl, NVT, InH, 1080 DAG.getConstant(NVTBits-Amt, ShTy))); 1081 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1082 } 1083 return; 1084 } 1085 1086 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1087 if (Amt > VTBits) { 1088 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1089 DAG.getConstant(NVTBits-1, ShTy)); 1090 } else if (Amt > NVTBits) { 1091 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1092 DAG.getConstant(Amt-NVTBits, ShTy)); 1093 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1094 DAG.getConstant(NVTBits-1, ShTy)); 1095 } else if (Amt == NVTBits) { 1096 Lo = InH; 1097 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1098 DAG.getConstant(NVTBits-1, ShTy)); 1099 } else { 1100 Lo = DAG.getNode(ISD::OR, NVT, 1101 DAG.getNode(ISD::SRL, dl, NVT, InL, 1102 DAG.getConstant(Amt, ShTy)), 1103 DAG.getNode(ISD::SHL, dl, NVT, InH, 1104 DAG.getConstant(NVTBits-Amt, ShTy))); 1105 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1106 } 1107} 1108 1109/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1110/// this shift based on knowledge of the high bit of the shift amount. If we 1111/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1112/// shift amount. 1113bool DAGTypeLegalizer:: 1114ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1115 SDValue Amt = N->getOperand(1); 1116 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1117 MVT ShTy = Amt.getValueType(); 1118 unsigned ShBits = ShTy.getSizeInBits(); 1119 unsigned NVTBits = NVT.getSizeInBits(); 1120 assert(isPowerOf2_32(NVTBits) && 1121 "Expanded integer type size not a power of two!"); 1122 DebugLoc dl = N->getDebugLoc(); 1123 1124 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1125 APInt KnownZero, KnownOne; 1126 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1127 1128 // If we don't know anything about the high bits, exit. 1129 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1130 return false; 1131 1132 // Get the incoming operand to be shifted. 1133 SDValue InL, InH; 1134 GetExpandedInteger(N->getOperand(0), InL, InH); 1135 1136 // If we know that any of the high bits of the shift amount are one, then we 1137 // can do this as a couple of simple shifts. 1138 if (KnownOne.intersects(HighBitMask)) { 1139 // Mask out the high bit, which we know is set. 1140 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1141 DAG.getConstant(~HighBitMask, ShTy)); 1142 1143 switch (N->getOpcode()) { 1144 default: assert(0 && "Unknown shift"); 1145 case ISD::SHL: 1146 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1147 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1148 return true; 1149 case ISD::SRL: 1150 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1151 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1152 return true; 1153 case ISD::SRA: 1154 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1155 DAG.getConstant(NVTBits-1, ShTy)); 1156 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1157 return true; 1158 } 1159 } 1160 1161#if 0 1162 // FIXME: This code is broken for shifts with a zero amount! 1163 // If we know that all of the high bits of the shift amount are zero, then we 1164 // can do this as a couple of simple shifts. 1165 if ((KnownZero & HighBitMask) == HighBitMask) { 1166 // Compute 32-amt. 1167 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1168 DAG.getConstant(NVTBits, ShTy), 1169 Amt); 1170 unsigned Op1, Op2; 1171 switch (N->getOpcode()) { 1172 default: assert(0 && "Unknown shift"); 1173 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1174 case ISD::SRL: 1175 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1176 } 1177 1178 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1179 Hi = DAG.getNode(ISD::OR, NVT, 1180 DAG.getNode(Op1, NVT, InH, Amt), 1181 DAG.getNode(Op2, NVT, InL, Amt2)); 1182 return true; 1183 } 1184#endif 1185 1186 return false; 1187} 1188 1189void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1190 SDValue &Lo, SDValue &Hi) { 1191 DebugLoc dl = N->getDebugLoc(); 1192 // Expand the subcomponents. 1193 SDValue LHSL, LHSH, RHSL, RHSH; 1194 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1195 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1196 1197 MVT NVT = LHSL.getValueType(); 1198 SDValue LoOps[2] = { LHSL, RHSL }; 1199 SDValue HiOps[3] = { LHSH, RHSH }; 1200 1201 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1202 // them. TODO: Teach operation legalization how to expand unsupported 1203 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1204 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1205 // generate a value of this type in the expanded code sequence. 1206 bool hasCarry = 1207 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1208 ISD::ADDC : ISD::SUBC, 1209 TLI.getTypeToExpandTo(NVT)); 1210 1211 if (hasCarry) { 1212 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1213 if (N->getOpcode() == ISD::ADD) { 1214 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1215 HiOps[2] = Lo.getValue(1); 1216 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1217 } else { 1218 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1219 HiOps[2] = Lo.getValue(1); 1220 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1221 } 1222 } else { 1223 if (N->getOpcode() == ISD::ADD) { 1224 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1225 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1226 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1227 ISD::SETULT); 1228 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1229 DAG.getConstant(1, NVT), 1230 DAG.getConstant(0, NVT)); 1231 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1232 ISD::SETULT); 1233 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1234 DAG.getConstant(1, NVT), Carry1); 1235 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1236 } else { 1237 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1238 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1239 SDValue Cmp = 1240 DAG.getSetCC(TLI.getSetCCResultType(LoOps[0].getValueType()), 1241 LoOps[0], LoOps[1], ISD::SETULT); 1242 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1243 DAG.getConstant(1, NVT), 1244 DAG.getConstant(0, NVT)); 1245 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1246 } 1247 } 1248} 1249 1250void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1251 SDValue &Lo, SDValue &Hi) { 1252 // Expand the subcomponents. 1253 SDValue LHSL, LHSH, RHSL, RHSH; 1254 DebugLoc dl = N->getDebugLoc(); 1255 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1256 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1257 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1258 SDValue LoOps[2] = { LHSL, RHSL }; 1259 SDValue HiOps[3] = { LHSH, RHSH }; 1260 1261 if (N->getOpcode() == ISD::ADDC) { 1262 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1263 HiOps[2] = Lo.getValue(1); 1264 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1265 } else { 1266 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1267 HiOps[2] = Lo.getValue(1); 1268 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1269 } 1270 1271 // Legalized the flag result - switch anything that used the old flag to 1272 // use the new one. 1273 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1274} 1275 1276void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1277 SDValue &Lo, SDValue &Hi) { 1278 // Expand the subcomponents. 1279 SDValue LHSL, LHSH, RHSL, RHSH; 1280 DebugLoc dl = N->getDebugLoc(); 1281 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1282 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1283 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1284 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1285 SDValue HiOps[3] = { LHSH, RHSH }; 1286 1287 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1288 HiOps[2] = Lo.getValue(1); 1289 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1290 1291 // Legalized the flag result - switch anything that used the old flag to 1292 // use the new one. 1293 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1294} 1295 1296void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1297 SDValue &Lo, SDValue &Hi) { 1298 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1299 DebugLoc dl = N->getDebugLoc(); 1300 SDValue Op = N->getOperand(0); 1301 if (Op.getValueType().bitsLE(NVT)) { 1302 // The low part is any extension of the input (which degenerates to a copy). 1303 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1304 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); // The high part is undefined. 1305 } else { 1306 // For example, extension of an i48 to an i64. The operand type necessarily 1307 // promotes to the result type, so will end up being expanded too. 1308 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1309 "Only know how to promote this result!"); 1310 SDValue Res = GetPromotedInteger(Op); 1311 assert(Res.getValueType() == N->getValueType(0) && 1312 "Operand over promoted?"); 1313 // Split the promoted operand. This will simplify when it is expanded. 1314 SplitInteger(Res, Lo, Hi); 1315 } 1316} 1317 1318void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1319 SDValue &Lo, SDValue &Hi) { 1320 DebugLoc dl = N->getDebugLoc(); 1321 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1322 MVT NVT = Lo.getValueType(); 1323 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1324 unsigned NVTBits = NVT.getSizeInBits(); 1325 unsigned EVTBits = EVT.getSizeInBits(); 1326 1327 if (NVTBits < EVTBits) { 1328 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1329 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1330 } else { 1331 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1332 // The high part replicates the sign bit of Lo, make it explicit. 1333 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1334 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1335 } 1336} 1337 1338void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1339 SDValue &Lo, SDValue &Hi) { 1340 DebugLoc dl = N->getDebugLoc(); 1341 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1342 MVT NVT = Lo.getValueType(); 1343 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1344 unsigned NVTBits = NVT.getSizeInBits(); 1345 unsigned EVTBits = EVT.getSizeInBits(); 1346 1347 if (NVTBits < EVTBits) { 1348 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1349 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1350 } else { 1351 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1352 // The high part must be zero, make it explicit. 1353 Hi = DAG.getConstant(0, NVT); 1354 } 1355} 1356 1357void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1358 SDValue &Lo, SDValue &Hi) { 1359 DebugLoc dl = N->getDebugLoc(); 1360 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1361 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1362 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1363} 1364 1365void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1366 SDValue &Lo, SDValue &Hi) { 1367 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1368 unsigned NBitWidth = NVT.getSizeInBits(); 1369 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1370 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1371 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1372} 1373 1374void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1375 SDValue &Lo, SDValue &Hi) { 1376 DebugLoc dl = N->getDebugLoc(); 1377 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1378 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1379 MVT NVT = Lo.getValueType(); 1380 1381 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1382 DAG.getConstant(0, NVT), ISD::SETNE); 1383 1384 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 1385 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 1386 1387 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1388 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1389 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1390 Hi = DAG.getConstant(0, NVT); 1391} 1392 1393void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1394 SDValue &Lo, SDValue &Hi) { 1395 DebugLoc dl = N->getDebugLoc(); 1396 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1397 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1398 MVT NVT = Lo.getValueType(); 1399 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1400 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1401 Hi = DAG.getConstant(0, NVT); 1402} 1403 1404void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1405 SDValue &Lo, SDValue &Hi) { 1406 DebugLoc dl = N->getDebugLoc(); 1407 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1408 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1409 MVT NVT = Lo.getValueType(); 1410 1411 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1412 DAG.getConstant(0, NVT), ISD::SETNE); 1413 1414 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 1415 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 1416 1417 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1418 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1419 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1420 Hi = DAG.getConstant(0, NVT); 1421} 1422 1423void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1424 SDValue &Hi) { 1425 DebugLoc dl = N->getDebugLoc(); 1426 MVT VT = N->getValueType(0); 1427 SDValue Op = N->getOperand(0); 1428 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1429 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1430 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1431} 1432 1433void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1434 SDValue &Hi) { 1435 DebugLoc dl = N->getDebugLoc(); 1436 MVT VT = N->getValueType(0); 1437 SDValue Op = N->getOperand(0); 1438 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1439 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1440 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1441} 1442 1443void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1444 SDValue &Lo, SDValue &Hi) { 1445 if (ISD::isNormalLoad(N)) { 1446 ExpandRes_NormalLoad(N, Lo, Hi); 1447 return; 1448 } 1449 1450 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1451 1452 MVT VT = N->getValueType(0); 1453 MVT NVT = TLI.getTypeToTransformTo(VT); 1454 SDValue Ch = N->getChain(); 1455 SDValue Ptr = N->getBasePtr(); 1456 ISD::LoadExtType ExtType = N->getExtensionType(); 1457 int SVOffset = N->getSrcValueOffset(); 1458 unsigned Alignment = N->getAlignment(); 1459 bool isVolatile = N->isVolatile(); 1460 DebugLoc dl = N->getDebugLoc(); 1461 1462 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1463 1464 if (N->getMemoryVT().bitsLE(NVT)) { 1465 MVT EVT = N->getMemoryVT(); 1466 1467 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1468 EVT, isVolatile, Alignment); 1469 1470 // Remember the chain. 1471 Ch = Lo.getValue(1); 1472 1473 if (ExtType == ISD::SEXTLOAD) { 1474 // The high part is obtained by SRA'ing all but one of the bits of the 1475 // lo part. 1476 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1477 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1478 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1479 } else if (ExtType == ISD::ZEXTLOAD) { 1480 // The high part is just a zero. 1481 Hi = DAG.getConstant(0, NVT); 1482 } else { 1483 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1484 // The high part is undefined. 1485 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); 1486 } 1487 } else if (TLI.isLittleEndian()) { 1488 // Little-endian - low bits are at low addresses. 1489 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset, 1490 isVolatile, Alignment); 1491 1492 unsigned ExcessBits = 1493 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1494 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1495 1496 // Increment the pointer to the other half. 1497 unsigned IncrementSize = NVT.getSizeInBits()/8; 1498 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1499 DAG.getIntPtrConstant(IncrementSize)); 1500 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), 1501 SVOffset+IncrementSize, NEVT, 1502 isVolatile, MinAlign(Alignment, IncrementSize)); 1503 1504 // Build a factor node to remember that this load is independent of the 1505 // other one. 1506 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1507 Hi.getValue(1)); 1508 } else { 1509 // Big-endian - high bits are at low addresses. Favor aligned loads at 1510 // the cost of some bit-fiddling. 1511 MVT EVT = N->getMemoryVT(); 1512 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1513 unsigned IncrementSize = NVT.getSizeInBits()/8; 1514 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1515 1516 // Load both the high bits and maybe some of the low bits. 1517 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1518 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1519 isVolatile, Alignment); 1520 1521 // Increment the pointer to the other half. 1522 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1523 DAG.getIntPtrConstant(IncrementSize)); 1524 // Load the rest of the low bits. 1525 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(), 1526 SVOffset+IncrementSize, 1527 MVT::getIntegerVT(ExcessBits), 1528 isVolatile, MinAlign(Alignment, IncrementSize)); 1529 1530 // Build a factor node to remember that this load is independent of the 1531 // other one. 1532 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1533 Hi.getValue(1)); 1534 1535 if (ExcessBits < NVT.getSizeInBits()) { 1536 // Transfer low bits from the bottom of Hi to the top of Lo. 1537 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1538 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1539 DAG.getConstant(ExcessBits, 1540 TLI.getPointerTy()))); 1541 // Move high bits to the right position in Hi. 1542 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1543 NVT, Hi, 1544 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1545 TLI.getPointerTy())); 1546 } 1547 } 1548 1549 // Legalized the chain result - switch anything that used the old chain to 1550 // use the new one. 1551 ReplaceValueWith(SDValue(N, 1), Ch); 1552} 1553 1554void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1555 SDValue &Lo, SDValue &Hi) { 1556 DebugLoc dl = N->getDebugLoc(); 1557 SDValue LL, LH, RL, RH; 1558 GetExpandedInteger(N->getOperand(0), LL, LH); 1559 GetExpandedInteger(N->getOperand(1), RL, RH); 1560 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1561 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1562} 1563 1564void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1565 SDValue &Lo, SDValue &Hi) { 1566 MVT VT = N->getValueType(0); 1567 MVT NVT = TLI.getTypeToTransformTo(VT); 1568 DebugLoc dl = N->getDebugLoc(); 1569 1570 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1571 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1572 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1573 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1574 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1575 SDValue LL, LH, RL, RH; 1576 GetExpandedInteger(N->getOperand(0), LL, LH); 1577 GetExpandedInteger(N->getOperand(1), RL, RH); 1578 unsigned OuterBitSize = VT.getSizeInBits(); 1579 unsigned InnerBitSize = NVT.getSizeInBits(); 1580 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1581 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1582 1583 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1584 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1585 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1586 // The inputs are both zero-extended. 1587 if (HasUMUL_LOHI) { 1588 // We can emit a umul_lohi. 1589 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1590 Hi = SDValue(Lo.getNode(), 1); 1591 return; 1592 } 1593 if (HasMULHU) { 1594 // We can emit a mulhu+mul. 1595 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1596 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1597 return; 1598 } 1599 } 1600 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1601 // The input values are both sign-extended. 1602 if (HasSMUL_LOHI) { 1603 // We can emit a smul_lohi. 1604 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1605 Hi = SDValue(Lo.getNode(), 1); 1606 return; 1607 } 1608 if (HasMULHS) { 1609 // We can emit a mulhs+mul. 1610 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1611 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1612 return; 1613 } 1614 } 1615 if (HasUMUL_LOHI) { 1616 // Lo,Hi = umul LHS, RHS. 1617 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1618 DAG.getVTList(NVT, NVT), LL, RL); 1619 Lo = UMulLOHI; 1620 Hi = UMulLOHI.getValue(1); 1621 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1622 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1623 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1624 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1625 return; 1626 } 1627 if (HasMULHU) { 1628 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1629 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1630 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1631 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1632 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1633 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1634 return; 1635 } 1636 } 1637 1638 // If nothing else, we can make a libcall. 1639 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1640 if (VT == MVT::i16) 1641 LC = RTLIB::MUL_I16; 1642 else if (VT == MVT::i32) 1643 LC = RTLIB::MUL_I32; 1644 else if (VT == MVT::i64) 1645 LC = RTLIB::MUL_I64; 1646 else if (VT == MVT::i128) 1647 LC = RTLIB::MUL_I128; 1648 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1649 1650 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1651 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1652} 1653 1654void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1655 SDValue &Lo, SDValue &Hi) { 1656 MVT VT = N->getValueType(0); 1657 DebugLoc dl = N->getDebugLoc(); 1658 1659 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1660 if (VT == MVT::i32) 1661 LC = RTLIB::SDIV_I32; 1662 else if (VT == MVT::i64) 1663 LC = RTLIB::SDIV_I64; 1664 else if (VT == MVT::i128) 1665 LC = RTLIB::SDIV_I128; 1666 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1667 1668 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1669 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1670} 1671 1672void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1673 SDValue &Lo, SDValue &Hi) { 1674 MVT VT = N->getValueType(0); 1675 DebugLoc dl = N->getDebugLoc(); 1676 1677 // If we can emit an efficient shift operation, do so now. Check to see if 1678 // the RHS is a constant. 1679 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1680 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1681 1682 // If we can determine that the high bit of the shift is zero or one, even if 1683 // the low bits are variable, emit this shift in an optimized form. 1684 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1685 return; 1686 1687 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1688 unsigned PartsOpc; 1689 if (N->getOpcode() == ISD::SHL) { 1690 PartsOpc = ISD::SHL_PARTS; 1691 } else if (N->getOpcode() == ISD::SRL) { 1692 PartsOpc = ISD::SRL_PARTS; 1693 } else { 1694 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1695 PartsOpc = ISD::SRA_PARTS; 1696 } 1697 1698 // Next check to see if the target supports this SHL_PARTS operation or if it 1699 // will custom expand it. 1700 MVT NVT = TLI.getTypeToTransformTo(VT); 1701 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1702 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1703 Action == TargetLowering::Custom) { 1704 // Expand the subcomponents. 1705 SDValue LHSL, LHSH; 1706 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1707 1708 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1709 MVT VT = LHSL.getValueType(); 1710 Lo = DAG.getNode(PartsOpc, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1711 Hi = Lo.getValue(1); 1712 return; 1713 } 1714 1715 // Otherwise, emit a libcall. 1716 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1717 bool isSigned; 1718 if (N->getOpcode() == ISD::SHL) { 1719 isSigned = false; /*sign irrelevant*/ 1720 if (VT == MVT::i16) 1721 LC = RTLIB::SHL_I16; 1722 else if (VT == MVT::i32) 1723 LC = RTLIB::SHL_I32; 1724 else if (VT == MVT::i64) 1725 LC = RTLIB::SHL_I64; 1726 else if (VT == MVT::i128) 1727 LC = RTLIB::SHL_I128; 1728 } else if (N->getOpcode() == ISD::SRL) { 1729 isSigned = false; 1730 if (VT == MVT::i16) 1731 LC = RTLIB::SRL_I16; 1732 else if (VT == MVT::i32) 1733 LC = RTLIB::SRL_I32; 1734 else if (VT == MVT::i64) 1735 LC = RTLIB::SRL_I64; 1736 else if (VT == MVT::i128) 1737 LC = RTLIB::SRL_I128; 1738 } else { 1739 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1740 isSigned = true; 1741 if (VT == MVT::i16) 1742 LC = RTLIB::SRA_I16; 1743 else if (VT == MVT::i32) 1744 LC = RTLIB::SRA_I32; 1745 else if (VT == MVT::i64) 1746 LC = RTLIB::SRA_I64; 1747 else if (VT == MVT::i128) 1748 LC = RTLIB::SRA_I128; 1749 } 1750 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1751 1752 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1753 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 1754} 1755 1756void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1757 SDValue &Lo, SDValue &Hi) { 1758 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1759 DebugLoc dl = N->getDebugLoc(); 1760 SDValue Op = N->getOperand(0); 1761 if (Op.getValueType().bitsLE(NVT)) { 1762 // The low part is sign extension of the input (degenerates to a copy). 1763 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 1764 // The high part is obtained by SRA'ing all but one of the bits of low part. 1765 unsigned LoSize = NVT.getSizeInBits(); 1766 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1767 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1768 } else { 1769 // For example, extension of an i48 to an i64. The operand type necessarily 1770 // promotes to the result type, so will end up being expanded too. 1771 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1772 "Only know how to promote this result!"); 1773 SDValue Res = GetPromotedInteger(Op); 1774 assert(Res.getValueType() == N->getValueType(0) && 1775 "Operand over promoted?"); 1776 // Split the promoted operand. This will simplify when it is expanded. 1777 SplitInteger(Res, Lo, Hi); 1778 unsigned ExcessBits = 1779 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1780 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1781 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1782 } 1783} 1784 1785void DAGTypeLegalizer:: 1786ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1787 DebugLoc dl = N->getDebugLoc(); 1788 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1789 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1790 1791 if (EVT.bitsLE(Lo.getValueType())) { 1792 // sext_inreg the low part if needed. 1793 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 1794 N->getOperand(1)); 1795 1796 // The high part gets the sign extension from the lo-part. This handles 1797 // things like sextinreg V:i64 from i8. 1798 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 1799 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1800 TLI.getPointerTy())); 1801 } else { 1802 // For example, extension of an i48 to an i64. Leave the low part alone, 1803 // sext_inreg the high part. 1804 unsigned ExcessBits = 1805 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1806 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1807 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1808 } 1809} 1810 1811void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1812 SDValue &Lo, SDValue &Hi) { 1813 MVT VT = N->getValueType(0); 1814 DebugLoc dl = N->getDebugLoc(); 1815 1816 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1817 if (VT == MVT::i32) 1818 LC = RTLIB::SREM_I32; 1819 else if (VT == MVT::i64) 1820 LC = RTLIB::SREM_I64; 1821 else if (VT == MVT::i128) 1822 LC = RTLIB::SREM_I128; 1823 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1824 1825 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1826 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1827} 1828 1829void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1830 SDValue &Lo, SDValue &Hi) { 1831 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1832 DebugLoc dl = N->getDebugLoc(); 1833 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 1834 Hi = DAG.getNode(ISD::SRL, dl, 1835 N->getOperand(0).getValueType(), N->getOperand(0), 1836 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 1837 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 1838} 1839 1840void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1841 SDValue &Lo, SDValue &Hi) { 1842 MVT VT = N->getValueType(0); 1843 DebugLoc dl = N->getDebugLoc(); 1844 1845 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1846 if (VT == MVT::i32) 1847 LC = RTLIB::UDIV_I32; 1848 else if (VT == MVT::i64) 1849 LC = RTLIB::UDIV_I64; 1850 else if (VT == MVT::i128) 1851 LC = RTLIB::UDIV_I128; 1852 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1853 1854 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1855 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1856} 1857 1858void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1859 SDValue &Lo, SDValue &Hi) { 1860 MVT VT = N->getValueType(0); 1861 DebugLoc dl = N->getDebugLoc(); 1862 1863 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1864 if (VT == MVT::i32) 1865 LC = RTLIB::UREM_I32; 1866 else if (VT == MVT::i64) 1867 LC = RTLIB::UREM_I64; 1868 else if (VT == MVT::i128) 1869 LC = RTLIB::UREM_I128; 1870 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1871 1872 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1873 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1874} 1875 1876void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1877 SDValue &Lo, SDValue &Hi) { 1878 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1879 DebugLoc dl = N->getDebugLoc(); 1880 SDValue Op = N->getOperand(0); 1881 if (Op.getValueType().bitsLE(NVT)) { 1882 // The low part is zero extension of the input (degenerates to a copy). 1883 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 1884 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1885 } else { 1886 // For example, extension of an i48 to an i64. The operand type necessarily 1887 // promotes to the result type, so will end up being expanded too. 1888 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1889 "Only know how to promote this result!"); 1890 SDValue Res = GetPromotedInteger(Op); 1891 assert(Res.getValueType() == N->getValueType(0) && 1892 "Operand over promoted?"); 1893 // Split the promoted operand. This will simplify when it is expanded. 1894 SplitInteger(Res, Lo, Hi); 1895 unsigned ExcessBits = 1896 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1897 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1898 } 1899} 1900 1901 1902//===----------------------------------------------------------------------===// 1903// Integer Operand Expansion 1904//===----------------------------------------------------------------------===// 1905 1906/// ExpandIntegerOperand - This method is called when the specified operand of 1907/// the specified node is found to need expansion. At this point, all of the 1908/// result types of the node are known to be legal, but other operands of the 1909/// node may need promotion or expansion as well as the specified one. 1910bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1911 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1912 SDValue Res = SDValue(); 1913 1914 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false)) 1915 return false; 1916 1917 switch (N->getOpcode()) { 1918 default: 1919 #ifndef NDEBUG 1920 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1921 N->dump(&DAG); cerr << "\n"; 1922 #endif 1923 assert(0 && "Do not know how to expand this operator's operand!"); 1924 abort(); 1925 1926 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1927 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1928 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1929 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1930 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 1931 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 1932 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1933 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1934 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1935 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 1936 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1937 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1938 } 1939 1940 // If the result is null, the sub-method took care of registering results etc. 1941 if (!Res.getNode()) return false; 1942 1943 // If the result is N, the sub-method updated N in place. Tell the legalizer 1944 // core about this. 1945 if (Res.getNode() == N) 1946 return true; 1947 1948 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1949 "Invalid operand expansion"); 1950 1951 ReplaceValueWith(SDValue(N, 0), Res); 1952 return false; 1953} 1954 1955/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1956/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1957void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1958 SDValue &NewRHS, 1959 ISD::CondCode &CCCode, 1960 DebugLoc dl) { 1961 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1962 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1963 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1964 1965 MVT VT = NewLHS.getValueType(); 1966 1967 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1968 if (RHSLo == RHSHi) { 1969 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1970 if (RHSCST->isAllOnesValue()) { 1971 // Equality comparison to -1. 1972 NewLHS = DAG.getNode(ISD::AND, dl, 1973 LHSLo.getValueType(), LHSLo, LHSHi); 1974 NewRHS = RHSLo; 1975 return; 1976 } 1977 } 1978 } 1979 1980 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 1981 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 1982 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 1983 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1984 return; 1985 } 1986 1987 // If this is a comparison of the sign bit, just look at the top part. 1988 // X > -1, x < 0 1989 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1990 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1991 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1992 NewLHS = LHSHi; 1993 NewRHS = RHSHi; 1994 return; 1995 } 1996 1997 // FIXME: This generated code sucks. 1998 ISD::CondCode LowCC; 1999 switch (CCCode) { 2000 default: assert(0 && "Unknown integer setcc!"); 2001 case ISD::SETLT: 2002 case ISD::SETULT: LowCC = ISD::SETULT; break; 2003 case ISD::SETGT: 2004 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2005 case ISD::SETLE: 2006 case ISD::SETULE: LowCC = ISD::SETULE; break; 2007 case ISD::SETGE: 2008 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2009 } 2010 2011 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2012 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2013 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2014 2015 // NOTE: on targets without efficient SELECT of bools, we can always use 2016 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2017 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 2018 SDValue Tmp1, Tmp2; 2019 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2020 LHSLo, RHSLo, LowCC, false, DagCombineInfo); 2021 if (!Tmp1.getNode()) 2022 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2023 LHSLo, RHSLo, LowCC); 2024 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2025 LHSHi, RHSHi, CCCode, false, DagCombineInfo); 2026 if (!Tmp2.getNode()) 2027 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2028 TLI.getSetCCResultType(LHSHi.getValueType()), 2029 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2030 2031 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2032 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2033 if ((Tmp1C && Tmp1C->isNullValue()) || 2034 (Tmp2C && Tmp2C->isNullValue() && 2035 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2036 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2037 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2038 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2039 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2040 // low part is known false, returns high part. 2041 // For LE / GE, if high part is known false, ignore the low part. 2042 // For LT / GT, if high part is known true, ignore the low part. 2043 NewLHS = Tmp2; 2044 NewRHS = SDValue(); 2045 return; 2046 } 2047 2048 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2049 LHSHi, RHSHi, ISD::SETEQ, false, DagCombineInfo); 2050 if (!NewLHS.getNode()) 2051 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2052 LHSHi, RHSHi, ISD::SETEQ); 2053 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2054 NewLHS, Tmp1, Tmp2); 2055 NewRHS = SDValue(); 2056} 2057 2058SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2059 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2060 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2061 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2062 2063 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2064 // against zero to select between true and false values. 2065 if (NewRHS.getNode() == 0) { 2066 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2067 CCCode = ISD::SETNE; 2068 } 2069 2070 // Update N to have the operands specified. 2071 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2072 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2073 N->getOperand(4)); 2074} 2075 2076SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2077 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2078 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2079 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2080 2081 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2082 // against zero to select between true and false values. 2083 if (NewRHS.getNode() == 0) { 2084 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2085 CCCode = ISD::SETNE; 2086 } 2087 2088 // Update N to have the operands specified. 2089 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2090 N->getOperand(2), N->getOperand(3), 2091 DAG.getCondCode(CCCode)); 2092} 2093 2094SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2095 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2096 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2097 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2098 2099 // If ExpandSetCCOperands returned a scalar, use it. 2100 if (NewRHS.getNode() == 0) { 2101 assert(NewLHS.getValueType() == N->getValueType(0) && 2102 "Unexpected setcc expansion!"); 2103 return NewLHS; 2104 } 2105 2106 // Otherwise, update N to have the operands specified. 2107 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2108 DAG.getCondCode(CCCode)); 2109} 2110 2111SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2112 SDValue Op = N->getOperand(0); 2113 MVT DstVT = N->getValueType(0); 2114 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2115 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2116 "Don't know how to expand this SINT_TO_FP!"); 2117 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2118} 2119 2120SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2121 if (ISD::isNormalStore(N)) 2122 return ExpandOp_NormalStore(N, OpNo); 2123 2124 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2125 assert(OpNo == 1 && "Can only expand the stored value so far"); 2126 2127 MVT VT = N->getOperand(1).getValueType(); 2128 MVT NVT = TLI.getTypeToTransformTo(VT); 2129 SDValue Ch = N->getChain(); 2130 SDValue Ptr = N->getBasePtr(); 2131 int SVOffset = N->getSrcValueOffset(); 2132 unsigned Alignment = N->getAlignment(); 2133 bool isVolatile = N->isVolatile(); 2134 DebugLoc dl = N->getDebugLoc(); 2135 SDValue Lo, Hi; 2136 2137 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2138 2139 if (N->getMemoryVT().bitsLE(NVT)) { 2140 GetExpandedInteger(N->getValue(), Lo, Hi); 2141 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2142 N->getMemoryVT(), isVolatile, Alignment); 2143 } else if (TLI.isLittleEndian()) { 2144 // Little-endian - low bits are at low addresses. 2145 GetExpandedInteger(N->getValue(), Lo, Hi); 2146 2147 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2148 isVolatile, Alignment); 2149 2150 unsigned ExcessBits = 2151 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2152 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2153 2154 // Increment the pointer to the other half. 2155 unsigned IncrementSize = NVT.getSizeInBits()/8; 2156 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2157 DAG.getIntPtrConstant(IncrementSize)); 2158 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2159 SVOffset+IncrementSize, NEVT, 2160 isVolatile, MinAlign(Alignment, IncrementSize)); 2161 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2162 } else { 2163 // Big-endian - high bits are at low addresses. Favor aligned stores at 2164 // the cost of some bit-fiddling. 2165 GetExpandedInteger(N->getValue(), Lo, Hi); 2166 2167 MVT EVT = N->getMemoryVT(); 2168 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2169 unsigned IncrementSize = NVT.getSizeInBits()/8; 2170 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2171 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2172 2173 if (ExcessBits < NVT.getSizeInBits()) { 2174 // Transfer high bits from the top of Lo to the bottom of Hi. 2175 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2176 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2177 TLI.getPointerTy())); 2178 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2179 DAG.getNode(ISD::SRL, NVT, Lo, 2180 DAG.getConstant(ExcessBits, 2181 TLI.getPointerTy()))); 2182 } 2183 2184 // Store both the high bits and maybe some of the low bits. 2185 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2186 SVOffset, HiVT, isVolatile, Alignment); 2187 2188 // Increment the pointer to the other half. 2189 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2190 DAG.getIntPtrConstant(IncrementSize)); 2191 // Store the lowest ExcessBits bits in the second half. 2192 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), 2193 SVOffset+IncrementSize, 2194 MVT::getIntegerVT(ExcessBits), 2195 isVolatile, MinAlign(Alignment, IncrementSize)); 2196 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2197 } 2198} 2199 2200SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2201 SDValue InL, InH; 2202 GetExpandedInteger(N->getOperand(0), InL, InH); 2203 // Just truncate the low part of the source. 2204 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2205} 2206 2207SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2208 SDValue Op = N->getOperand(0); 2209 MVT SrcVT = Op.getValueType(); 2210 MVT DstVT = N->getValueType(0); 2211 DebugLoc dl = N->getDebugLoc(); 2212 2213 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2214 // Do a signed conversion then adjust the result. 2215 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2216 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2217 2218 // The result of the signed conversion needs adjusting if the 'sign bit' of 2219 // the incoming integer was set. To handle this, we dynamically test to see 2220 // if it is set, and, if so, add a fudge factor. 2221 2222 const uint64_t F32TwoE32 = 0x4F800000ULL; 2223 const uint64_t F32TwoE64 = 0x5F800000ULL; 2224 const uint64_t F32TwoE128 = 0x7F800000ULL; 2225 2226 APInt FF(32, 0); 2227 if (SrcVT == MVT::i32) 2228 FF = APInt(32, F32TwoE32); 2229 else if (SrcVT == MVT::i64) 2230 FF = APInt(32, F32TwoE64); 2231 else if (SrcVT == MVT::i128) 2232 FF = APInt(32, F32TwoE128); 2233 else 2234 assert(false && "Unsupported UINT_TO_FP!"); 2235 2236 // Check whether the sign bit is set. 2237 SDValue Lo, Hi; 2238 GetExpandedInteger(Op, Lo, Hi); 2239 SDValue SignSet = DAG.getSetCC(dl, 2240 TLI.getSetCCResultType(Hi.getValueType()), 2241 Hi, DAG.getConstant(0, Hi.getValueType()), 2242 ISD::SETLT); 2243 2244 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2245 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2246 TLI.getPointerTy()); 2247 2248 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2249 SDValue Zero = DAG.getIntPtrConstant(0); 2250 SDValue Four = DAG.getIntPtrConstant(4); 2251 if (TLI.isBigEndian()) std::swap(Zero, Four); 2252 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2253 Zero, Four); 2254 unsigned Alignment = 2255 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2256 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2257 Alignment = std::min(Alignment, 4u); 2258 2259 // Load the value out, extending it from f32 to the destination float type. 2260 // FIXME: Avoid the extend by constructing the right constant pool? 2261 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2262 FudgePtr, NULL, 0, MVT::f32, 2263 false, Alignment); 2264 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2265 } 2266 2267 // Otherwise, use a libcall. 2268 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2269 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2270 "Don't know how to expand this UINT_TO_FP!"); 2271 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2272} 2273