ARMBaseInstrInfo.cpp revision 14f1d4e74bd52b044a2c2bb6dd8df20b0480e633 
1//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Base ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMGenInstrInfo.inc"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalValue.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/CodeGen/LiveVariables.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineJumpTableInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37using namespace llvm;
38
39static cl::opt<bool>
40EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41               cl::desc("Enable ARM 2-addr to 3-addr conv"));
42
43ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
45    Subtarget(STI) {
46}
47
48MachineInstr *
49ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50                                        MachineBasicBlock::iterator &MBBI,
51                                        LiveVariables *LV) const {
52  // FIXME: Thumb2 support.
53
54  if (!EnableARM3Addr)
55    return NULL;
56
57  MachineInstr *MI = MBBI;
58  MachineFunction &MF = *MI->getParent()->getParent();
59  uint64_t TSFlags = MI->getDesc().TSFlags;
60  bool isPre = false;
61  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62  default: return NULL;
63  case ARMII::IndexModePre:
64    isPre = true;
65    break;
66  case ARMII::IndexModePost:
67    break;
68  }
69
70  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71  // operation.
72  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
73  if (MemOpc == 0)
74    return NULL;
75
76  MachineInstr *UpdateMI = NULL;
77  MachineInstr *MemMI = NULL;
78  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79  const TargetInstrDesc &TID = MI->getDesc();
80  unsigned NumOps = TID.getNumOperands();
81  bool isLoad = !TID.mayStore();
82  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83  const MachineOperand &Base = MI->getOperand(2);
84  const MachineOperand &Offset = MI->getOperand(NumOps-3);
85  unsigned WBReg = WB.getReg();
86  unsigned BaseReg = Base.getReg();
87  unsigned OffReg = Offset.getReg();
88  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
90  switch (AddrMode) {
91  default:
92    assert(false && "Unknown indexed op!");
93    return NULL;
94  case ARMII::AddrMode2: {
95    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97    if (OffReg == 0) {
98      if (ARM_AM::getSOImmVal(Amt) == -1)
99        // Can't encode it in a so_imm operand. This transformation will
100        // add more than 1 instruction. Abandon!
101        return NULL;
102      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104        .addReg(BaseReg).addImm(Amt)
105        .addImm(Pred).addReg(0).addReg(0);
106    } else if (Amt != 0) {
107      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112        .addImm(Pred).addReg(0).addReg(0);
113    } else
114      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116        .addReg(BaseReg).addReg(OffReg)
117        .addImm(Pred).addReg(0).addReg(0);
118    break;
119  }
120  case ARMII::AddrMode3 : {
121    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123    if (OffReg == 0)
124      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127        .addReg(BaseReg).addImm(Amt)
128        .addImm(Pred).addReg(0).addReg(0);
129    else
130      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132        .addReg(BaseReg).addReg(OffReg)
133        .addImm(Pred).addReg(0).addReg(0);
134    break;
135  }
136  }
137
138  std::vector<MachineInstr*> NewMIs;
139  if (isPre) {
140    if (isLoad)
141      MemMI = BuildMI(MF, MI->getDebugLoc(),
142                      get(MemOpc), MI->getOperand(0).getReg())
143        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144    else
145      MemMI = BuildMI(MF, MI->getDebugLoc(),
146                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
147        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148    NewMIs.push_back(MemMI);
149    NewMIs.push_back(UpdateMI);
150  } else {
151    if (isLoad)
152      MemMI = BuildMI(MF, MI->getDebugLoc(),
153                      get(MemOpc), MI->getOperand(0).getReg())
154        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155    else
156      MemMI = BuildMI(MF, MI->getDebugLoc(),
157                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
158        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159    if (WB.isDead())
160      UpdateMI->getOperand(0).setIsDead();
161    NewMIs.push_back(UpdateMI);
162    NewMIs.push_back(MemMI);
163  }
164
165  // Transfer LiveVariables states, kill / dead info.
166  if (LV) {
167    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168      MachineOperand &MO = MI->getOperand(i);
169      if (MO.isReg() && MO.getReg() &&
170          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171        unsigned Reg = MO.getReg();
172
173        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174        if (MO.isDef()) {
175          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176          if (MO.isDead())
177            LV->addVirtualRegisterDead(Reg, NewMI);
178        }
179        if (MO.isUse() && MO.isKill()) {
180          for (unsigned j = 0; j < 2; ++j) {
181            // Look at the two new MI's in reverse order.
182            MachineInstr *NewMI = NewMIs[j];
183            if (!NewMI->readsRegister(Reg))
184              continue;
185            LV->addVirtualRegisterKilled(Reg, NewMI);
186            if (VI.removeKill(MI))
187              VI.Kills.push_back(NewMI);
188            break;
189          }
190        }
191      }
192    }
193  }
194
195  MFI->insert(MBBI, NewMIs[1]);
196  MFI->insert(MBBI, NewMIs[0]);
197  return NewMIs[0];
198}
199
200bool
201ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202                                        MachineBasicBlock::iterator MI,
203                                        const std::vector<CalleeSavedInfo> &CSI,
204                                        const TargetRegisterInfo *TRI) const {
205  if (CSI.empty())
206    return false;
207
208  DebugLoc DL;
209  if (MI != MBB.end()) DL = MI->getDebugLoc();
210
211  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212    unsigned Reg = CSI[i].getReg();
213    bool isKill = true;
214
215    // Add the callee-saved register as live-in unless it's LR and
216    // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217    // then it's already added to the function and entry block live-in sets.
218    if (Reg == ARM::LR) {
219      MachineFunction &MF = *MBB.getParent();
220      if (MF.getFrameInfo()->isReturnAddressTaken() &&
221          MF.getRegInfo().isLiveIn(Reg))
222        isKill = false;
223    }
224
225    if (isKill)
226      MBB.addLiveIn(Reg);
227
228    // Insert the spill to the stack frame. The register is killed at the spill
229    //
230    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
231    storeRegToStackSlot(MBB, MI, Reg, isKill,
232                        CSI[i].getFrameIdx(), RC, TRI);
233  }
234  return true;
235}
236
237// Branch analysis.
238bool
239ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
240                                MachineBasicBlock *&FBB,
241                                SmallVectorImpl<MachineOperand> &Cond,
242                                bool AllowModify) const {
243  // If the block has no terminators, it just falls into the block after it.
244  MachineBasicBlock::iterator I = MBB.end();
245  if (I == MBB.begin())
246    return false;
247  --I;
248  while (I->isDebugValue()) {
249    if (I == MBB.begin())
250      return false;
251    --I;
252  }
253  if (!isUnpredicatedTerminator(I))
254    return false;
255
256  // Get the last instruction in the block.
257  MachineInstr *LastInst = I;
258
259  // If there is only one terminator instruction, process it.
260  unsigned LastOpc = LastInst->getOpcode();
261  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
262    if (isUncondBranchOpcode(LastOpc)) {
263      TBB = LastInst->getOperand(0).getMBB();
264      return false;
265    }
266    if (isCondBranchOpcode(LastOpc)) {
267      // Block ends with fall-through condbranch.
268      TBB = LastInst->getOperand(0).getMBB();
269      Cond.push_back(LastInst->getOperand(1));
270      Cond.push_back(LastInst->getOperand(2));
271      return false;
272    }
273    return true;  // Can't handle indirect branch.
274  }
275
276  // Get the instruction before it if it is a terminator.
277  MachineInstr *SecondLastInst = I;
278
279  // If there are three terminators, we don't know what sort of block this is.
280  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
281    return true;
282
283  // If the block ends with a B and a Bcc, handle it.
284  unsigned SecondLastOpc = SecondLastInst->getOpcode();
285  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
286    TBB =  SecondLastInst->getOperand(0).getMBB();
287    Cond.push_back(SecondLastInst->getOperand(1));
288    Cond.push_back(SecondLastInst->getOperand(2));
289    FBB = LastInst->getOperand(0).getMBB();
290    return false;
291  }
292
293  // If the block ends with two unconditional branches, handle it.  The second
294  // one is not executed, so remove it.
295  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
296    TBB = SecondLastInst->getOperand(0).getMBB();
297    I = LastInst;
298    if (AllowModify)
299      I->eraseFromParent();
300    return false;
301  }
302
303  // ...likewise if it ends with a branch table followed by an unconditional
304  // branch. The branch folder can create these, and we must get rid of them for
305  // correctness of Thumb constant islands.
306  if ((isJumpTableBranchOpcode(SecondLastOpc) ||
307       isIndirectBranchOpcode(SecondLastOpc)) &&
308      isUncondBranchOpcode(LastOpc)) {
309    I = LastInst;
310    if (AllowModify)
311      I->eraseFromParent();
312    return true;
313  }
314
315  // Otherwise, can't handle this.
316  return true;
317}
318
319
320unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
321  MachineBasicBlock::iterator I = MBB.end();
322  if (I == MBB.begin()) return 0;
323  --I;
324  while (I->isDebugValue()) {
325    if (I == MBB.begin())
326      return 0;
327    --I;
328  }
329  if (!isUncondBranchOpcode(I->getOpcode()) &&
330      !isCondBranchOpcode(I->getOpcode()))
331    return 0;
332
333  // Remove the branch.
334  I->eraseFromParent();
335
336  I = MBB.end();
337
338  if (I == MBB.begin()) return 1;
339  --I;
340  if (!isCondBranchOpcode(I->getOpcode()))
341    return 1;
342
343  // Remove the branch.
344  I->eraseFromParent();
345  return 2;
346}
347
348unsigned
349ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
350                            MachineBasicBlock *FBB,
351                            const SmallVectorImpl<MachineOperand> &Cond) const {
352  // FIXME this should probably have a DebugLoc argument
353  DebugLoc dl;
354
355  ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
356  int BOpc   = !AFI->isThumbFunction()
357    ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
358  int BccOpc = !AFI->isThumbFunction()
359    ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
360
361  // Shouldn't be a fall through.
362  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
363  assert((Cond.size() == 2 || Cond.size() == 0) &&
364         "ARM branch conditions have two components!");
365
366  if (FBB == 0) {
367    if (Cond.empty()) // Unconditional branch?
368      BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
369    else
370      BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
371        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
372    return 1;
373  }
374
375  // Two-way conditional branch.
376  BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
377    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
378  BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
379  return 2;
380}
381
382bool ARMBaseInstrInfo::
383ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
384  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
385  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
386  return false;
387}
388
389bool ARMBaseInstrInfo::
390PredicateInstruction(MachineInstr *MI,
391                     const SmallVectorImpl<MachineOperand> &Pred) const {
392  unsigned Opc = MI->getOpcode();
393  if (isUncondBranchOpcode(Opc)) {
394    MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
395    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
396    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
397    return true;
398  }
399
400  int PIdx = MI->findFirstPredOperandIdx();
401  if (PIdx != -1) {
402    MachineOperand &PMO = MI->getOperand(PIdx);
403    PMO.setImm(Pred[0].getImm());
404    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
405    return true;
406  }
407  return false;
408}
409
410bool ARMBaseInstrInfo::
411SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
412                  const SmallVectorImpl<MachineOperand> &Pred2) const {
413  if (Pred1.size() > 2 || Pred2.size() > 2)
414    return false;
415
416  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
417  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
418  if (CC1 == CC2)
419    return true;
420
421  switch (CC1) {
422  default:
423    return false;
424  case ARMCC::AL:
425    return true;
426  case ARMCC::HS:
427    return CC2 == ARMCC::HI;
428  case ARMCC::LS:
429    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
430  case ARMCC::GE:
431    return CC2 == ARMCC::GT;
432  case ARMCC::LE:
433    return CC2 == ARMCC::LT;
434  }
435}
436
437bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
438                                    std::vector<MachineOperand> &Pred) const {
439  // FIXME: This confuses implicit_def with optional CPSR def.
440  const TargetInstrDesc &TID = MI->getDesc();
441  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
442    return false;
443
444  bool Found = false;
445  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
446    const MachineOperand &MO = MI->getOperand(i);
447    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
448      Pred.push_back(MO);
449      Found = true;
450    }
451  }
452
453  return Found;
454}
455
456/// isPredicable - Return true if the specified instruction can be predicated.
457/// By default, this returns true for every instruction with a
458/// PredicateOperand.
459bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
460  const TargetInstrDesc &TID = MI->getDesc();
461  if (!TID.isPredicable())
462    return false;
463
464  if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
465    ARMFunctionInfo *AFI =
466      MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
467    return AFI->isThumb2Function();
468  }
469  return true;
470}
471
472/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
473DISABLE_INLINE
474static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
475                                unsigned JTI);
476static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
477                                unsigned JTI) {
478  assert(JTI < JT.size());
479  return JT[JTI].MBBs.size();
480}
481
482/// GetInstSize - Return the size of the specified MachineInstr.
483///
484unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
485  const MachineBasicBlock &MBB = *MI->getParent();
486  const MachineFunction *MF = MBB.getParent();
487  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
488
489  // Basic size info comes from the TSFlags field.
490  const TargetInstrDesc &TID = MI->getDesc();
491  uint64_t TSFlags = TID.TSFlags;
492
493  unsigned Opc = MI->getOpcode();
494  switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
495  default: {
496    // If this machine instr is an inline asm, measure it.
497    if (MI->getOpcode() == ARM::INLINEASM)
498      return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
499    if (MI->isLabel())
500      return 0;
501    switch (Opc) {
502    default:
503      llvm_unreachable("Unknown or unset size field for instr!");
504    case TargetOpcode::IMPLICIT_DEF:
505    case TargetOpcode::KILL:
506    case TargetOpcode::DBG_LABEL:
507    case TargetOpcode::EH_LABEL:
508    case TargetOpcode::DBG_VALUE:
509      return 0;
510    }
511    break;
512  }
513  case ARMII::Size8Bytes: return 8;          // ARM instruction x 2.
514  case ARMII::Size4Bytes: return 4;          // ARM / Thumb2 instruction.
515  case ARMII::Size2Bytes: return 2;          // Thumb1 instruction.
516  case ARMII::SizeSpecial: {
517    switch (Opc) {
518    case ARM::CONSTPOOL_ENTRY:
519      // If this machine instr is a constant pool entry, its size is recorded as
520      // operand #2.
521      return MI->getOperand(2).getImm();
522    case ARM::Int_eh_sjlj_longjmp:
523      return 16;
524    case ARM::tInt_eh_sjlj_longjmp:
525      return 10;
526    case ARM::Int_eh_sjlj_setjmp:
527    case ARM::Int_eh_sjlj_setjmp_nofp:
528      return 20;
529    case ARM::tInt_eh_sjlj_setjmp:
530    case ARM::t2Int_eh_sjlj_setjmp:
531    case ARM::t2Int_eh_sjlj_setjmp_nofp:
532      return 12;
533    case ARM::BR_JTr:
534    case ARM::BR_JTm:
535    case ARM::BR_JTadd:
536    case ARM::tBR_JTr:
537    case ARM::t2BR_JT:
538    case ARM::t2TBB:
539    case ARM::t2TBH: {
540      // These are jumptable branches, i.e. a branch followed by an inlined
541      // jumptable. The size is 4 + 4 * number of entries. For TBB, each
542      // entry is one byte; TBH two byte each.
543      unsigned EntrySize = (Opc == ARM::t2TBB)
544        ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
545      unsigned NumOps = TID.getNumOperands();
546      MachineOperand JTOP =
547        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
548      unsigned JTI = JTOP.getIndex();
549      const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
550      assert(MJTI != 0);
551      const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
552      assert(JTI < JT.size());
553      // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
554      // 4 aligned. The assembler / linker may add 2 byte padding just before
555      // the JT entries.  The size does not include this padding; the
556      // constant islands pass does separate bookkeeping for it.
557      // FIXME: If we know the size of the function is less than (1 << 16) *2
558      // bytes, we can use 16-bit entries instead. Then there won't be an
559      // alignment issue.
560      unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
561      unsigned NumEntries = getNumJTEntries(JT, JTI);
562      if (Opc == ARM::t2TBB && (NumEntries & 1))
563        // Make sure the instruction that follows TBB is 2-byte aligned.
564        // FIXME: Constant island pass should insert an "ALIGN" instruction
565        // instead.
566        ++NumEntries;
567      return NumEntries * EntrySize + InstSize;
568    }
569    default:
570      // Otherwise, pseudo-instruction sizes are zero.
571      return 0;
572    }
573  }
574  }
575  return 0; // Not reached
576}
577
578/// Return true if the instruction is a register to register move and
579/// leave the source and dest operands in the passed parameters.
580///
581bool
582ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
583                              unsigned &SrcReg, unsigned &DstReg,
584                              unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
585  switch (MI.getOpcode()) {
586  default: break;
587  case ARM::VMOVS:
588  case ARM::VMOVD:
589  case ARM::VMOVDneon:
590  case ARM::VMOVQ:
591  case ARM::VMOVQQ : {
592    SrcReg = MI.getOperand(1).getReg();
593    DstReg = MI.getOperand(0).getReg();
594    SrcSubIdx = MI.getOperand(1).getSubReg();
595    DstSubIdx = MI.getOperand(0).getSubReg();
596    return true;
597  }
598  case ARM::MOVr:
599  case ARM::tMOVr:
600  case ARM::tMOVgpr2tgpr:
601  case ARM::tMOVtgpr2gpr:
602  case ARM::tMOVgpr2gpr:
603  case ARM::t2MOVr: {
604    assert(MI.getDesc().getNumOperands() >= 2 &&
605           MI.getOperand(0).isReg() &&
606           MI.getOperand(1).isReg() &&
607           "Invalid ARM MOV instruction");
608    SrcReg = MI.getOperand(1).getReg();
609    DstReg = MI.getOperand(0).getReg();
610    SrcSubIdx = MI.getOperand(1).getSubReg();
611    DstSubIdx = MI.getOperand(0).getSubReg();
612    return true;
613  }
614  }
615
616  return false;
617}
618
619unsigned
620ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
621                                      int &FrameIndex) const {
622  switch (MI->getOpcode()) {
623  default: break;
624  case ARM::LDR:
625  case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
626    if (MI->getOperand(1).isFI() &&
627        MI->getOperand(2).isReg() &&
628        MI->getOperand(3).isImm() &&
629        MI->getOperand(2).getReg() == 0 &&
630        MI->getOperand(3).getImm() == 0) {
631      FrameIndex = MI->getOperand(1).getIndex();
632      return MI->getOperand(0).getReg();
633    }
634    break;
635  case ARM::t2LDRi12:
636  case ARM::tRestore:
637    if (MI->getOperand(1).isFI() &&
638        MI->getOperand(2).isImm() &&
639        MI->getOperand(2).getImm() == 0) {
640      FrameIndex = MI->getOperand(1).getIndex();
641      return MI->getOperand(0).getReg();
642    }
643    break;
644  case ARM::VLDRD:
645  case ARM::VLDRS:
646    if (MI->getOperand(1).isFI() &&
647        MI->getOperand(2).isImm() &&
648        MI->getOperand(2).getImm() == 0) {
649      FrameIndex = MI->getOperand(1).getIndex();
650      return MI->getOperand(0).getReg();
651    }
652    break;
653  }
654
655  return 0;
656}
657
658unsigned
659ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
660                                     int &FrameIndex) const {
661  switch (MI->getOpcode()) {
662  default: break;
663  case ARM::STR:
664  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
665    if (MI->getOperand(1).isFI() &&
666        MI->getOperand(2).isReg() &&
667        MI->getOperand(3).isImm() &&
668        MI->getOperand(2).getReg() == 0 &&
669        MI->getOperand(3).getImm() == 0) {
670      FrameIndex = MI->getOperand(1).getIndex();
671      return MI->getOperand(0).getReg();
672    }
673    break;
674  case ARM::t2STRi12:
675  case ARM::tSpill:
676    if (MI->getOperand(1).isFI() &&
677        MI->getOperand(2).isImm() &&
678        MI->getOperand(2).getImm() == 0) {
679      FrameIndex = MI->getOperand(1).getIndex();
680      return MI->getOperand(0).getReg();
681    }
682    break;
683  case ARM::VSTRD:
684  case ARM::VSTRS:
685    if (MI->getOperand(1).isFI() &&
686        MI->getOperand(2).isImm() &&
687        MI->getOperand(2).getImm() == 0) {
688      FrameIndex = MI->getOperand(1).getIndex();
689      return MI->getOperand(0).getReg();
690    }
691    break;
692  }
693
694  return 0;
695}
696
697bool
698ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
699                               MachineBasicBlock::iterator I,
700                               unsigned DestReg, unsigned SrcReg,
701                               const TargetRegisterClass *DestRC,
702                               const TargetRegisterClass *SrcRC,
703                               DebugLoc DL) const {
704  // tGPR is used sometimes in ARM instructions that need to avoid using
705  // certain registers.  Just treat it as GPR here.
706  if (DestRC == ARM::tGPRRegisterClass)
707    DestRC = ARM::GPRRegisterClass;
708  if (SrcRC == ARM::tGPRRegisterClass)
709    SrcRC = ARM::GPRRegisterClass;
710
711  // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
712  if (DestRC == ARM::DPR_8RegisterClass)
713    DestRC = ARM::DPR_VFP2RegisterClass;
714  if (SrcRC == ARM::DPR_8RegisterClass)
715    SrcRC = ARM::DPR_VFP2RegisterClass;
716
717  // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
718  if (DestRC == ARM::QPR_VFP2RegisterClass ||
719      DestRC == ARM::QPR_8RegisterClass)
720    DestRC = ARM::QPRRegisterClass;
721  if (SrcRC == ARM::QPR_VFP2RegisterClass ||
722      SrcRC == ARM::QPR_8RegisterClass)
723    SrcRC = ARM::QPRRegisterClass;
724
725  // Allow QQPR / QQPR_VFP2 cross-class copies.
726  if (DestRC == ARM::QQPR_VFP2RegisterClass)
727    DestRC = ARM::QQPRRegisterClass;
728  if (SrcRC == ARM::QQPR_VFP2RegisterClass)
729    SrcRC = ARM::QQPRRegisterClass;
730
731  // Disallow copies of unequal sizes.
732  if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
733    return false;
734
735  if (DestRC == ARM::GPRRegisterClass) {
736    if (SrcRC == ARM::SPRRegisterClass)
737      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
738                     .addReg(SrcReg));
739    else
740      AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
741                                          DestReg).addReg(SrcReg)));
742  } else {
743    unsigned Opc;
744
745    if (DestRC == ARM::SPRRegisterClass)
746      Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
747    else if (DestRC == ARM::DPRRegisterClass)
748      Opc = ARM::VMOVD;
749    else if (DestRC == ARM::DPR_VFP2RegisterClass ||
750             SrcRC == ARM::DPR_VFP2RegisterClass)
751      // Always use neon reg-reg move if source or dest is NEON-only regclass.
752      Opc = ARM::VMOVDneon;
753    else if (DestRC == ARM::QPRRegisterClass)
754      Opc = ARM::VMOVQ;
755    else if (DestRC == ARM::QQPRRegisterClass)
756      Opc = ARM::VMOVQQ;
757    else if (DestRC == ARM::QQQQPRRegisterClass)
758      Opc = ARM::VMOVQQQQ;
759    else
760      return false;
761
762    MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
763    MIB.addReg(SrcReg);
764    if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
765      AddDefaultPred(MIB);
766  }
767
768  return true;
769}
770
771static const
772MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
773                             unsigned Reg, unsigned SubIdx, unsigned State,
774                             const TargetRegisterInfo *TRI) {
775  if (!SubIdx)
776    return MIB.addReg(Reg, State);
777
778  if (TargetRegisterInfo::isPhysicalRegister(Reg))
779    return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
780  return MIB.addReg(Reg, State, SubIdx);
781}
782
783void ARMBaseInstrInfo::
784storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
785                    unsigned SrcReg, bool isKill, int FI,
786                    const TargetRegisterClass *RC,
787                    const TargetRegisterInfo *TRI) const {
788  DebugLoc DL;
789  if (I != MBB.end()) DL = I->getDebugLoc();
790  MachineFunction &MF = *MBB.getParent();
791  MachineFrameInfo &MFI = *MF.getFrameInfo();
792  unsigned Align = MFI.getObjectAlignment(FI);
793
794  MachineMemOperand *MMO =
795    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
796                            MachineMemOperand::MOStore, 0,
797                            MFI.getObjectSize(FI),
798                            Align);
799
800  // tGPR is used sometimes in ARM instructions that need to avoid using
801  // certain registers.  Just treat it as GPR here.
802  if (RC == ARM::tGPRRegisterClass)
803    RC = ARM::GPRRegisterClass;
804
805  if (RC == ARM::GPRRegisterClass) {
806    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
807                   .addReg(SrcReg, getKillRegState(isKill))
808                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
809  } else if (RC == ARM::SPRRegisterClass) {
810    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
811                   .addReg(SrcReg, getKillRegState(isKill))
812                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
813  } else if (RC == ARM::DPRRegisterClass ||
814             RC == ARM::DPR_VFP2RegisterClass ||
815             RC == ARM::DPR_8RegisterClass) {
816    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
817                   .addReg(SrcReg, getKillRegState(isKill))
818                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
819  } else if (RC == ARM::QPRRegisterClass ||
820             RC == ARM::QPR_VFP2RegisterClass ||
821             RC == ARM::QPR_8RegisterClass) {
822    // FIXME: Neon instructions should support predicates
823    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
824      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
825                     .addFrameIndex(FI).addImm(128)
826                     .addReg(SrcReg, getKillRegState(isKill))
827                     .addMemOperand(MMO));
828    } else {
829      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
830                     .addReg(SrcReg, getKillRegState(isKill))
831                     .addFrameIndex(FI)
832                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
833                     .addMemOperand(MMO));
834    }
835  } else if (RC == ARM::QQPRRegisterClass || RC == ARM::QQPR_VFP2RegisterClass){
836    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
837      // FIXME: It's possible to only store part of the QQ register if the
838      // spilled def has a sub-register index.
839      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
840        .addFrameIndex(FI).addImm(128);
841      MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
842      MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
843      MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
844      MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
845      AddDefaultPred(MIB.addMemOperand(MMO));
846    } else {
847      MachineInstrBuilder MIB =
848        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
849                       .addFrameIndex(FI)
850                       .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
851        .addMemOperand(MMO);
852      MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
853      MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
854      MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
855            AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
856    }
857  } else {
858    assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!");
859    MachineInstrBuilder MIB =
860      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
861                     .addFrameIndex(FI)
862                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
863      .addMemOperand(MMO);
864    MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
865    MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
866    MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
867    MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
868    MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
869    MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
870    MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
871          AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
872  }
873}
874
875void ARMBaseInstrInfo::
876loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
877                     unsigned DestReg, int FI,
878                     const TargetRegisterClass *RC,
879                     const TargetRegisterInfo *TRI) const {
880  DebugLoc DL;
881  if (I != MBB.end()) DL = I->getDebugLoc();
882  MachineFunction &MF = *MBB.getParent();
883  MachineFrameInfo &MFI = *MF.getFrameInfo();
884  unsigned Align = MFI.getObjectAlignment(FI);
885  MachineMemOperand *MMO =
886    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
887                            MachineMemOperand::MOLoad, 0,
888                            MFI.getObjectSize(FI),
889                            Align);
890
891  // tGPR is used sometimes in ARM instructions that need to avoid using
892  // certain registers.  Just treat it as GPR here.
893  if (RC == ARM::tGPRRegisterClass)
894    RC = ARM::GPRRegisterClass;
895
896  if (RC == ARM::GPRRegisterClass) {
897    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
898                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
899  } else if (RC == ARM::SPRRegisterClass) {
900    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
901                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
902  } else if (RC == ARM::DPRRegisterClass ||
903             RC == ARM::DPR_VFP2RegisterClass ||
904             RC == ARM::DPR_8RegisterClass) {
905    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
906                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
907  } else if (RC == ARM::QPRRegisterClass ||
908             RC == ARM::QPR_VFP2RegisterClass ||
909             RC == ARM::QPR_8RegisterClass) {
910    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
911      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
912                     .addFrameIndex(FI).addImm(128)
913                     .addMemOperand(MMO));
914    } else {
915      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
916                     .addFrameIndex(FI)
917                     .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
918                     .addMemOperand(MMO));
919    }
920  } else if (RC == ARM::QQPRRegisterClass || RC == ARM::QQPR_VFP2RegisterClass){
921    if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
922      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
923      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
924      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
925      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
926      MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
927      AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
928    } else {
929      MachineInstrBuilder MIB =
930        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
931                       .addFrameIndex(FI)
932                       .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
933        .addMemOperand(MMO);
934      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
935      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
936      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
937            AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
938    }
939  } else {
940    assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!");
941      MachineInstrBuilder MIB =
942        AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
943                       .addFrameIndex(FI)
944                       .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
945        .addMemOperand(MMO);
946      MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
947      MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
948      MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
949      MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
950      MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
951      MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
952      MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
953            AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
954  }
955}
956
957MachineInstr*
958ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
959                                           int FrameIx, uint64_t Offset,
960                                           const MDNode *MDPtr,
961                                           DebugLoc DL) const {
962  MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
963    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
964  return &*MIB;
965}
966
967MachineInstr *ARMBaseInstrInfo::
968foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
969                      const SmallVectorImpl<unsigned> &Ops, int FI) const {
970  if (Ops.size() != 1) return NULL;
971
972  unsigned OpNum = Ops[0];
973  unsigned Opc = MI->getOpcode();
974  MachineInstr *NewMI = NULL;
975  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
976    // If it is updating CPSR, then it cannot be folded.
977    if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
978      return NULL;
979    unsigned Pred = MI->getOperand(2).getImm();
980    unsigned PredReg = MI->getOperand(3).getReg();
981    if (OpNum == 0) { // move -> store
982      unsigned SrcReg = MI->getOperand(1).getReg();
983      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
984      bool isKill = MI->getOperand(1).isKill();
985      bool isUndef = MI->getOperand(1).isUndef();
986      if (Opc == ARM::MOVr)
987        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
988          .addReg(SrcReg,
989                  getKillRegState(isKill) | getUndefRegState(isUndef),
990                  SrcSubReg)
991          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
992      else // ARM::t2MOVr
993        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
994          .addReg(SrcReg,
995                  getKillRegState(isKill) | getUndefRegState(isUndef),
996                  SrcSubReg)
997          .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
998    } else {          // move -> load
999      unsigned DstReg = MI->getOperand(0).getReg();
1000      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1001      bool isDead = MI->getOperand(0).isDead();
1002      bool isUndef = MI->getOperand(0).isUndef();
1003      if (Opc == ARM::MOVr)
1004        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
1005          .addReg(DstReg,
1006                  RegState::Define |
1007                  getDeadRegState(isDead) |
1008                  getUndefRegState(isUndef), DstSubReg)
1009          .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1010      else // ARM::t2MOVr
1011        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1012          .addReg(DstReg,
1013                  RegState::Define |
1014                  getDeadRegState(isDead) |
1015                  getUndefRegState(isUndef), DstSubReg)
1016          .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1017    }
1018  } else if (Opc == ARM::tMOVgpr2gpr ||
1019             Opc == ARM::tMOVtgpr2gpr ||
1020             Opc == ARM::tMOVgpr2tgpr) {
1021    if (OpNum == 0) { // move -> store
1022      unsigned SrcReg = MI->getOperand(1).getReg();
1023      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1024      bool isKill = MI->getOperand(1).isKill();
1025      bool isUndef = MI->getOperand(1).isUndef();
1026      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
1027        .addReg(SrcReg,
1028                getKillRegState(isKill) | getUndefRegState(isUndef),
1029                SrcSubReg)
1030        .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1031    } else {          // move -> load
1032      unsigned DstReg = MI->getOperand(0).getReg();
1033      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1034      bool isDead = MI->getOperand(0).isDead();
1035      bool isUndef = MI->getOperand(0).isUndef();
1036      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1037        .addReg(DstReg,
1038                RegState::Define |
1039                getDeadRegState(isDead) |
1040                getUndefRegState(isUndef),
1041                DstSubReg)
1042        .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1043    }
1044  } else if (Opc == ARM::VMOVS) {
1045    unsigned Pred = MI->getOperand(2).getImm();
1046    unsigned PredReg = MI->getOperand(3).getReg();
1047    if (OpNum == 0) { // move -> store
1048      unsigned SrcReg = MI->getOperand(1).getReg();
1049      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1050      bool isKill = MI->getOperand(1).isKill();
1051      bool isUndef = MI->getOperand(1).isUndef();
1052      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
1053        .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
1054                SrcSubReg)
1055        .addFrameIndex(FI)
1056        .addImm(0).addImm(Pred).addReg(PredReg);
1057    } else {          // move -> load
1058      unsigned DstReg = MI->getOperand(0).getReg();
1059      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1060      bool isDead = MI->getOperand(0).isDead();
1061      bool isUndef = MI->getOperand(0).isUndef();
1062      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
1063        .addReg(DstReg,
1064                RegState::Define |
1065                getDeadRegState(isDead) |
1066                getUndefRegState(isUndef),
1067                DstSubReg)
1068        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1069    }
1070  } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) {
1071    unsigned Pred = MI->getOperand(2).getImm();
1072    unsigned PredReg = MI->getOperand(3).getReg();
1073    if (OpNum == 0) { // move -> store
1074      unsigned SrcReg = MI->getOperand(1).getReg();
1075      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1076      bool isKill = MI->getOperand(1).isKill();
1077      bool isUndef = MI->getOperand(1).isUndef();
1078      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
1079        .addReg(SrcReg,
1080                getKillRegState(isKill) | getUndefRegState(isUndef),
1081                SrcSubReg)
1082        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1083    } else {          // move -> load
1084      unsigned DstReg = MI->getOperand(0).getReg();
1085      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1086      bool isDead = MI->getOperand(0).isDead();
1087      bool isUndef = MI->getOperand(0).isUndef();
1088      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
1089        .addReg(DstReg,
1090                RegState::Define |
1091                getDeadRegState(isDead) |
1092                getUndefRegState(isUndef),
1093                DstSubReg)
1094        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1095    }
1096  }  else if (Opc == ARM::VMOVQ) {
1097    MachineFrameInfo &MFI = *MF.getFrameInfo();
1098    unsigned Pred = MI->getOperand(2).getImm();
1099    unsigned PredReg = MI->getOperand(3).getReg();
1100    if (OpNum == 0) { // move -> store
1101      unsigned SrcReg = MI->getOperand(1).getReg();
1102      unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1103      bool isKill = MI->getOperand(1).isKill();
1104      bool isUndef = MI->getOperand(1).isUndef();
1105      if (MFI.getObjectAlignment(FI) >= 16 &&
1106          getRegisterInfo().canRealignStack(MF)) {
1107        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
1108          .addFrameIndex(FI).addImm(128)
1109          .addReg(SrcReg,
1110                  getKillRegState(isKill) | getUndefRegState(isUndef),
1111                  SrcSubReg)
1112          .addImm(Pred).addReg(PredReg);
1113      } else {
1114        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ))
1115          .addReg(SrcReg,
1116                  getKillRegState(isKill) | getUndefRegState(isUndef),
1117                  SrcSubReg)
1118          .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1119          .addImm(Pred).addReg(PredReg);
1120      }
1121    } else {          // move -> load
1122      unsigned DstReg = MI->getOperand(0).getReg();
1123      unsigned DstSubReg = MI->getOperand(0).getSubReg();
1124      bool isDead = MI->getOperand(0).isDead();
1125      bool isUndef = MI->getOperand(0).isUndef();
1126      if (MFI.getObjectAlignment(FI) >= 16 &&
1127          getRegisterInfo().canRealignStack(MF)) {
1128        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q))
1129          .addReg(DstReg,
1130                  RegState::Define |
1131                  getDeadRegState(isDead) |
1132                  getUndefRegState(isUndef),
1133                  DstSubReg)
1134          .addFrameIndex(FI).addImm(128).addImm(Pred).addReg(PredReg);
1135      } else {
1136        NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
1137          .addReg(DstReg,
1138                  RegState::Define |
1139                  getDeadRegState(isDead) |
1140                  getUndefRegState(isUndef),
1141                  DstSubReg)
1142          .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1143          .addImm(Pred).addReg(PredReg);
1144      }
1145    }
1146  }
1147
1148  return NewMI;
1149}
1150
1151MachineInstr*
1152ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
1153                                        MachineInstr* MI,
1154                                        const SmallVectorImpl<unsigned> &Ops,
1155                                        MachineInstr* LoadMI) const {
1156  // FIXME
1157  return 0;
1158}
1159
1160bool
1161ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
1162                                   const SmallVectorImpl<unsigned> &Ops) const {
1163  if (Ops.size() != 1) return false;
1164
1165  unsigned Opc = MI->getOpcode();
1166  if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
1167    // If it is updating CPSR, then it cannot be folded.
1168    return MI->getOperand(4).getReg() != ARM::CPSR ||
1169      MI->getOperand(4).isDead();
1170  } else if (Opc == ARM::tMOVgpr2gpr ||
1171             Opc == ARM::tMOVtgpr2gpr ||
1172             Opc == ARM::tMOVgpr2tgpr) {
1173    return true;
1174  } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD ||
1175             Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
1176    return true;
1177  }
1178
1179  // FIXME: VMOVQQ and VMOVQQQQ?
1180
1181  return false;
1182}
1183
1184/// Create a copy of a const pool value. Update CPI to the new index and return
1185/// the label UID.
1186static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1187  MachineConstantPool *MCP = MF.getConstantPool();
1188  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1189
1190  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1191  assert(MCPE.isMachineConstantPoolEntry() &&
1192         "Expecting a machine constantpool entry!");
1193  ARMConstantPoolValue *ACPV =
1194    static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1195
1196  unsigned PCLabelId = AFI->createConstPoolEntryUId();
1197  ARMConstantPoolValue *NewCPV = 0;
1198  if (ACPV->isGlobalValue())
1199    NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
1200                                      ARMCP::CPValue, 4);
1201  else if (ACPV->isExtSymbol())
1202    NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1203                                      ACPV->getSymbol(), PCLabelId, 4);
1204  else if (ACPV->isBlockAddress())
1205    NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
1206                                      ARMCP::CPBlockAddress, 4);
1207  else
1208    llvm_unreachable("Unexpected ARM constantpool value type!!");
1209  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1210  return PCLabelId;
1211}
1212
1213void ARMBaseInstrInfo::
1214reMaterialize(MachineBasicBlock &MBB,
1215              MachineBasicBlock::iterator I,
1216              unsigned DestReg, unsigned SubIdx,
1217              const MachineInstr *Orig,
1218              const TargetRegisterInfo &TRI) const {
1219  unsigned Opcode = Orig->getOpcode();
1220  switch (Opcode) {
1221  default: {
1222    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1223    MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1224    MBB.insert(I, MI);
1225    break;
1226  }
1227  case ARM::tLDRpci_pic:
1228  case ARM::t2LDRpci_pic: {
1229    MachineFunction &MF = *MBB.getParent();
1230    unsigned CPI = Orig->getOperand(1).getIndex();
1231    unsigned PCLabelId = duplicateCPV(MF, CPI);
1232    MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1233                                      DestReg)
1234      .addConstantPoolIndex(CPI).addImm(PCLabelId);
1235    (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1236    break;
1237  }
1238  }
1239}
1240
1241MachineInstr *
1242ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1243  MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1244  switch(Orig->getOpcode()) {
1245  case ARM::tLDRpci_pic:
1246  case ARM::t2LDRpci_pic: {
1247    unsigned CPI = Orig->getOperand(1).getIndex();
1248    unsigned PCLabelId = duplicateCPV(MF, CPI);
1249    Orig->getOperand(1).setIndex(CPI);
1250    Orig->getOperand(2).setImm(PCLabelId);
1251    break;
1252  }
1253  }
1254  return MI;
1255}
1256
1257bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1258                                        const MachineInstr *MI1) const {
1259  int Opcode = MI0->getOpcode();
1260  if (Opcode == ARM::t2LDRpci ||
1261      Opcode == ARM::t2LDRpci_pic ||
1262      Opcode == ARM::tLDRpci ||
1263      Opcode == ARM::tLDRpci_pic) {
1264    if (MI1->getOpcode() != Opcode)
1265      return false;
1266    if (MI0->getNumOperands() != MI1->getNumOperands())
1267      return false;
1268
1269    const MachineOperand &MO0 = MI0->getOperand(1);
1270    const MachineOperand &MO1 = MI1->getOperand(1);
1271    if (MO0.getOffset() != MO1.getOffset())
1272      return false;
1273
1274    const MachineFunction *MF = MI0->getParent()->getParent();
1275    const MachineConstantPool *MCP = MF->getConstantPool();
1276    int CPI0 = MO0.getIndex();
1277    int CPI1 = MO1.getIndex();
1278    const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1279    const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1280    ARMConstantPoolValue *ACPV0 =
1281      static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1282    ARMConstantPoolValue *ACPV1 =
1283      static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1284    return ACPV0->hasSameValue(ACPV1);
1285  }
1286
1287  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1288}
1289
1290/// getInstrPredicate - If instruction is predicated, returns its predicate
1291/// condition, otherwise returns AL. It also returns the condition code
1292/// register by reference.
1293ARMCC::CondCodes
1294llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1295  int PIdx = MI->findFirstPredOperandIdx();
1296  if (PIdx == -1) {
1297    PredReg = 0;
1298    return ARMCC::AL;
1299  }
1300
1301  PredReg = MI->getOperand(PIdx+1).getReg();
1302  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1303}
1304
1305
1306int llvm::getMatchingCondBranchOpcode(int Opc) {
1307  if (Opc == ARM::B)
1308    return ARM::Bcc;
1309  else if (Opc == ARM::tB)
1310    return ARM::tBcc;
1311  else if (Opc == ARM::t2B)
1312      return ARM::t2Bcc;
1313
1314  llvm_unreachable("Unknown unconditional branch opcode!");
1315  return 0;
1316}
1317
1318
1319void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1320                               MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1321                               unsigned DestReg, unsigned BaseReg, int NumBytes,
1322                               ARMCC::CondCodes Pred, unsigned PredReg,
1323                               const ARMBaseInstrInfo &TII) {
1324  bool isSub = NumBytes < 0;
1325  if (isSub) NumBytes = -NumBytes;
1326
1327  while (NumBytes) {
1328    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1329    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1330    assert(ThisVal && "Didn't extract field correctly");
1331
1332    // We will handle these bits from offset, clear them.
1333    NumBytes &= ~ThisVal;
1334
1335    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1336
1337    // Build the new ADD / SUB.
1338    unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1339    BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1340      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1341      .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1342    BaseReg = DestReg;
1343  }
1344}
1345
1346bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1347                                unsigned FrameReg, int &Offset,
1348                                const ARMBaseInstrInfo &TII) {
1349  unsigned Opcode = MI.getOpcode();
1350  const TargetInstrDesc &Desc = MI.getDesc();
1351  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1352  bool isSub = false;
1353
1354  // Memory operands in inline assembly always use AddrMode2.
1355  if (Opcode == ARM::INLINEASM)
1356    AddrMode = ARMII::AddrMode2;
1357
1358  if (Opcode == ARM::ADDri) {
1359    Offset += MI.getOperand(FrameRegIdx+1).getImm();
1360    if (Offset == 0) {
1361      // Turn it into a move.
1362      MI.setDesc(TII.get(ARM::MOVr));
1363      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1364      MI.RemoveOperand(FrameRegIdx+1);
1365      Offset = 0;
1366      return true;
1367    } else if (Offset < 0) {
1368      Offset = -Offset;
1369      isSub = true;
1370      MI.setDesc(TII.get(ARM::SUBri));
1371    }
1372
1373    // Common case: small offset, fits into instruction.
1374    if (ARM_AM::getSOImmVal(Offset) != -1) {
1375      // Replace the FrameIndex with sp / fp
1376      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1377      MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1378      Offset = 0;
1379      return true;
1380    }
1381
1382    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1383    // as possible.
1384    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1385    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1386
1387    // We will handle these bits from offset, clear them.
1388    Offset &= ~ThisImmVal;
1389
1390    // Get the properly encoded SOImmVal field.
1391    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1392           "Bit extraction didn't work?");
1393    MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1394 } else {
1395    unsigned ImmIdx = 0;
1396    int InstrOffs = 0;
1397    unsigned NumBits = 0;
1398    unsigned Scale = 1;
1399    switch (AddrMode) {
1400    case ARMII::AddrMode2: {
1401      ImmIdx = FrameRegIdx+2;
1402      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1403      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1404        InstrOffs *= -1;
1405      NumBits = 12;
1406      break;
1407    }
1408    case ARMII::AddrMode3: {
1409      ImmIdx = FrameRegIdx+2;
1410      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1411      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1412        InstrOffs *= -1;
1413      NumBits = 8;
1414      break;
1415    }
1416    case ARMII::AddrMode4:
1417    case ARMII::AddrMode6:
1418      // Can't fold any offset even if it's zero.
1419      return false;
1420    case ARMII::AddrMode5: {
1421      ImmIdx = FrameRegIdx+1;
1422      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1423      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1424        InstrOffs *= -1;
1425      NumBits = 8;
1426      Scale = 4;
1427      break;
1428    }
1429    default:
1430      llvm_unreachable("Unsupported addressing mode!");
1431      break;
1432    }
1433
1434    Offset += InstrOffs * Scale;
1435    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1436    if (Offset < 0) {
1437      Offset = -Offset;
1438      isSub = true;
1439    }
1440
1441    // Attempt to fold address comp. if opcode has offset bits
1442    if (NumBits > 0) {
1443      // Common case: small offset, fits into instruction.
1444      MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1445      int ImmedOffset = Offset / Scale;
1446      unsigned Mask = (1 << NumBits) - 1;
1447      if ((unsigned)Offset <= Mask * Scale) {
1448        // Replace the FrameIndex with sp
1449        MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1450        if (isSub)
1451          ImmedOffset |= 1 << NumBits;
1452        ImmOp.ChangeToImmediate(ImmedOffset);
1453        Offset = 0;
1454        return true;
1455      }
1456
1457      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1458      ImmedOffset = ImmedOffset & Mask;
1459      if (isSub)
1460        ImmedOffset |= 1 << NumBits;
1461      ImmOp.ChangeToImmediate(ImmedOffset);
1462      Offset &= ~(Mask*Scale);
1463    }
1464  }
1465
1466  Offset = (isSub) ? -Offset : Offset;
1467  return Offset == 0;
1468}
1469