ARMBaseInstrInfo.cpp revision 3c8ad92455ff06c8e69085702ef1f13944eab4dd
1//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Base ARM implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseInstrInfo.h" 15#include "ARM.h" 16#include "ARMBaseRegisterInfo.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMHazardRecognizer.h" 19#include "ARMMachineFunctionInfo.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalValue.h" 24#include "llvm/CodeGen/LiveVariables.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/MachineJumpTableInfo.h" 29#include "llvm/CodeGen/MachineMemOperand.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/SelectionDAGNodes.h" 32#include "llvm/MC/MCAsmInfo.h" 33#include "llvm/Support/BranchProbability.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/ADT/STLExtras.h" 38 39#define GET_INSTRINFO_CTOR 40#include "ARMGenInstrInfo.inc" 41 42using namespace llvm; 43 44static cl::opt<bool> 45EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 46 cl::desc("Enable ARM 2-addr to 3-addr conv")); 47 48static cl::opt<bool> 49WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 50 cl::desc("Widen ARM vmovs to vmovd when possible")); 51 52/// ARM_MLxEntry - Record information about MLA / MLS instructions. 53struct ARM_MLxEntry { 54 uint16_t MLxOpc; // MLA / MLS opcode 55 uint16_t MulOpc; // Expanded multiplication opcode 56 uint16_t AddSubOpc; // Expanded add / sub opcode 57 bool NegAcc; // True if the acc is negated before the add / sub. 58 bool HasLane; // True if instruction has an extra "lane" operand. 59}; 60 61static const ARM_MLxEntry ARM_MLxTable[] = { 62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 63 // fp scalar ops 64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 72 73 // fp SIMD ops 74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 82}; 83 84ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 86 Subtarget(STI) { 87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 89 assert(false && "Duplicated entries?"); 90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 92 } 93} 94 95// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 96// currently defaults to no prepass hazard recognizer. 97ScheduleHazardRecognizer *ARMBaseInstrInfo:: 98CreateTargetHazardRecognizer(const TargetMachine *TM, 99 const ScheduleDAG *DAG) const { 100 if (usePreRAHazardRecognizer()) { 101 const InstrItineraryData *II = TM->getInstrItineraryData(); 102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 103 } 104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 105} 106 107ScheduleHazardRecognizer *ARMBaseInstrInfo:: 108CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 109 const ScheduleDAG *DAG) const { 110 if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 111 return (ScheduleHazardRecognizer *) 112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG); 113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG); 114} 115 116MachineInstr * 117ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 118 MachineBasicBlock::iterator &MBBI, 119 LiveVariables *LV) const { 120 // FIXME: Thumb2 support. 121 122 if (!EnableARM3Addr) 123 return NULL; 124 125 MachineInstr *MI = MBBI; 126 MachineFunction &MF = *MI->getParent()->getParent(); 127 uint64_t TSFlags = MI->getDesc().TSFlags; 128 bool isPre = false; 129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 130 default: return NULL; 131 case ARMII::IndexModePre: 132 isPre = true; 133 break; 134 case ARMII::IndexModePost: 135 break; 136 } 137 138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub 139 // operation. 140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 141 if (MemOpc == 0) 142 return NULL; 143 144 MachineInstr *UpdateMI = NULL; 145 MachineInstr *MemMI = NULL; 146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 147 const MCInstrDesc &MCID = MI->getDesc(); 148 unsigned NumOps = MCID.getNumOperands(); 149 bool isLoad = !MI->mayStore(); 150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 151 const MachineOperand &Base = MI->getOperand(2); 152 const MachineOperand &Offset = MI->getOperand(NumOps-3); 153 unsigned WBReg = WB.getReg(); 154 unsigned BaseReg = Base.getReg(); 155 unsigned OffReg = Offset.getReg(); 156 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 158 switch (AddrMode) { 159 default: llvm_unreachable("Unknown indexed op!"); 160 case ARMII::AddrMode2: { 161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 162 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 163 if (OffReg == 0) { 164 if (ARM_AM::getSOImmVal(Amt) == -1) 165 // Can't encode it in a so_imm operand. This transformation will 166 // add more than 1 instruction. Abandon! 167 return NULL; 168 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 170 .addReg(BaseReg).addImm(Amt) 171 .addImm(Pred).addReg(0).addReg(0); 172 } else if (Amt != 0) { 173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 175 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 178 .addImm(Pred).addReg(0).addReg(0); 179 } else 180 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 182 .addReg(BaseReg).addReg(OffReg) 183 .addImm(Pred).addReg(0).addReg(0); 184 break; 185 } 186 case ARMII::AddrMode3 : { 187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 188 unsigned Amt = ARM_AM::getAM3Offset(OffImm); 189 if (OffReg == 0) 190 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 191 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 193 .addReg(BaseReg).addImm(Amt) 194 .addImm(Pred).addReg(0).addReg(0); 195 else 196 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 198 .addReg(BaseReg).addReg(OffReg) 199 .addImm(Pred).addReg(0).addReg(0); 200 break; 201 } 202 } 203 204 std::vector<MachineInstr*> NewMIs; 205 if (isPre) { 206 if (isLoad) 207 MemMI = BuildMI(MF, MI->getDebugLoc(), 208 get(MemOpc), MI->getOperand(0).getReg()) 209 .addReg(WBReg).addImm(0).addImm(Pred); 210 else 211 MemMI = BuildMI(MF, MI->getDebugLoc(), 212 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 213 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 214 NewMIs.push_back(MemMI); 215 NewMIs.push_back(UpdateMI); 216 } else { 217 if (isLoad) 218 MemMI = BuildMI(MF, MI->getDebugLoc(), 219 get(MemOpc), MI->getOperand(0).getReg()) 220 .addReg(BaseReg).addImm(0).addImm(Pred); 221 else 222 MemMI = BuildMI(MF, MI->getDebugLoc(), 223 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 225 if (WB.isDead()) 226 UpdateMI->getOperand(0).setIsDead(); 227 NewMIs.push_back(UpdateMI); 228 NewMIs.push_back(MemMI); 229 } 230 231 // Transfer LiveVariables states, kill / dead info. 232 if (LV) { 233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 234 MachineOperand &MO = MI->getOperand(i); 235 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 236 unsigned Reg = MO.getReg(); 237 238 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 239 if (MO.isDef()) { 240 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 241 if (MO.isDead()) 242 LV->addVirtualRegisterDead(Reg, NewMI); 243 } 244 if (MO.isUse() && MO.isKill()) { 245 for (unsigned j = 0; j < 2; ++j) { 246 // Look at the two new MI's in reverse order. 247 MachineInstr *NewMI = NewMIs[j]; 248 if (!NewMI->readsRegister(Reg)) 249 continue; 250 LV->addVirtualRegisterKilled(Reg, NewMI); 251 if (VI.removeKill(MI)) 252 VI.Kills.push_back(NewMI); 253 break; 254 } 255 } 256 } 257 } 258 } 259 260 MFI->insert(MBBI, NewMIs[1]); 261 MFI->insert(MBBI, NewMIs[0]); 262 return NewMIs[0]; 263} 264 265// Branch analysis. 266bool 267ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 268 MachineBasicBlock *&FBB, 269 SmallVectorImpl<MachineOperand> &Cond, 270 bool AllowModify) const { 271 // If the block has no terminators, it just falls into the block after it. 272 MachineBasicBlock::iterator I = MBB.end(); 273 if (I == MBB.begin()) 274 return false; 275 --I; 276 while (I->isDebugValue()) { 277 if (I == MBB.begin()) 278 return false; 279 --I; 280 } 281 if (!isUnpredicatedTerminator(I)) 282 return false; 283 284 // Get the last instruction in the block. 285 MachineInstr *LastInst = I; 286 287 // If there is only one terminator instruction, process it. 288 unsigned LastOpc = LastInst->getOpcode(); 289 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 290 if (isUncondBranchOpcode(LastOpc)) { 291 TBB = LastInst->getOperand(0).getMBB(); 292 return false; 293 } 294 if (isCondBranchOpcode(LastOpc)) { 295 // Block ends with fall-through condbranch. 296 TBB = LastInst->getOperand(0).getMBB(); 297 Cond.push_back(LastInst->getOperand(1)); 298 Cond.push_back(LastInst->getOperand(2)); 299 return false; 300 } 301 return true; // Can't handle indirect branch. 302 } 303 304 // Get the instruction before it if it is a terminator. 305 MachineInstr *SecondLastInst = I; 306 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 307 308 // If AllowModify is true and the block ends with two or more unconditional 309 // branches, delete all but the first unconditional branch. 310 if (AllowModify && isUncondBranchOpcode(LastOpc)) { 311 while (isUncondBranchOpcode(SecondLastOpc)) { 312 LastInst->eraseFromParent(); 313 LastInst = SecondLastInst; 314 LastOpc = LastInst->getOpcode(); 315 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 316 // Return now the only terminator is an unconditional branch. 317 TBB = LastInst->getOperand(0).getMBB(); 318 return false; 319 } else { 320 SecondLastInst = I; 321 SecondLastOpc = SecondLastInst->getOpcode(); 322 } 323 } 324 } 325 326 // If there are three terminators, we don't know what sort of block this is. 327 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) 328 return true; 329 330 // If the block ends with a B and a Bcc, handle it. 331 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 332 TBB = SecondLastInst->getOperand(0).getMBB(); 333 Cond.push_back(SecondLastInst->getOperand(1)); 334 Cond.push_back(SecondLastInst->getOperand(2)); 335 FBB = LastInst->getOperand(0).getMBB(); 336 return false; 337 } 338 339 // If the block ends with two unconditional branches, handle it. The second 340 // one is not executed, so remove it. 341 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 342 TBB = SecondLastInst->getOperand(0).getMBB(); 343 I = LastInst; 344 if (AllowModify) 345 I->eraseFromParent(); 346 return false; 347 } 348 349 // ...likewise if it ends with a branch table followed by an unconditional 350 // branch. The branch folder can create these, and we must get rid of them for 351 // correctness of Thumb constant islands. 352 if ((isJumpTableBranchOpcode(SecondLastOpc) || 353 isIndirectBranchOpcode(SecondLastOpc)) && 354 isUncondBranchOpcode(LastOpc)) { 355 I = LastInst; 356 if (AllowModify) 357 I->eraseFromParent(); 358 return true; 359 } 360 361 // Otherwise, can't handle this. 362 return true; 363} 364 365 366unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 367 MachineBasicBlock::iterator I = MBB.end(); 368 if (I == MBB.begin()) return 0; 369 --I; 370 while (I->isDebugValue()) { 371 if (I == MBB.begin()) 372 return 0; 373 --I; 374 } 375 if (!isUncondBranchOpcode(I->getOpcode()) && 376 !isCondBranchOpcode(I->getOpcode())) 377 return 0; 378 379 // Remove the branch. 380 I->eraseFromParent(); 381 382 I = MBB.end(); 383 384 if (I == MBB.begin()) return 1; 385 --I; 386 if (!isCondBranchOpcode(I->getOpcode())) 387 return 1; 388 389 // Remove the branch. 390 I->eraseFromParent(); 391 return 2; 392} 393 394unsigned 395ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 396 MachineBasicBlock *FBB, 397 const SmallVectorImpl<MachineOperand> &Cond, 398 DebugLoc DL) const { 399 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 400 int BOpc = !AFI->isThumbFunction() 401 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 402 int BccOpc = !AFI->isThumbFunction() 403 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 404 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 405 406 // Shouldn't be a fall through. 407 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 408 assert((Cond.size() == 2 || Cond.size() == 0) && 409 "ARM branch conditions have two components!"); 410 411 if (FBB == 0) { 412 if (Cond.empty()) { // Unconditional branch? 413 if (isThumb) 414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 415 else 416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 417 } else 418 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 419 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 420 return 1; 421 } 422 423 // Two-way conditional branch. 424 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 425 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 426 if (isThumb) 427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 428 else 429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 430 return 2; 431} 432 433bool ARMBaseInstrInfo:: 434ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 436 Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 437 return false; 438} 439 440bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 441 if (MI->isBundle()) { 442 MachineBasicBlock::const_instr_iterator I = MI; 443 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 444 while (++I != E && I->isInsideBundle()) { 445 int PIdx = I->findFirstPredOperandIdx(); 446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 447 return true; 448 } 449 return false; 450 } 451 452 int PIdx = MI->findFirstPredOperandIdx(); 453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 454} 455 456bool ARMBaseInstrInfo:: 457PredicateInstruction(MachineInstr *MI, 458 const SmallVectorImpl<MachineOperand> &Pred) const { 459 unsigned Opc = MI->getOpcode(); 460 if (isUncondBranchOpcode(Opc)) { 461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 462 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); 463 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); 464 return true; 465 } 466 467 int PIdx = MI->findFirstPredOperandIdx(); 468 if (PIdx != -1) { 469 MachineOperand &PMO = MI->getOperand(PIdx); 470 PMO.setImm(Pred[0].getImm()); 471 MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 472 return true; 473 } 474 return false; 475} 476 477bool ARMBaseInstrInfo:: 478SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 479 const SmallVectorImpl<MachineOperand> &Pred2) const { 480 if (Pred1.size() > 2 || Pred2.size() > 2) 481 return false; 482 483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 485 if (CC1 == CC2) 486 return true; 487 488 switch (CC1) { 489 default: 490 return false; 491 case ARMCC::AL: 492 return true; 493 case ARMCC::HS: 494 return CC2 == ARMCC::HI; 495 case ARMCC::LS: 496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 497 case ARMCC::GE: 498 return CC2 == ARMCC::GT; 499 case ARMCC::LE: 500 return CC2 == ARMCC::LT; 501 } 502} 503 504bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 505 std::vector<MachineOperand> &Pred) const { 506 bool Found = false; 507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 508 const MachineOperand &MO = MI->getOperand(i); 509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 511 Pred.push_back(MO); 512 Found = true; 513 } 514 } 515 516 return Found; 517} 518 519/// isPredicable - Return true if the specified instruction can be predicated. 520/// By default, this returns true for every instruction with a 521/// PredicateOperand. 522bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 523 if (!MI->isPredicable()) 524 return false; 525 526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { 527 ARMFunctionInfo *AFI = 528 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 529 return AFI->isThumb2Function(); 530 } 531 return true; 532} 533 534/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 535LLVM_ATTRIBUTE_NOINLINE 536static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 537 unsigned JTI); 538static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 539 unsigned JTI) { 540 assert(JTI < JT.size()); 541 return JT[JTI].MBBs.size(); 542} 543 544/// GetInstSize - Return the size of the specified MachineInstr. 545/// 546unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 547 const MachineBasicBlock &MBB = *MI->getParent(); 548 const MachineFunction *MF = MBB.getParent(); 549 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 550 551 const MCInstrDesc &MCID = MI->getDesc(); 552 if (MCID.getSize()) 553 return MCID.getSize(); 554 555 // If this machine instr is an inline asm, measure it. 556 if (MI->getOpcode() == ARM::INLINEASM) 557 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 558 if (MI->isLabel()) 559 return 0; 560 unsigned Opc = MI->getOpcode(); 561 switch (Opc) { 562 case TargetOpcode::IMPLICIT_DEF: 563 case TargetOpcode::KILL: 564 case TargetOpcode::PROLOG_LABEL: 565 case TargetOpcode::EH_LABEL: 566 case TargetOpcode::DBG_VALUE: 567 return 0; 568 case TargetOpcode::BUNDLE: 569 return getInstBundleLength(MI); 570 case ARM::MOVi16_ga_pcrel: 571 case ARM::MOVTi16_ga_pcrel: 572 case ARM::t2MOVi16_ga_pcrel: 573 case ARM::t2MOVTi16_ga_pcrel: 574 return 4; 575 case ARM::MOVi32imm: 576 case ARM::t2MOVi32imm: 577 return 8; 578 case ARM::CONSTPOOL_ENTRY: 579 // If this machine instr is a constant pool entry, its size is recorded as 580 // operand #2. 581 return MI->getOperand(2).getImm(); 582 case ARM::Int_eh_sjlj_longjmp: 583 return 16; 584 case ARM::tInt_eh_sjlj_longjmp: 585 return 10; 586 case ARM::Int_eh_sjlj_setjmp: 587 case ARM::Int_eh_sjlj_setjmp_nofp: 588 return 20; 589 case ARM::tInt_eh_sjlj_setjmp: 590 case ARM::t2Int_eh_sjlj_setjmp: 591 case ARM::t2Int_eh_sjlj_setjmp_nofp: 592 return 12; 593 case ARM::BR_JTr: 594 case ARM::BR_JTm: 595 case ARM::BR_JTadd: 596 case ARM::tBR_JTr: 597 case ARM::t2BR_JT: 598 case ARM::t2TBB_JT: 599 case ARM::t2TBH_JT: { 600 // These are jumptable branches, i.e. a branch followed by an inlined 601 // jumptable. The size is 4 + 4 * number of entries. For TBB, each 602 // entry is one byte; TBH two byte each. 603 unsigned EntrySize = (Opc == ARM::t2TBB_JT) 604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 605 unsigned NumOps = MCID.getNumOperands(); 606 MachineOperand JTOP = 607 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 608 unsigned JTI = JTOP.getIndex(); 609 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 610 assert(MJTI != 0); 611 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 612 assert(JTI < JT.size()); 613 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 614 // 4 aligned. The assembler / linker may add 2 byte padding just before 615 // the JT entries. The size does not include this padding; the 616 // constant islands pass does separate bookkeeping for it. 617 // FIXME: If we know the size of the function is less than (1 << 16) *2 618 // bytes, we can use 16-bit entries instead. Then there won't be an 619 // alignment issue. 620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 621 unsigned NumEntries = getNumJTEntries(JT, JTI); 622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 623 // Make sure the instruction that follows TBB is 2-byte aligned. 624 // FIXME: Constant island pass should insert an "ALIGN" instruction 625 // instead. 626 ++NumEntries; 627 return NumEntries * EntrySize + InstSize; 628 } 629 default: 630 // Otherwise, pseudo-instruction sizes are zero. 631 return 0; 632 } 633} 634 635unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 636 unsigned Size = 0; 637 MachineBasicBlock::const_instr_iterator I = MI; 638 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 639 while (++I != E && I->isInsideBundle()) { 640 assert(!I->isBundle() && "No nested bundle!"); 641 Size += GetInstSizeInBytes(&*I); 642 } 643 return Size; 644} 645 646void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 647 MachineBasicBlock::iterator I, DebugLoc DL, 648 unsigned DestReg, unsigned SrcReg, 649 bool KillSrc) const { 650 bool GPRDest = ARM::GPRRegClass.contains(DestReg); 651 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 652 653 if (GPRDest && GPRSrc) { 654 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 655 .addReg(SrcReg, getKillRegState(KillSrc)))); 656 return; 657 } 658 659 bool SPRDest = ARM::SPRRegClass.contains(DestReg); 660 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 661 662 unsigned Opc = 0; 663 if (SPRDest && SPRSrc) 664 Opc = ARM::VMOVS; 665 else if (GPRDest && SPRSrc) 666 Opc = ARM::VMOVRS; 667 else if (SPRDest && GPRSrc) 668 Opc = ARM::VMOVSR; 669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 670 Opc = ARM::VMOVD; 671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 672 Opc = ARM::VORRq; 673 674 if (Opc) { 675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 676 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 677 if (Opc == ARM::VORRq) 678 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 679 AddDefaultPred(MIB); 680 return; 681 } 682 683 // Handle register classes that require multiple instructions. 684 unsigned BeginIdx = 0; 685 unsigned SubRegs = 0; 686 unsigned Spacing = 1; 687 688 // Use VORRq when possible. 689 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) 690 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2; 691 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) 692 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4; 693 // Fall back to VMOVD. 694 else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) 695 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2; 696 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) 697 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3; 698 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) 699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4; 700 701 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) 702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2; 703 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) 704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2; 705 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) 706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2; 707 708 if (Opc) { 709 const TargetRegisterInfo *TRI = &getRegisterInfo(); 710 MachineInstrBuilder Mov; 711 for (unsigned i = 0; i != SubRegs; ++i) { 712 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); 713 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); 714 assert(Dst && Src && "Bad sub-register"); 715 Mov = AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) 716 .addReg(Src)); 717 // VORR takes two source operands. 718 if (Opc == ARM::VORRq) 719 Mov.addReg(Src); 720 } 721 // Add implicit super-register defs and kills to the last instruction. 722 Mov->addRegisterDefined(DestReg, TRI); 723 if (KillSrc) 724 Mov->addRegisterKilled(SrcReg, TRI); 725 return; 726 } 727 728 llvm_unreachable("Impossible reg-to-reg copy"); 729} 730 731static const 732MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 733 unsigned Reg, unsigned SubIdx, unsigned State, 734 const TargetRegisterInfo *TRI) { 735 if (!SubIdx) 736 return MIB.addReg(Reg, State); 737 738 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 739 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 740 return MIB.addReg(Reg, State, SubIdx); 741} 742 743void ARMBaseInstrInfo:: 744storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 745 unsigned SrcReg, bool isKill, int FI, 746 const TargetRegisterClass *RC, 747 const TargetRegisterInfo *TRI) const { 748 DebugLoc DL; 749 if (I != MBB.end()) DL = I->getDebugLoc(); 750 MachineFunction &MF = *MBB.getParent(); 751 MachineFrameInfo &MFI = *MF.getFrameInfo(); 752 unsigned Align = MFI.getObjectAlignment(FI); 753 754 MachineMemOperand *MMO = 755 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 756 MachineMemOperand::MOStore, 757 MFI.getObjectSize(FI), 758 Align); 759 760 switch (RC->getSize()) { 761 case 4: 762 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 763 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 764 .addReg(SrcReg, getKillRegState(isKill)) 765 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 766 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 767 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 768 .addReg(SrcReg, getKillRegState(isKill)) 769 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 770 } else 771 llvm_unreachable("Unknown reg class!"); 772 break; 773 case 8: 774 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 775 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 776 .addReg(SrcReg, getKillRegState(isKill)) 777 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 778 } else 779 llvm_unreachable("Unknown reg class!"); 780 break; 781 case 16: 782 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 783 // Use aligned spills if the stack can be realigned. 784 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 785 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 786 .addFrameIndex(FI).addImm(16) 787 .addReg(SrcReg, getKillRegState(isKill)) 788 .addMemOperand(MMO)); 789 } else { 790 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 791 .addReg(SrcReg, getKillRegState(isKill)) 792 .addFrameIndex(FI) 793 .addMemOperand(MMO)); 794 } 795 } else 796 llvm_unreachable("Unknown reg class!"); 797 break; 798 case 24: 799 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 800 // Use aligned spills if the stack can be realigned. 801 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 802 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) 803 .addFrameIndex(FI).addImm(16) 804 .addReg(SrcReg, getKillRegState(isKill)) 805 .addMemOperand(MMO)); 806 } else { 807 MachineInstrBuilder MIB = 808 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 809 .addFrameIndex(FI)) 810 .addMemOperand(MMO); 811 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 813 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 814 } 815 } else 816 llvm_unreachable("Unknown reg class!"); 817 break; 818 case 32: 819 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 820 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 821 // FIXME: It's possible to only store part of the QQ register if the 822 // spilled def has a sub-register index. 823 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 824 .addFrameIndex(FI).addImm(16) 825 .addReg(SrcReg, getKillRegState(isKill)) 826 .addMemOperand(MMO)); 827 } else { 828 MachineInstrBuilder MIB = 829 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 830 .addFrameIndex(FI)) 831 .addMemOperand(MMO); 832 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 833 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 834 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 835 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 836 } 837 } else 838 llvm_unreachable("Unknown reg class!"); 839 break; 840 case 64: 841 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 842 MachineInstrBuilder MIB = 843 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 844 .addFrameIndex(FI)) 845 .addMemOperand(MMO); 846 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 847 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 848 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 849 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 850 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 851 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 852 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 853 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 854 } else 855 llvm_unreachable("Unknown reg class!"); 856 break; 857 default: 858 llvm_unreachable("Unknown reg class!"); 859 } 860} 861 862unsigned 863ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 864 int &FrameIndex) const { 865 switch (MI->getOpcode()) { 866 default: break; 867 case ARM::STRrs: 868 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 869 if (MI->getOperand(1).isFI() && 870 MI->getOperand(2).isReg() && 871 MI->getOperand(3).isImm() && 872 MI->getOperand(2).getReg() == 0 && 873 MI->getOperand(3).getImm() == 0) { 874 FrameIndex = MI->getOperand(1).getIndex(); 875 return MI->getOperand(0).getReg(); 876 } 877 break; 878 case ARM::STRi12: 879 case ARM::t2STRi12: 880 case ARM::tSTRspi: 881 case ARM::VSTRD: 882 case ARM::VSTRS: 883 if (MI->getOperand(1).isFI() && 884 MI->getOperand(2).isImm() && 885 MI->getOperand(2).getImm() == 0) { 886 FrameIndex = MI->getOperand(1).getIndex(); 887 return MI->getOperand(0).getReg(); 888 } 889 break; 890 case ARM::VST1q64: 891 case ARM::VST1d64TPseudo: 892 case ARM::VST1d64QPseudo: 893 if (MI->getOperand(0).isFI() && 894 MI->getOperand(2).getSubReg() == 0) { 895 FrameIndex = MI->getOperand(0).getIndex(); 896 return MI->getOperand(2).getReg(); 897 } 898 break; 899 case ARM::VSTMQIA: 900 if (MI->getOperand(1).isFI() && 901 MI->getOperand(0).getSubReg() == 0) { 902 FrameIndex = MI->getOperand(1).getIndex(); 903 return MI->getOperand(0).getReg(); 904 } 905 break; 906 } 907 908 return 0; 909} 910 911unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 912 int &FrameIndex) const { 913 const MachineMemOperand *Dummy; 914 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 915} 916 917void ARMBaseInstrInfo:: 918loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 919 unsigned DestReg, int FI, 920 const TargetRegisterClass *RC, 921 const TargetRegisterInfo *TRI) const { 922 DebugLoc DL; 923 if (I != MBB.end()) DL = I->getDebugLoc(); 924 MachineFunction &MF = *MBB.getParent(); 925 MachineFrameInfo &MFI = *MF.getFrameInfo(); 926 unsigned Align = MFI.getObjectAlignment(FI); 927 MachineMemOperand *MMO = 928 MF.getMachineMemOperand( 929 MachinePointerInfo::getFixedStack(FI), 930 MachineMemOperand::MOLoad, 931 MFI.getObjectSize(FI), 932 Align); 933 934 switch (RC->getSize()) { 935 case 4: 936 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 937 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 938 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 939 940 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 941 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 942 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 943 } else 944 llvm_unreachable("Unknown reg class!"); 945 break; 946 case 8: 947 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 948 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 949 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 950 } else 951 llvm_unreachable("Unknown reg class!"); 952 break; 953 case 16: 954 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 955 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 956 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 957 .addFrameIndex(FI).addImm(16) 958 .addMemOperand(MMO)); 959 } else { 960 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 961 .addFrameIndex(FI) 962 .addMemOperand(MMO)); 963 } 964 } else 965 llvm_unreachable("Unknown reg class!"); 966 break; 967 case 24: 968 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 969 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 970 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) 971 .addFrameIndex(FI).addImm(16) 972 .addMemOperand(MMO)); 973 } else { 974 MachineInstrBuilder MIB = 975 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 976 .addFrameIndex(FI) 977 .addMemOperand(MMO)); 978 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 979 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 980 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 981 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 982 MIB.addReg(DestReg, RegState::ImplicitDefine); 983 } 984 } else 985 llvm_unreachable("Unknown reg class!"); 986 break; 987 case 32: 988 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 989 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 990 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 991 .addFrameIndex(FI).addImm(16) 992 .addMemOperand(MMO)); 993 } else { 994 MachineInstrBuilder MIB = 995 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 996 .addFrameIndex(FI)) 997 .addMemOperand(MMO); 998 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 999 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1000 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1001 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1002 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1003 MIB.addReg(DestReg, RegState::ImplicitDefine); 1004 } 1005 } else 1006 llvm_unreachable("Unknown reg class!"); 1007 break; 1008 case 64: 1009 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 1010 MachineInstrBuilder MIB = 1011 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1012 .addFrameIndex(FI)) 1013 .addMemOperand(MMO); 1014 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1015 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1016 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1017 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1018 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 1019 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 1020 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 1021 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 1022 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1023 MIB.addReg(DestReg, RegState::ImplicitDefine); 1024 } else 1025 llvm_unreachable("Unknown reg class!"); 1026 break; 1027 default: 1028 llvm_unreachable("Unknown regclass!"); 1029 } 1030} 1031 1032unsigned 1033ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1034 int &FrameIndex) const { 1035 switch (MI->getOpcode()) { 1036 default: break; 1037 case ARM::LDRrs: 1038 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 1039 if (MI->getOperand(1).isFI() && 1040 MI->getOperand(2).isReg() && 1041 MI->getOperand(3).isImm() && 1042 MI->getOperand(2).getReg() == 0 && 1043 MI->getOperand(3).getImm() == 0) { 1044 FrameIndex = MI->getOperand(1).getIndex(); 1045 return MI->getOperand(0).getReg(); 1046 } 1047 break; 1048 case ARM::LDRi12: 1049 case ARM::t2LDRi12: 1050 case ARM::tLDRspi: 1051 case ARM::VLDRD: 1052 case ARM::VLDRS: 1053 if (MI->getOperand(1).isFI() && 1054 MI->getOperand(2).isImm() && 1055 MI->getOperand(2).getImm() == 0) { 1056 FrameIndex = MI->getOperand(1).getIndex(); 1057 return MI->getOperand(0).getReg(); 1058 } 1059 break; 1060 case ARM::VLD1q64: 1061 case ARM::VLD1d64TPseudo: 1062 case ARM::VLD1d64QPseudo: 1063 if (MI->getOperand(1).isFI() && 1064 MI->getOperand(0).getSubReg() == 0) { 1065 FrameIndex = MI->getOperand(1).getIndex(); 1066 return MI->getOperand(0).getReg(); 1067 } 1068 break; 1069 case ARM::VLDMQIA: 1070 if (MI->getOperand(1).isFI() && 1071 MI->getOperand(0).getSubReg() == 0) { 1072 FrameIndex = MI->getOperand(1).getIndex(); 1073 return MI->getOperand(0).getReg(); 1074 } 1075 break; 1076 } 1077 1078 return 0; 1079} 1080 1081unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1082 int &FrameIndex) const { 1083 const MachineMemOperand *Dummy; 1084 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1085} 1086 1087bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1088 // This hook gets to expand COPY instructions before they become 1089 // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1090 // widened to VMOVD. We prefer the VMOVD when possible because it may be 1091 // changed into a VORR that can go down the NEON pipeline. 1092 if (!WidenVMOVS || !MI->isCopy()) 1093 return false; 1094 1095 // Look for a copy between even S-registers. That is where we keep floats 1096 // when using NEON v2f32 instructions for f32 arithmetic. 1097 unsigned DstRegS = MI->getOperand(0).getReg(); 1098 unsigned SrcRegS = MI->getOperand(1).getReg(); 1099 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1100 return false; 1101 1102 const TargetRegisterInfo *TRI = &getRegisterInfo(); 1103 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1104 &ARM::DPRRegClass); 1105 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1106 &ARM::DPRRegClass); 1107 if (!DstRegD || !SrcRegD) 1108 return false; 1109 1110 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1111 // legal if the COPY already defines the full DstRegD, and it isn't a 1112 // sub-register insertion. 1113 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1114 return false; 1115 1116 // A dead copy shouldn't show up here, but reject it just in case. 1117 if (MI->getOperand(0).isDead()) 1118 return false; 1119 1120 // All clear, widen the COPY. 1121 DEBUG(dbgs() << "widening: " << *MI); 1122 1123 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 1124 // or some other super-register. 1125 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 1126 if (ImpDefIdx != -1) 1127 MI->RemoveOperand(ImpDefIdx); 1128 1129 // Change the opcode and operands. 1130 MI->setDesc(get(ARM::VMOVD)); 1131 MI->getOperand(0).setReg(DstRegD); 1132 MI->getOperand(1).setReg(SrcRegD); 1133 AddDefaultPred(MachineInstrBuilder(MI)); 1134 1135 // We are now reading SrcRegD instead of SrcRegS. This may upset the 1136 // register scavenger and machine verifier, so we need to indicate that we 1137 // are reading an undefined value from SrcRegD, but a proper value from 1138 // SrcRegS. 1139 MI->getOperand(1).setIsUndef(); 1140 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit); 1141 1142 // SrcRegD may actually contain an unrelated value in the ssub_1 1143 // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 1144 if (MI->getOperand(1).isKill()) { 1145 MI->getOperand(1).setIsKill(false); 1146 MI->addRegisterKilled(SrcRegS, TRI, true); 1147 } 1148 1149 DEBUG(dbgs() << "replaced by: " << *MI); 1150 return true; 1151} 1152 1153MachineInstr* 1154ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 1155 int FrameIx, uint64_t Offset, 1156 const MDNode *MDPtr, 1157 DebugLoc DL) const { 1158 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) 1159 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 1160 return &*MIB; 1161} 1162 1163/// Create a copy of a const pool value. Update CPI to the new index and return 1164/// the label UID. 1165static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 1166 MachineConstantPool *MCP = MF.getConstantPool(); 1167 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1168 1169 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 1170 assert(MCPE.isMachineConstantPoolEntry() && 1171 "Expecting a machine constantpool entry!"); 1172 ARMConstantPoolValue *ACPV = 1173 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 1174 1175 unsigned PCLabelId = AFI->createPICLabelUId(); 1176 ARMConstantPoolValue *NewCPV = 0; 1177 // FIXME: The below assumes PIC relocation model and that the function 1178 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 1179 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 1180 // instructions, so that's probably OK, but is PIC always correct when 1181 // we get here? 1182 if (ACPV->isGlobalValue()) 1183 NewCPV = ARMConstantPoolConstant:: 1184 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 1185 ARMCP::CPValue, 4); 1186 else if (ACPV->isExtSymbol()) 1187 NewCPV = ARMConstantPoolSymbol:: 1188 Create(MF.getFunction()->getContext(), 1189 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 1190 else if (ACPV->isBlockAddress()) 1191 NewCPV = ARMConstantPoolConstant:: 1192 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 1193 ARMCP::CPBlockAddress, 4); 1194 else if (ACPV->isLSDA()) 1195 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 1196 ARMCP::CPLSDA, 4); 1197 else if (ACPV->isMachineBasicBlock()) 1198 NewCPV = ARMConstantPoolMBB:: 1199 Create(MF.getFunction()->getContext(), 1200 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 1201 else 1202 llvm_unreachable("Unexpected ARM constantpool value type!!"); 1203 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 1204 return PCLabelId; 1205} 1206 1207void ARMBaseInstrInfo:: 1208reMaterialize(MachineBasicBlock &MBB, 1209 MachineBasicBlock::iterator I, 1210 unsigned DestReg, unsigned SubIdx, 1211 const MachineInstr *Orig, 1212 const TargetRegisterInfo &TRI) const { 1213 unsigned Opcode = Orig->getOpcode(); 1214 switch (Opcode) { 1215 default: { 1216 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1217 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1218 MBB.insert(I, MI); 1219 break; 1220 } 1221 case ARM::tLDRpci_pic: 1222 case ARM::t2LDRpci_pic: { 1223 MachineFunction &MF = *MBB.getParent(); 1224 unsigned CPI = Orig->getOperand(1).getIndex(); 1225 unsigned PCLabelId = duplicateCPV(MF, CPI); 1226 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1227 DestReg) 1228 .addConstantPoolIndex(CPI).addImm(PCLabelId); 1229 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1230 break; 1231 } 1232 } 1233} 1234 1235MachineInstr * 1236ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 1237 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF); 1238 switch(Orig->getOpcode()) { 1239 case ARM::tLDRpci_pic: 1240 case ARM::t2LDRpci_pic: { 1241 unsigned CPI = Orig->getOperand(1).getIndex(); 1242 unsigned PCLabelId = duplicateCPV(MF, CPI); 1243 Orig->getOperand(1).setIndex(CPI); 1244 Orig->getOperand(2).setImm(PCLabelId); 1245 break; 1246 } 1247 } 1248 return MI; 1249} 1250 1251bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1252 const MachineInstr *MI1, 1253 const MachineRegisterInfo *MRI) const { 1254 int Opcode = MI0->getOpcode(); 1255 if (Opcode == ARM::t2LDRpci || 1256 Opcode == ARM::t2LDRpci_pic || 1257 Opcode == ARM::tLDRpci || 1258 Opcode == ARM::tLDRpci_pic || 1259 Opcode == ARM::MOV_ga_dyn || 1260 Opcode == ARM::MOV_ga_pcrel || 1261 Opcode == ARM::MOV_ga_pcrel_ldr || 1262 Opcode == ARM::t2MOV_ga_dyn || 1263 Opcode == ARM::t2MOV_ga_pcrel) { 1264 if (MI1->getOpcode() != Opcode) 1265 return false; 1266 if (MI0->getNumOperands() != MI1->getNumOperands()) 1267 return false; 1268 1269 const MachineOperand &MO0 = MI0->getOperand(1); 1270 const MachineOperand &MO1 = MI1->getOperand(1); 1271 if (MO0.getOffset() != MO1.getOffset()) 1272 return false; 1273 1274 if (Opcode == ARM::MOV_ga_dyn || 1275 Opcode == ARM::MOV_ga_pcrel || 1276 Opcode == ARM::MOV_ga_pcrel_ldr || 1277 Opcode == ARM::t2MOV_ga_dyn || 1278 Opcode == ARM::t2MOV_ga_pcrel) 1279 // Ignore the PC labels. 1280 return MO0.getGlobal() == MO1.getGlobal(); 1281 1282 const MachineFunction *MF = MI0->getParent()->getParent(); 1283 const MachineConstantPool *MCP = MF->getConstantPool(); 1284 int CPI0 = MO0.getIndex(); 1285 int CPI1 = MO1.getIndex(); 1286 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1287 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1288 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1289 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1290 if (isARMCP0 && isARMCP1) { 1291 ARMConstantPoolValue *ACPV0 = 1292 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1293 ARMConstantPoolValue *ACPV1 = 1294 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1295 return ACPV0->hasSameValue(ACPV1); 1296 } else if (!isARMCP0 && !isARMCP1) { 1297 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1298 } 1299 return false; 1300 } else if (Opcode == ARM::PICLDR) { 1301 if (MI1->getOpcode() != Opcode) 1302 return false; 1303 if (MI0->getNumOperands() != MI1->getNumOperands()) 1304 return false; 1305 1306 unsigned Addr0 = MI0->getOperand(1).getReg(); 1307 unsigned Addr1 = MI1->getOperand(1).getReg(); 1308 if (Addr0 != Addr1) { 1309 if (!MRI || 1310 !TargetRegisterInfo::isVirtualRegister(Addr0) || 1311 !TargetRegisterInfo::isVirtualRegister(Addr1)) 1312 return false; 1313 1314 // This assumes SSA form. 1315 MachineInstr *Def0 = MRI->getVRegDef(Addr0); 1316 MachineInstr *Def1 = MRI->getVRegDef(Addr1); 1317 // Check if the loaded value, e.g. a constantpool of a global address, are 1318 // the same. 1319 if (!produceSameValue(Def0, Def1, MRI)) 1320 return false; 1321 } 1322 1323 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 1324 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 1325 const MachineOperand &MO0 = MI0->getOperand(i); 1326 const MachineOperand &MO1 = MI1->getOperand(i); 1327 if (!MO0.isIdenticalTo(MO1)) 1328 return false; 1329 } 1330 return true; 1331 } 1332 1333 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1334} 1335 1336/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 1337/// determine if two loads are loading from the same base address. It should 1338/// only return true if the base pointers are the same and the only differences 1339/// between the two addresses is the offset. It also returns the offsets by 1340/// reference. 1341bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1342 int64_t &Offset1, 1343 int64_t &Offset2) const { 1344 // Don't worry about Thumb: just ARM and Thumb2. 1345 if (Subtarget.isThumb1Only()) return false; 1346 1347 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 1348 return false; 1349 1350 switch (Load1->getMachineOpcode()) { 1351 default: 1352 return false; 1353 case ARM::LDRi12: 1354 case ARM::LDRBi12: 1355 case ARM::LDRD: 1356 case ARM::LDRH: 1357 case ARM::LDRSB: 1358 case ARM::LDRSH: 1359 case ARM::VLDRD: 1360 case ARM::VLDRS: 1361 case ARM::t2LDRi8: 1362 case ARM::t2LDRDi8: 1363 case ARM::t2LDRSHi8: 1364 case ARM::t2LDRi12: 1365 case ARM::t2LDRSHi12: 1366 break; 1367 } 1368 1369 switch (Load2->getMachineOpcode()) { 1370 default: 1371 return false; 1372 case ARM::LDRi12: 1373 case ARM::LDRBi12: 1374 case ARM::LDRD: 1375 case ARM::LDRH: 1376 case ARM::LDRSB: 1377 case ARM::LDRSH: 1378 case ARM::VLDRD: 1379 case ARM::VLDRS: 1380 case ARM::t2LDRi8: 1381 case ARM::t2LDRDi8: 1382 case ARM::t2LDRSHi8: 1383 case ARM::t2LDRi12: 1384 case ARM::t2LDRSHi12: 1385 break; 1386 } 1387 1388 // Check if base addresses and chain operands match. 1389 if (Load1->getOperand(0) != Load2->getOperand(0) || 1390 Load1->getOperand(4) != Load2->getOperand(4)) 1391 return false; 1392 1393 // Index should be Reg0. 1394 if (Load1->getOperand(3) != Load2->getOperand(3)) 1395 return false; 1396 1397 // Determine the offsets. 1398 if (isa<ConstantSDNode>(Load1->getOperand(1)) && 1399 isa<ConstantSDNode>(Load2->getOperand(1))) { 1400 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 1401 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 1402 return true; 1403 } 1404 1405 return false; 1406} 1407 1408/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 1409/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 1410/// be scheduled togther. On some targets if two loads are loading from 1411/// addresses in the same cache line, it's better if they are scheduled 1412/// together. This function takes two integers that represent the load offsets 1413/// from the common base address. It returns true if it decides it's desirable 1414/// to schedule the two loads together. "NumLoads" is the number of loads that 1415/// have already been scheduled after Load1. 1416bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1417 int64_t Offset1, int64_t Offset2, 1418 unsigned NumLoads) const { 1419 // Don't worry about Thumb: just ARM and Thumb2. 1420 if (Subtarget.isThumb1Only()) return false; 1421 1422 assert(Offset2 > Offset1); 1423 1424 if ((Offset2 - Offset1) / 8 > 64) 1425 return false; 1426 1427 if (Load1->getMachineOpcode() != Load2->getMachineOpcode()) 1428 return false; // FIXME: overly conservative? 1429 1430 // Four loads in a row should be sufficient. 1431 if (NumLoads >= 3) 1432 return false; 1433 1434 return true; 1435} 1436 1437bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 1438 const MachineBasicBlock *MBB, 1439 const MachineFunction &MF) const { 1440 // Debug info is never a scheduling boundary. It's necessary to be explicit 1441 // due to the special treatment of IT instructions below, otherwise a 1442 // dbg_value followed by an IT will result in the IT instruction being 1443 // considered a scheduling hazard, which is wrong. It should be the actual 1444 // instruction preceding the dbg_value instruction(s), just like it is 1445 // when debug info is not present. 1446 if (MI->isDebugValue()) 1447 return false; 1448 1449 // Terminators and labels can't be scheduled around. 1450 if (MI->isTerminator() || MI->isLabel()) 1451 return true; 1452 1453 // Treat the start of the IT block as a scheduling boundary, but schedule 1454 // t2IT along with all instructions following it. 1455 // FIXME: This is a big hammer. But the alternative is to add all potential 1456 // true and anti dependencies to IT block instructions as implicit operands 1457 // to the t2IT instruction. The added compile time and complexity does not 1458 // seem worth it. 1459 MachineBasicBlock::const_iterator I = MI; 1460 // Make sure to skip any dbg_value instructions 1461 while (++I != MBB->end() && I->isDebugValue()) 1462 ; 1463 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 1464 return true; 1465 1466 // Don't attempt to schedule around any instruction that defines 1467 // a stack-oriented pointer, as it's unlikely to be profitable. This 1468 // saves compile time, because it doesn't require every single 1469 // stack slot reference to depend on the instruction that does the 1470 // modification. 1471 // Calls don't actually change the stack pointer, even if they have imp-defs. 1472 // No ARM calling conventions change the stack pointer. (X86 calling 1473 // conventions sometimes do). 1474 if (!MI->isCall() && MI->definesRegister(ARM::SP)) 1475 return true; 1476 1477 return false; 1478} 1479 1480bool ARMBaseInstrInfo:: 1481isProfitableToIfCvt(MachineBasicBlock &MBB, 1482 unsigned NumCycles, unsigned ExtraPredCycles, 1483 const BranchProbability &Probability) const { 1484 if (!NumCycles) 1485 return false; 1486 1487 // Attempt to estimate the relative costs of predication versus branching. 1488 unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1489 UnpredCost /= Probability.getDenominator(); 1490 UnpredCost += 1; // The branch itself 1491 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1492 1493 return (NumCycles + ExtraPredCycles) <= UnpredCost; 1494} 1495 1496bool ARMBaseInstrInfo:: 1497isProfitableToIfCvt(MachineBasicBlock &TMBB, 1498 unsigned TCycles, unsigned TExtra, 1499 MachineBasicBlock &FMBB, 1500 unsigned FCycles, unsigned FExtra, 1501 const BranchProbability &Probability) const { 1502 if (!TCycles || !FCycles) 1503 return false; 1504 1505 // Attempt to estimate the relative costs of predication versus branching. 1506 unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1507 TUnpredCost /= Probability.getDenominator(); 1508 1509 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1510 unsigned FUnpredCost = Comp * FCycles; 1511 FUnpredCost /= Probability.getDenominator(); 1512 1513 unsigned UnpredCost = TUnpredCost + FUnpredCost; 1514 UnpredCost += 1; // The branch itself 1515 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1516 1517 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 1518} 1519 1520/// getInstrPredicate - If instruction is predicated, returns its predicate 1521/// condition, otherwise returns AL. It also returns the condition code 1522/// register by reference. 1523ARMCC::CondCodes 1524llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 1525 int PIdx = MI->findFirstPredOperandIdx(); 1526 if (PIdx == -1) { 1527 PredReg = 0; 1528 return ARMCC::AL; 1529 } 1530 1531 PredReg = MI->getOperand(PIdx+1).getReg(); 1532 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 1533} 1534 1535 1536int llvm::getMatchingCondBranchOpcode(int Opc) { 1537 if (Opc == ARM::B) 1538 return ARM::Bcc; 1539 if (Opc == ARM::tB) 1540 return ARM::tBcc; 1541 if (Opc == ARM::t2B) 1542 return ARM::t2Bcc; 1543 1544 llvm_unreachable("Unknown unconditional branch opcode!"); 1545} 1546 1547/// commuteInstruction - Handle commutable instructions. 1548MachineInstr * 1549ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1550 switch (MI->getOpcode()) { 1551 case ARM::MOVCCr: 1552 case ARM::t2MOVCCr: { 1553 // MOVCC can be commuted by inverting the condition. 1554 unsigned PredReg = 0; 1555 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1556 // MOVCC AL can't be inverted. Shouldn't happen. 1557 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1558 return NULL; 1559 MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1560 if (!MI) 1561 return NULL; 1562 // After swapping the MOVCC operands, also invert the condition. 1563 MI->getOperand(MI->findFirstPredOperandIdx()) 1564 .setImm(ARMCC::getOppositeCondition(CC)); 1565 return MI; 1566 } 1567 } 1568 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1569} 1570 1571/// Identify instructions that can be folded into a MOVCC instruction, and 1572/// return the corresponding opcode for the predicated pseudo-instruction. 1573static unsigned canFoldIntoMOVCC(unsigned Reg, MachineInstr *&MI, 1574 const MachineRegisterInfo &MRI) { 1575 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 1576 return 0; 1577 if (!MRI.hasOneNonDBGUse(Reg)) 1578 return 0; 1579 MI = MRI.getVRegDef(Reg); 1580 if (!MI) 1581 return 0; 1582 // Check if MI has any non-dead defs or physreg uses. This also detects 1583 // predicated instructions which will be reading CPSR. 1584 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 1585 const MachineOperand &MO = MI->getOperand(i); 1586 if (!MO.isReg()) 1587 continue; 1588 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 1589 return 0; 1590 if (MO.isDef() && !MO.isDead()) 1591 return 0; 1592 } 1593 switch (MI->getOpcode()) { 1594 default: return 0; 1595 case ARM::ANDri: return ARM::ANDCCri; 1596 case ARM::ANDrr: return ARM::ANDCCrr; 1597 case ARM::ANDrsi: return ARM::ANDCCrsi; 1598 case ARM::ANDrsr: return ARM::ANDCCrsr; 1599 case ARM::t2ANDri: return ARM::t2ANDCCri; 1600 case ARM::t2ANDrr: return ARM::t2ANDCCrr; 1601 case ARM::t2ANDrs: return ARM::t2ANDCCrs; 1602 case ARM::EORri: return ARM::EORCCri; 1603 case ARM::EORrr: return ARM::EORCCrr; 1604 case ARM::EORrsi: return ARM::EORCCrsi; 1605 case ARM::EORrsr: return ARM::EORCCrsr; 1606 case ARM::t2EORri: return ARM::t2EORCCri; 1607 case ARM::t2EORrr: return ARM::t2EORCCrr; 1608 case ARM::t2EORrs: return ARM::t2EORCCrs; 1609 case ARM::ORRri: return ARM::ORRCCri; 1610 case ARM::ORRrr: return ARM::ORRCCrr; 1611 case ARM::ORRrsi: return ARM::ORRCCrsi; 1612 case ARM::ORRrsr: return ARM::ORRCCrsr; 1613 case ARM::t2ORRri: return ARM::t2ORRCCri; 1614 case ARM::t2ORRrr: return ARM::t2ORRCCrr; 1615 case ARM::t2ORRrs: return ARM::t2ORRCCrs; 1616 1617 // ARM ADD/SUB 1618 case ARM::ADDri: return ARM::ADDCCri; 1619 case ARM::ADDrr: return ARM::ADDCCrr; 1620 case ARM::ADDrsi: return ARM::ADDCCrsi; 1621 case ARM::ADDrsr: return ARM::ADDCCrsr; 1622 case ARM::SUBri: return ARM::SUBCCri; 1623 case ARM::SUBrr: return ARM::SUBCCrr; 1624 case ARM::SUBrsi: return ARM::SUBCCrsi; 1625 case ARM::SUBrsr: return ARM::SUBCCrsr; 1626 1627 // Thumb2 ADD/SUB 1628 case ARM::t2ADDri: return ARM::t2ADDCCri; 1629 case ARM::t2ADDri12: return ARM::t2ADDCCri12; 1630 case ARM::t2ADDrr: return ARM::t2ADDCCrr; 1631 case ARM::t2ADDrs: return ARM::t2ADDCCrs; 1632 case ARM::t2SUBri: return ARM::t2SUBCCri; 1633 case ARM::t2SUBri12: return ARM::t2SUBCCri12; 1634 case ARM::t2SUBrr: return ARM::t2SUBCCrr; 1635 case ARM::t2SUBrs: return ARM::t2SUBCCrs; 1636 } 1637} 1638 1639bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI, 1640 SmallVectorImpl<MachineOperand> &Cond, 1641 unsigned &TrueOp, unsigned &FalseOp, 1642 bool &Optimizable) const { 1643 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1644 "Unknown select instruction"); 1645 // MOVCC operands: 1646 // 0: Def. 1647 // 1: True use. 1648 // 2: False use. 1649 // 3: Condition code. 1650 // 4: CPSR use. 1651 TrueOp = 1; 1652 FalseOp = 2; 1653 Cond.push_back(MI->getOperand(3)); 1654 Cond.push_back(MI->getOperand(4)); 1655 // We can always fold a def. 1656 Optimizable = true; 1657 return false; 1658} 1659 1660MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI, 1661 bool PreferFalse) const { 1662 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1663 "Unknown select instruction"); 1664 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1665 MachineInstr *DefMI = 0; 1666 unsigned Opc = canFoldIntoMOVCC(MI->getOperand(2).getReg(), DefMI, MRI); 1667 bool Invert = !Opc; 1668 if (!Opc) 1669 Opc = canFoldIntoMOVCC(MI->getOperand(1).getReg(), DefMI, MRI); 1670 if (!Opc) 1671 return 0; 1672 1673 // Create a new predicated version of DefMI. 1674 // Rfalse is the first use. 1675 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1676 get(Opc), MI->getOperand(0).getReg()) 1677 .addOperand(MI->getOperand(Invert ? 2 : 1)); 1678 1679 // Copy all the DefMI operands, excluding its (null) predicate. 1680 const MCInstrDesc &DefDesc = DefMI->getDesc(); 1681 for (unsigned i = 1, e = DefDesc.getNumOperands(); 1682 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i) 1683 NewMI.addOperand(DefMI->getOperand(i)); 1684 1685 unsigned CondCode = MI->getOperand(3).getImm(); 1686 if (Invert) 1687 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1688 else 1689 NewMI.addImm(CondCode); 1690 NewMI.addOperand(MI->getOperand(4)); 1691 1692 // DefMI is not the -S version that sets CPSR, so add an optional %noreg. 1693 if (NewMI->hasOptionalDef()) 1694 AddDefaultCC(NewMI); 1695 1696 // The caller will erase MI, but not DefMI. 1697 DefMI->eraseFromParent(); 1698 return NewMI; 1699} 1700 1701/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 1702/// instruction is encoded with an 'S' bit is determined by the optional CPSR 1703/// def operand. 1704/// 1705/// This will go away once we can teach tblgen how to set the optional CPSR def 1706/// operand itself. 1707struct AddSubFlagsOpcodePair { 1708 uint16_t PseudoOpc; 1709 uint16_t MachineOpc; 1710}; 1711 1712static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 1713 {ARM::ADDSri, ARM::ADDri}, 1714 {ARM::ADDSrr, ARM::ADDrr}, 1715 {ARM::ADDSrsi, ARM::ADDrsi}, 1716 {ARM::ADDSrsr, ARM::ADDrsr}, 1717 1718 {ARM::SUBSri, ARM::SUBri}, 1719 {ARM::SUBSrr, ARM::SUBrr}, 1720 {ARM::SUBSrsi, ARM::SUBrsi}, 1721 {ARM::SUBSrsr, ARM::SUBrsr}, 1722 1723 {ARM::RSBSri, ARM::RSBri}, 1724 {ARM::RSBSrsi, ARM::RSBrsi}, 1725 {ARM::RSBSrsr, ARM::RSBrsr}, 1726 1727 {ARM::t2ADDSri, ARM::t2ADDri}, 1728 {ARM::t2ADDSrr, ARM::t2ADDrr}, 1729 {ARM::t2ADDSrs, ARM::t2ADDrs}, 1730 1731 {ARM::t2SUBSri, ARM::t2SUBri}, 1732 {ARM::t2SUBSrr, ARM::t2SUBrr}, 1733 {ARM::t2SUBSrs, ARM::t2SUBrs}, 1734 1735 {ARM::t2RSBSri, ARM::t2RSBri}, 1736 {ARM::t2RSBSrs, ARM::t2RSBrs}, 1737}; 1738 1739unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 1740 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i) 1741 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc) 1742 return AddSubFlagsOpcodeMap[i].MachineOpc; 1743 return 0; 1744} 1745 1746void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 1747 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 1748 unsigned DestReg, unsigned BaseReg, int NumBytes, 1749 ARMCC::CondCodes Pred, unsigned PredReg, 1750 const ARMBaseInstrInfo &TII, unsigned MIFlags) { 1751 bool isSub = NumBytes < 0; 1752 if (isSub) NumBytes = -NumBytes; 1753 1754 while (NumBytes) { 1755 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 1756 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 1757 assert(ThisVal && "Didn't extract field correctly"); 1758 1759 // We will handle these bits from offset, clear them. 1760 NumBytes &= ~ThisVal; 1761 1762 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 1763 1764 // Build the new ADD / SUB. 1765 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 1766 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 1767 .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 1768 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1769 .setMIFlags(MIFlags); 1770 BaseReg = DestReg; 1771 } 1772} 1773 1774bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1775 unsigned FrameReg, int &Offset, 1776 const ARMBaseInstrInfo &TII) { 1777 unsigned Opcode = MI.getOpcode(); 1778 const MCInstrDesc &Desc = MI.getDesc(); 1779 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1780 bool isSub = false; 1781 1782 // Memory operands in inline assembly always use AddrMode2. 1783 if (Opcode == ARM::INLINEASM) 1784 AddrMode = ARMII::AddrMode2; 1785 1786 if (Opcode == ARM::ADDri) { 1787 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 1788 if (Offset == 0) { 1789 // Turn it into a move. 1790 MI.setDesc(TII.get(ARM::MOVr)); 1791 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1792 MI.RemoveOperand(FrameRegIdx+1); 1793 Offset = 0; 1794 return true; 1795 } else if (Offset < 0) { 1796 Offset = -Offset; 1797 isSub = true; 1798 MI.setDesc(TII.get(ARM::SUBri)); 1799 } 1800 1801 // Common case: small offset, fits into instruction. 1802 if (ARM_AM::getSOImmVal(Offset) != -1) { 1803 // Replace the FrameIndex with sp / fp 1804 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1805 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 1806 Offset = 0; 1807 return true; 1808 } 1809 1810 // Otherwise, pull as much of the immedidate into this ADDri/SUBri 1811 // as possible. 1812 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 1813 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 1814 1815 // We will handle these bits from offset, clear them. 1816 Offset &= ~ThisImmVal; 1817 1818 // Get the properly encoded SOImmVal field. 1819 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 1820 "Bit extraction didn't work?"); 1821 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 1822 } else { 1823 unsigned ImmIdx = 0; 1824 int InstrOffs = 0; 1825 unsigned NumBits = 0; 1826 unsigned Scale = 1; 1827 switch (AddrMode) { 1828 case ARMII::AddrMode_i12: { 1829 ImmIdx = FrameRegIdx + 1; 1830 InstrOffs = MI.getOperand(ImmIdx).getImm(); 1831 NumBits = 12; 1832 break; 1833 } 1834 case ARMII::AddrMode2: { 1835 ImmIdx = FrameRegIdx+2; 1836 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 1837 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1838 InstrOffs *= -1; 1839 NumBits = 12; 1840 break; 1841 } 1842 case ARMII::AddrMode3: { 1843 ImmIdx = FrameRegIdx+2; 1844 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 1845 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1846 InstrOffs *= -1; 1847 NumBits = 8; 1848 break; 1849 } 1850 case ARMII::AddrMode4: 1851 case ARMII::AddrMode6: 1852 // Can't fold any offset even if it's zero. 1853 return false; 1854 case ARMII::AddrMode5: { 1855 ImmIdx = FrameRegIdx+1; 1856 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 1857 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1858 InstrOffs *= -1; 1859 NumBits = 8; 1860 Scale = 4; 1861 break; 1862 } 1863 default: 1864 llvm_unreachable("Unsupported addressing mode!"); 1865 } 1866 1867 Offset += InstrOffs * Scale; 1868 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 1869 if (Offset < 0) { 1870 Offset = -Offset; 1871 isSub = true; 1872 } 1873 1874 // Attempt to fold address comp. if opcode has offset bits 1875 if (NumBits > 0) { 1876 // Common case: small offset, fits into instruction. 1877 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 1878 int ImmedOffset = Offset / Scale; 1879 unsigned Mask = (1 << NumBits) - 1; 1880 if ((unsigned)Offset <= Mask * Scale) { 1881 // Replace the FrameIndex with sp 1882 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 1883 // FIXME: When addrmode2 goes away, this will simplify (like the 1884 // T2 version), as the LDR.i12 versions don't need the encoding 1885 // tricks for the offset value. 1886 if (isSub) { 1887 if (AddrMode == ARMII::AddrMode_i12) 1888 ImmedOffset = -ImmedOffset; 1889 else 1890 ImmedOffset |= 1 << NumBits; 1891 } 1892 ImmOp.ChangeToImmediate(ImmedOffset); 1893 Offset = 0; 1894 return true; 1895 } 1896 1897 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 1898 ImmedOffset = ImmedOffset & Mask; 1899 if (isSub) { 1900 if (AddrMode == ARMII::AddrMode_i12) 1901 ImmedOffset = -ImmedOffset; 1902 else 1903 ImmedOffset |= 1 << NumBits; 1904 } 1905 ImmOp.ChangeToImmediate(ImmedOffset); 1906 Offset &= ~(Mask*Scale); 1907 } 1908 } 1909 1910 Offset = (isSub) ? -Offset : Offset; 1911 return Offset == 0; 1912} 1913 1914/// analyzeCompare - For a comparison instruction, return the source registers 1915/// in SrcReg and SrcReg2 if having two register operands, and the value it 1916/// compares against in CmpValue. Return true if the comparison instruction 1917/// can be analyzed. 1918bool ARMBaseInstrInfo:: 1919analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 1920 int &CmpMask, int &CmpValue) const { 1921 switch (MI->getOpcode()) { 1922 default: break; 1923 case ARM::CMPri: 1924 case ARM::t2CMPri: 1925 SrcReg = MI->getOperand(0).getReg(); 1926 SrcReg2 = 0; 1927 CmpMask = ~0; 1928 CmpValue = MI->getOperand(1).getImm(); 1929 return true; 1930 case ARM::CMPrr: 1931 case ARM::t2CMPrr: 1932 SrcReg = MI->getOperand(0).getReg(); 1933 SrcReg2 = MI->getOperand(1).getReg(); 1934 CmpMask = ~0; 1935 CmpValue = 0; 1936 return true; 1937 case ARM::TSTri: 1938 case ARM::t2TSTri: 1939 SrcReg = MI->getOperand(0).getReg(); 1940 SrcReg2 = 0; 1941 CmpMask = MI->getOperand(1).getImm(); 1942 CmpValue = 0; 1943 return true; 1944 } 1945 1946 return false; 1947} 1948 1949/// isSuitableForMask - Identify a suitable 'and' instruction that 1950/// operates on the given source register and applies the same mask 1951/// as a 'tst' instruction. Provide a limited look-through for copies. 1952/// When successful, MI will hold the found instruction. 1953static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 1954 int CmpMask, bool CommonUse) { 1955 switch (MI->getOpcode()) { 1956 case ARM::ANDri: 1957 case ARM::t2ANDri: 1958 if (CmpMask != MI->getOperand(2).getImm()) 1959 return false; 1960 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 1961 return true; 1962 break; 1963 case ARM::COPY: { 1964 // Walk down one instruction which is potentially an 'and'. 1965 const MachineInstr &Copy = *MI; 1966 MachineBasicBlock::iterator AND( 1967 llvm::next(MachineBasicBlock::iterator(MI))); 1968 if (AND == MI->getParent()->end()) return false; 1969 MI = AND; 1970 return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 1971 CmpMask, true); 1972 } 1973 } 1974 1975 return false; 1976} 1977 1978/// getSwappedCondition - assume the flags are set by MI(a,b), return 1979/// the condition code if we modify the instructions such that flags are 1980/// set by MI(b,a). 1981inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { 1982 switch (CC) { 1983 default: return ARMCC::AL; 1984 case ARMCC::EQ: return ARMCC::EQ; 1985 case ARMCC::NE: return ARMCC::NE; 1986 case ARMCC::HS: return ARMCC::LS; 1987 case ARMCC::LO: return ARMCC::HI; 1988 case ARMCC::HI: return ARMCC::LO; 1989 case ARMCC::LS: return ARMCC::HS; 1990 case ARMCC::GE: return ARMCC::LE; 1991 case ARMCC::LT: return ARMCC::GT; 1992 case ARMCC::GT: return ARMCC::LT; 1993 case ARMCC::LE: return ARMCC::GE; 1994 } 1995} 1996 1997/// isRedundantFlagInstr - check whether the first instruction, whose only 1998/// purpose is to update flags, can be made redundant. 1999/// CMPrr can be made redundant by SUBrr if the operands are the same. 2000/// CMPri can be made redundant by SUBri if the operands are the same. 2001/// This function can be extended later on. 2002inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, 2003 unsigned SrcReg2, int ImmValue, 2004 MachineInstr *OI) { 2005 if ((CmpI->getOpcode() == ARM::CMPrr || 2006 CmpI->getOpcode() == ARM::t2CMPrr) && 2007 (OI->getOpcode() == ARM::SUBrr || 2008 OI->getOpcode() == ARM::t2SUBrr) && 2009 ((OI->getOperand(1).getReg() == SrcReg && 2010 OI->getOperand(2).getReg() == SrcReg2) || 2011 (OI->getOperand(1).getReg() == SrcReg2 && 2012 OI->getOperand(2).getReg() == SrcReg))) 2013 return true; 2014 2015 if ((CmpI->getOpcode() == ARM::CMPri || 2016 CmpI->getOpcode() == ARM::t2CMPri) && 2017 (OI->getOpcode() == ARM::SUBri || 2018 OI->getOpcode() == ARM::t2SUBri) && 2019 OI->getOperand(1).getReg() == SrcReg && 2020 OI->getOperand(2).getImm() == ImmValue) 2021 return true; 2022 return false; 2023} 2024 2025/// optimizeCompareInstr - Convert the instruction supplying the argument to the 2026/// comparison into one that sets the zero bit in the flags register; 2027/// Remove a redundant Compare instruction if an earlier instruction can set the 2028/// flags in the same way as Compare. 2029/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two 2030/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the 2031/// condition code of instructions which use the flags. 2032bool ARMBaseInstrInfo:: 2033optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 2034 int CmpMask, int CmpValue, 2035 const MachineRegisterInfo *MRI) const { 2036 // Get the unique definition of SrcReg. 2037 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 2038 if (!MI) return false; 2039 2040 // Masked compares sometimes use the same register as the corresponding 'and'. 2041 if (CmpMask != ~0) { 2042 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) { 2043 MI = 0; 2044 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), 2045 UE = MRI->use_end(); UI != UE; ++UI) { 2046 if (UI->getParent() != CmpInstr->getParent()) continue; 2047 MachineInstr *PotentialAND = &*UI; 2048 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true)) 2049 continue; 2050 MI = PotentialAND; 2051 break; 2052 } 2053 if (!MI) return false; 2054 } 2055 } 2056 2057 // Get ready to iterate backward from CmpInstr. 2058 MachineBasicBlock::iterator I = CmpInstr, E = MI, 2059 B = CmpInstr->getParent()->begin(); 2060 2061 // Early exit if CmpInstr is at the beginning of the BB. 2062 if (I == B) return false; 2063 2064 // There are two possible candidates which can be changed to set CPSR: 2065 // One is MI, the other is a SUB instruction. 2066 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 2067 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 2068 MachineInstr *Sub = NULL; 2069 if (SrcReg2 != 0) 2070 // MI is not a candidate for CMPrr. 2071 MI = NULL; 2072 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 2073 // Conservatively refuse to convert an instruction which isn't in the same 2074 // BB as the comparison. 2075 // For CMPri, we need to check Sub, thus we can't return here. 2076 if (CmpInstr->getOpcode() == ARM::CMPri || 2077 CmpInstr->getOpcode() == ARM::t2CMPri) 2078 MI = NULL; 2079 else 2080 return false; 2081 } 2082 2083 // Check that CPSR isn't set between the comparison instruction and the one we 2084 // want to change. At the same time, search for Sub. 2085 const TargetRegisterInfo *TRI = &getRegisterInfo(); 2086 --I; 2087 for (; I != E; --I) { 2088 const MachineInstr &Instr = *I; 2089 2090 if (Instr.modifiesRegister(ARM::CPSR, TRI) || 2091 Instr.readsRegister(ARM::CPSR, TRI)) 2092 // This instruction modifies or uses CPSR after the one we want to 2093 // change. We can't do this transformation. 2094 return false; 2095 2096 // Check whether CmpInstr can be made redundant by the current instruction. 2097 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 2098 Sub = &*I; 2099 break; 2100 } 2101 2102 if (I == B) 2103 // The 'and' is below the comparison instruction. 2104 return false; 2105 } 2106 2107 // Return false if no candidates exist. 2108 if (!MI && !Sub) 2109 return false; 2110 2111 // The single candidate is called MI. 2112 if (!MI) MI = Sub; 2113 2114 switch (MI->getOpcode()) { 2115 default: break; 2116 case ARM::RSBrr: 2117 case ARM::RSBri: 2118 case ARM::RSCrr: 2119 case ARM::RSCri: 2120 case ARM::ADDrr: 2121 case ARM::ADDri: 2122 case ARM::ADCrr: 2123 case ARM::ADCri: 2124 case ARM::SUBrr: 2125 case ARM::SUBri: 2126 case ARM::SBCrr: 2127 case ARM::SBCri: 2128 case ARM::t2RSBri: 2129 case ARM::t2ADDrr: 2130 case ARM::t2ADDri: 2131 case ARM::t2ADCrr: 2132 case ARM::t2ADCri: 2133 case ARM::t2SUBrr: 2134 case ARM::t2SUBri: 2135 case ARM::t2SBCrr: 2136 case ARM::t2SBCri: 2137 case ARM::ANDrr: 2138 case ARM::ANDri: 2139 case ARM::t2ANDrr: 2140 case ARM::t2ANDri: 2141 case ARM::ORRrr: 2142 case ARM::ORRri: 2143 case ARM::t2ORRrr: 2144 case ARM::t2ORRri: 2145 case ARM::EORrr: 2146 case ARM::EORri: 2147 case ARM::t2EORrr: 2148 case ARM::t2EORri: { 2149 // Scan forward for the use of CPSR 2150 // When checking against MI: if it's a conditional code requires 2151 // checking of V bit, then this is not safe to do. 2152 // It is safe to remove CmpInstr if CPSR is redefined or killed. 2153 // If we are done with the basic block, we need to check whether CPSR is 2154 // live-out. 2155 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> 2156 OperandsToUpdate; 2157 bool isSafe = false; 2158 I = CmpInstr; 2159 E = CmpInstr->getParent()->end(); 2160 while (!isSafe && ++I != E) { 2161 const MachineInstr &Instr = *I; 2162 for (unsigned IO = 0, EO = Instr.getNumOperands(); 2163 !isSafe && IO != EO; ++IO) { 2164 const MachineOperand &MO = Instr.getOperand(IO); 2165 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 2166 isSafe = true; 2167 break; 2168 } 2169 if (!MO.isReg() || MO.getReg() != ARM::CPSR) 2170 continue; 2171 if (MO.isDef()) { 2172 isSafe = true; 2173 break; 2174 } 2175 // Condition code is after the operand before CPSR. 2176 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm(); 2177 if (Sub) { 2178 ARMCC::CondCodes NewCC = getSwappedCondition(CC); 2179 if (NewCC == ARMCC::AL) 2180 return false; 2181 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 2182 // on CMP needs to be updated to be based on SUB. 2183 // Push the condition code operands to OperandsToUpdate. 2184 // If it is safe to remove CmpInstr, the condition code of these 2185 // operands will be modified. 2186 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 2187 Sub->getOperand(2).getReg() == SrcReg) 2188 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)), 2189 NewCC)); 2190 } 2191 else 2192 switch (CC) { 2193 default: 2194 // CPSR can be used multiple times, we should continue. 2195 break; 2196 case ARMCC::VS: 2197 case ARMCC::VC: 2198 case ARMCC::GE: 2199 case ARMCC::LT: 2200 case ARMCC::GT: 2201 case ARMCC::LE: 2202 return false; 2203 } 2204 } 2205 } 2206 2207 // If CPSR is not killed nor re-defined, we should check whether it is 2208 // live-out. If it is live-out, do not optimize. 2209 if (!isSafe) { 2210 MachineBasicBlock *MBB = CmpInstr->getParent(); 2211 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 2212 SE = MBB->succ_end(); SI != SE; ++SI) 2213 if ((*SI)->isLiveIn(ARM::CPSR)) 2214 return false; 2215 } 2216 2217 // Toggle the optional operand to CPSR. 2218 MI->getOperand(5).setReg(ARM::CPSR); 2219 MI->getOperand(5).setIsDef(true); 2220 CmpInstr->eraseFromParent(); 2221 2222 // Modify the condition code of operands in OperandsToUpdate. 2223 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2224 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 2225 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) 2226 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); 2227 return true; 2228 } 2229 } 2230 2231 return false; 2232} 2233 2234bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2235 MachineInstr *DefMI, unsigned Reg, 2236 MachineRegisterInfo *MRI) const { 2237 // Fold large immediates into add, sub, or, xor. 2238 unsigned DefOpc = DefMI->getOpcode(); 2239 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2240 return false; 2241 if (!DefMI->getOperand(1).isImm()) 2242 // Could be t2MOVi32imm <ga:xx> 2243 return false; 2244 2245 if (!MRI->hasOneNonDBGUse(Reg)) 2246 return false; 2247 2248 const MCInstrDesc &DefMCID = DefMI->getDesc(); 2249 if (DefMCID.hasOptionalDef()) { 2250 unsigned NumOps = DefMCID.getNumOperands(); 2251 const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2252 if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2253 // If DefMI defines CPSR and it is not dead, it's obviously not safe 2254 // to delete DefMI. 2255 return false; 2256 } 2257 2258 const MCInstrDesc &UseMCID = UseMI->getDesc(); 2259 if (UseMCID.hasOptionalDef()) { 2260 unsigned NumOps = UseMCID.getNumOperands(); 2261 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2262 // If the instruction sets the flag, do not attempt this optimization 2263 // since it may change the semantics of the code. 2264 return false; 2265 } 2266 2267 unsigned UseOpc = UseMI->getOpcode(); 2268 unsigned NewUseOpc = 0; 2269 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 2270 uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2271 bool Commute = false; 2272 switch (UseOpc) { 2273 default: return false; 2274 case ARM::SUBrr: 2275 case ARM::ADDrr: 2276 case ARM::ORRrr: 2277 case ARM::EORrr: 2278 case ARM::t2SUBrr: 2279 case ARM::t2ADDrr: 2280 case ARM::t2ORRrr: 2281 case ARM::t2EORrr: { 2282 Commute = UseMI->getOperand(2).getReg() != Reg; 2283 switch (UseOpc) { 2284 default: break; 2285 case ARM::SUBrr: { 2286 if (Commute) 2287 return false; 2288 ImmVal = -ImmVal; 2289 NewUseOpc = ARM::SUBri; 2290 // Fallthrough 2291 } 2292 case ARM::ADDrr: 2293 case ARM::ORRrr: 2294 case ARM::EORrr: { 2295 if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2296 return false; 2297 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2298 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2299 switch (UseOpc) { 2300 default: break; 2301 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2302 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2303 case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2304 } 2305 break; 2306 } 2307 case ARM::t2SUBrr: { 2308 if (Commute) 2309 return false; 2310 ImmVal = -ImmVal; 2311 NewUseOpc = ARM::t2SUBri; 2312 // Fallthrough 2313 } 2314 case ARM::t2ADDrr: 2315 case ARM::t2ORRrr: 2316 case ARM::t2EORrr: { 2317 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2318 return false; 2319 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2320 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2321 switch (UseOpc) { 2322 default: break; 2323 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2324 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2325 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2326 } 2327 break; 2328 } 2329 } 2330 } 2331 } 2332 2333 unsigned OpIdx = Commute ? 2 : 1; 2334 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2335 bool isKill = UseMI->getOperand(OpIdx).isKill(); 2336 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2337 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2338 UseMI, UseMI->getDebugLoc(), 2339 get(NewUseOpc), NewReg) 2340 .addReg(Reg1, getKillRegState(isKill)) 2341 .addImm(SOImmValV1))); 2342 UseMI->setDesc(get(NewUseOpc)); 2343 UseMI->getOperand(1).setReg(NewReg); 2344 UseMI->getOperand(1).setIsKill(); 2345 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2346 DefMI->eraseFromParent(); 2347 return true; 2348} 2349 2350unsigned 2351ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 2352 const MachineInstr *MI) const { 2353 if (!ItinData || ItinData->isEmpty()) 2354 return 1; 2355 2356 const MCInstrDesc &Desc = MI->getDesc(); 2357 unsigned Class = Desc.getSchedClass(); 2358 int ItinUOps = ItinData->getNumMicroOps(Class); 2359 if (ItinUOps >= 0) 2360 return ItinUOps; 2361 2362 unsigned Opc = MI->getOpcode(); 2363 switch (Opc) { 2364 default: 2365 llvm_unreachable("Unexpected multi-uops instruction!"); 2366 case ARM::VLDMQIA: 2367 case ARM::VSTMQIA: 2368 return 2; 2369 2370 // The number of uOps for load / store multiple are determined by the number 2371 // registers. 2372 // 2373 // On Cortex-A8, each pair of register loads / stores can be scheduled on the 2374 // same cycle. The scheduling for the first load / store must be done 2375 // separately by assuming the address is not 64-bit aligned. 2376 // 2377 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 2378 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 2379 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 2380 case ARM::VLDMDIA: 2381 case ARM::VLDMDIA_UPD: 2382 case ARM::VLDMDDB_UPD: 2383 case ARM::VLDMSIA: 2384 case ARM::VLDMSIA_UPD: 2385 case ARM::VLDMSDB_UPD: 2386 case ARM::VSTMDIA: 2387 case ARM::VSTMDIA_UPD: 2388 case ARM::VSTMDDB_UPD: 2389 case ARM::VSTMSIA: 2390 case ARM::VSTMSIA_UPD: 2391 case ARM::VSTMSDB_UPD: { 2392 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 2393 return (NumRegs / 2) + (NumRegs % 2) + 1; 2394 } 2395 2396 case ARM::LDMIA_RET: 2397 case ARM::LDMIA: 2398 case ARM::LDMDA: 2399 case ARM::LDMDB: 2400 case ARM::LDMIB: 2401 case ARM::LDMIA_UPD: 2402 case ARM::LDMDA_UPD: 2403 case ARM::LDMDB_UPD: 2404 case ARM::LDMIB_UPD: 2405 case ARM::STMIA: 2406 case ARM::STMDA: 2407 case ARM::STMDB: 2408 case ARM::STMIB: 2409 case ARM::STMIA_UPD: 2410 case ARM::STMDA_UPD: 2411 case ARM::STMDB_UPD: 2412 case ARM::STMIB_UPD: 2413 case ARM::tLDMIA: 2414 case ARM::tLDMIA_UPD: 2415 case ARM::tSTMIA_UPD: 2416 case ARM::tPOP_RET: 2417 case ARM::tPOP: 2418 case ARM::tPUSH: 2419 case ARM::t2LDMIA_RET: 2420 case ARM::t2LDMIA: 2421 case ARM::t2LDMDB: 2422 case ARM::t2LDMIA_UPD: 2423 case ARM::t2LDMDB_UPD: 2424 case ARM::t2STMIA: 2425 case ARM::t2STMDB: 2426 case ARM::t2STMIA_UPD: 2427 case ARM::t2STMDB_UPD: { 2428 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 2429 if (Subtarget.isCortexA8()) { 2430 if (NumRegs < 4) 2431 return 2; 2432 // 4 registers would be issued: 2, 2. 2433 // 5 registers would be issued: 2, 2, 1. 2434 int A8UOps = (NumRegs / 2); 2435 if (NumRegs % 2) 2436 ++A8UOps; 2437 return A8UOps; 2438 } else if (Subtarget.isCortexA9()) { 2439 int A9UOps = (NumRegs / 2); 2440 // If there are odd number of registers or if it's not 64-bit aligned, 2441 // then it takes an extra AGU (Address Generation Unit) cycle. 2442 if ((NumRegs % 2) || 2443 !MI->hasOneMemOperand() || 2444 (*MI->memoperands_begin())->getAlignment() < 8) 2445 ++A9UOps; 2446 return A9UOps; 2447 } else { 2448 // Assume the worst. 2449 return NumRegs; 2450 } 2451 } 2452 } 2453} 2454 2455int 2456ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 2457 const MCInstrDesc &DefMCID, 2458 unsigned DefClass, 2459 unsigned DefIdx, unsigned DefAlign) const { 2460 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2461 if (RegNo <= 0) 2462 // Def is the address writeback. 2463 return ItinData->getOperandCycle(DefClass, DefIdx); 2464 2465 int DefCycle; 2466 if (Subtarget.isCortexA8()) { 2467 // (regno / 2) + (regno % 2) + 1 2468 DefCycle = RegNo / 2 + 1; 2469 if (RegNo % 2) 2470 ++DefCycle; 2471 } else if (Subtarget.isCortexA9()) { 2472 DefCycle = RegNo; 2473 bool isSLoad = false; 2474 2475 switch (DefMCID.getOpcode()) { 2476 default: break; 2477 case ARM::VLDMSIA: 2478 case ARM::VLDMSIA_UPD: 2479 case ARM::VLDMSDB_UPD: 2480 isSLoad = true; 2481 break; 2482 } 2483 2484 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2485 // then it takes an extra cycle. 2486 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2487 ++DefCycle; 2488 } else { 2489 // Assume the worst. 2490 DefCycle = RegNo + 2; 2491 } 2492 2493 return DefCycle; 2494} 2495 2496int 2497ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 2498 const MCInstrDesc &DefMCID, 2499 unsigned DefClass, 2500 unsigned DefIdx, unsigned DefAlign) const { 2501 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2502 if (RegNo <= 0) 2503 // Def is the address writeback. 2504 return ItinData->getOperandCycle(DefClass, DefIdx); 2505 2506 int DefCycle; 2507 if (Subtarget.isCortexA8()) { 2508 // 4 registers would be issued: 1, 2, 1. 2509 // 5 registers would be issued: 1, 2, 2. 2510 DefCycle = RegNo / 2; 2511 if (DefCycle < 1) 2512 DefCycle = 1; 2513 // Result latency is issue cycle + 2: E2. 2514 DefCycle += 2; 2515 } else if (Subtarget.isCortexA9()) { 2516 DefCycle = (RegNo / 2); 2517 // If there are odd number of registers or if it's not 64-bit aligned, 2518 // then it takes an extra AGU (Address Generation Unit) cycle. 2519 if ((RegNo % 2) || DefAlign < 8) 2520 ++DefCycle; 2521 // Result latency is AGU cycles + 2. 2522 DefCycle += 2; 2523 } else { 2524 // Assume the worst. 2525 DefCycle = RegNo + 2; 2526 } 2527 2528 return DefCycle; 2529} 2530 2531int 2532ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 2533 const MCInstrDesc &UseMCID, 2534 unsigned UseClass, 2535 unsigned UseIdx, unsigned UseAlign) const { 2536 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2537 if (RegNo <= 0) 2538 return ItinData->getOperandCycle(UseClass, UseIdx); 2539 2540 int UseCycle; 2541 if (Subtarget.isCortexA8()) { 2542 // (regno / 2) + (regno % 2) + 1 2543 UseCycle = RegNo / 2 + 1; 2544 if (RegNo % 2) 2545 ++UseCycle; 2546 } else if (Subtarget.isCortexA9()) { 2547 UseCycle = RegNo; 2548 bool isSStore = false; 2549 2550 switch (UseMCID.getOpcode()) { 2551 default: break; 2552 case ARM::VSTMSIA: 2553 case ARM::VSTMSIA_UPD: 2554 case ARM::VSTMSDB_UPD: 2555 isSStore = true; 2556 break; 2557 } 2558 2559 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 2560 // then it takes an extra cycle. 2561 if ((isSStore && (RegNo % 2)) || UseAlign < 8) 2562 ++UseCycle; 2563 } else { 2564 // Assume the worst. 2565 UseCycle = RegNo + 2; 2566 } 2567 2568 return UseCycle; 2569} 2570 2571int 2572ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 2573 const MCInstrDesc &UseMCID, 2574 unsigned UseClass, 2575 unsigned UseIdx, unsigned UseAlign) const { 2576 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 2577 if (RegNo <= 0) 2578 return ItinData->getOperandCycle(UseClass, UseIdx); 2579 2580 int UseCycle; 2581 if (Subtarget.isCortexA8()) { 2582 UseCycle = RegNo / 2; 2583 if (UseCycle < 2) 2584 UseCycle = 2; 2585 // Read in E3. 2586 UseCycle += 2; 2587 } else if (Subtarget.isCortexA9()) { 2588 UseCycle = (RegNo / 2); 2589 // If there are odd number of registers or if it's not 64-bit aligned, 2590 // then it takes an extra AGU (Address Generation Unit) cycle. 2591 if ((RegNo % 2) || UseAlign < 8) 2592 ++UseCycle; 2593 } else { 2594 // Assume the worst. 2595 UseCycle = 1; 2596 } 2597 return UseCycle; 2598} 2599 2600int 2601ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2602 const MCInstrDesc &DefMCID, 2603 unsigned DefIdx, unsigned DefAlign, 2604 const MCInstrDesc &UseMCID, 2605 unsigned UseIdx, unsigned UseAlign) const { 2606 unsigned DefClass = DefMCID.getSchedClass(); 2607 unsigned UseClass = UseMCID.getSchedClass(); 2608 2609 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2610 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2611 2612 // This may be a def / use of a variable_ops instruction, the operand 2613 // latency might be determinable dynamically. Let the target try to 2614 // figure it out. 2615 int DefCycle = -1; 2616 bool LdmBypass = false; 2617 switch (DefMCID.getOpcode()) { 2618 default: 2619 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2620 break; 2621 2622 case ARM::VLDMDIA: 2623 case ARM::VLDMDIA_UPD: 2624 case ARM::VLDMDDB_UPD: 2625 case ARM::VLDMSIA: 2626 case ARM::VLDMSIA_UPD: 2627 case ARM::VLDMSDB_UPD: 2628 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2629 break; 2630 2631 case ARM::LDMIA_RET: 2632 case ARM::LDMIA: 2633 case ARM::LDMDA: 2634 case ARM::LDMDB: 2635 case ARM::LDMIB: 2636 case ARM::LDMIA_UPD: 2637 case ARM::LDMDA_UPD: 2638 case ARM::LDMDB_UPD: 2639 case ARM::LDMIB_UPD: 2640 case ARM::tLDMIA: 2641 case ARM::tLDMIA_UPD: 2642 case ARM::tPUSH: 2643 case ARM::t2LDMIA_RET: 2644 case ARM::t2LDMIA: 2645 case ARM::t2LDMDB: 2646 case ARM::t2LDMIA_UPD: 2647 case ARM::t2LDMDB_UPD: 2648 LdmBypass = 1; 2649 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 2650 break; 2651 } 2652 2653 if (DefCycle == -1) 2654 // We can't seem to determine the result latency of the def, assume it's 2. 2655 DefCycle = 2; 2656 2657 int UseCycle = -1; 2658 switch (UseMCID.getOpcode()) { 2659 default: 2660 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 2661 break; 2662 2663 case ARM::VSTMDIA: 2664 case ARM::VSTMDIA_UPD: 2665 case ARM::VSTMDDB_UPD: 2666 case ARM::VSTMSIA: 2667 case ARM::VSTMSIA_UPD: 2668 case ARM::VSTMSDB_UPD: 2669 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 2670 break; 2671 2672 case ARM::STMIA: 2673 case ARM::STMDA: 2674 case ARM::STMDB: 2675 case ARM::STMIB: 2676 case ARM::STMIA_UPD: 2677 case ARM::STMDA_UPD: 2678 case ARM::STMDB_UPD: 2679 case ARM::STMIB_UPD: 2680 case ARM::tSTMIA_UPD: 2681 case ARM::tPOP_RET: 2682 case ARM::tPOP: 2683 case ARM::t2STMIA: 2684 case ARM::t2STMDB: 2685 case ARM::t2STMIA_UPD: 2686 case ARM::t2STMDB_UPD: 2687 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 2688 break; 2689 } 2690 2691 if (UseCycle == -1) 2692 // Assume it's read in the first stage. 2693 UseCycle = 1; 2694 2695 UseCycle = DefCycle - UseCycle + 1; 2696 if (UseCycle > 0) { 2697 if (LdmBypass) { 2698 // It's a variable_ops instruction so we can't use DefIdx here. Just use 2699 // first def operand. 2700 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 2701 UseClass, UseIdx)) 2702 --UseCycle; 2703 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 2704 UseClass, UseIdx)) { 2705 --UseCycle; 2706 } 2707 } 2708 2709 return UseCycle; 2710} 2711 2712static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 2713 const MachineInstr *MI, unsigned Reg, 2714 unsigned &DefIdx, unsigned &Dist) { 2715 Dist = 0; 2716 2717 MachineBasicBlock::const_iterator I = MI; ++I; 2718 MachineBasicBlock::const_instr_iterator II = 2719 llvm::prior(I.getInstrIterator()); 2720 assert(II->isInsideBundle() && "Empty bundle?"); 2721 2722 int Idx = -1; 2723 while (II->isInsideBundle()) { 2724 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 2725 if (Idx != -1) 2726 break; 2727 --II; 2728 ++Dist; 2729 } 2730 2731 assert(Idx != -1 && "Cannot find bundled definition!"); 2732 DefIdx = Idx; 2733 return II; 2734} 2735 2736static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 2737 const MachineInstr *MI, unsigned Reg, 2738 unsigned &UseIdx, unsigned &Dist) { 2739 Dist = 0; 2740 2741 MachineBasicBlock::const_instr_iterator II = MI; ++II; 2742 assert(II->isInsideBundle() && "Empty bundle?"); 2743 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 2744 2745 // FIXME: This doesn't properly handle multiple uses. 2746 int Idx = -1; 2747 while (II != E && II->isInsideBundle()) { 2748 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 2749 if (Idx != -1) 2750 break; 2751 if (II->getOpcode() != ARM::t2IT) 2752 ++Dist; 2753 ++II; 2754 } 2755 2756 if (Idx == -1) { 2757 Dist = 0; 2758 return 0; 2759 } 2760 2761 UseIdx = Idx; 2762 return II; 2763} 2764 2765/// Return the number of cycles to add to (or subtract from) the static 2766/// itinerary based on the def opcode and alignment. The caller will ensure that 2767/// adjusted latency is at least one cycle. 2768static int adjustDefLatency(const ARMSubtarget &Subtarget, 2769 const MachineInstr *DefMI, 2770 const MCInstrDesc *DefMCID, unsigned DefAlign) { 2771 int Adjust = 0; 2772 if (Subtarget.isCortexA8() || Subtarget.isCortexA9()) { 2773 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 2774 // variants are one cycle cheaper. 2775 switch (DefMCID->getOpcode()) { 2776 default: break; 2777 case ARM::LDRrs: 2778 case ARM::LDRBrs: { 2779 unsigned ShOpVal = DefMI->getOperand(3).getImm(); 2780 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2781 if (ShImm == 0 || 2782 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 2783 --Adjust; 2784 break; 2785 } 2786 case ARM::t2LDRs: 2787 case ARM::t2LDRBs: 2788 case ARM::t2LDRHs: 2789 case ARM::t2LDRSHs: { 2790 // Thumb2 mode: lsl only. 2791 unsigned ShAmt = DefMI->getOperand(3).getImm(); 2792 if (ShAmt == 0 || ShAmt == 2) 2793 --Adjust; 2794 break; 2795 } 2796 } 2797 } 2798 2799 if (DefAlign < 8 && Subtarget.isCortexA9()) { 2800 switch (DefMCID->getOpcode()) { 2801 default: break; 2802 case ARM::VLD1q8: 2803 case ARM::VLD1q16: 2804 case ARM::VLD1q32: 2805 case ARM::VLD1q64: 2806 case ARM::VLD1q8wb_fixed: 2807 case ARM::VLD1q16wb_fixed: 2808 case ARM::VLD1q32wb_fixed: 2809 case ARM::VLD1q64wb_fixed: 2810 case ARM::VLD1q8wb_register: 2811 case ARM::VLD1q16wb_register: 2812 case ARM::VLD1q32wb_register: 2813 case ARM::VLD1q64wb_register: 2814 case ARM::VLD2d8: 2815 case ARM::VLD2d16: 2816 case ARM::VLD2d32: 2817 case ARM::VLD2q8: 2818 case ARM::VLD2q16: 2819 case ARM::VLD2q32: 2820 case ARM::VLD2d8wb_fixed: 2821 case ARM::VLD2d16wb_fixed: 2822 case ARM::VLD2d32wb_fixed: 2823 case ARM::VLD2q8wb_fixed: 2824 case ARM::VLD2q16wb_fixed: 2825 case ARM::VLD2q32wb_fixed: 2826 case ARM::VLD2d8wb_register: 2827 case ARM::VLD2d16wb_register: 2828 case ARM::VLD2d32wb_register: 2829 case ARM::VLD2q8wb_register: 2830 case ARM::VLD2q16wb_register: 2831 case ARM::VLD2q32wb_register: 2832 case ARM::VLD3d8: 2833 case ARM::VLD3d16: 2834 case ARM::VLD3d32: 2835 case ARM::VLD1d64T: 2836 case ARM::VLD3d8_UPD: 2837 case ARM::VLD3d16_UPD: 2838 case ARM::VLD3d32_UPD: 2839 case ARM::VLD1d64Twb_fixed: 2840 case ARM::VLD1d64Twb_register: 2841 case ARM::VLD3q8_UPD: 2842 case ARM::VLD3q16_UPD: 2843 case ARM::VLD3q32_UPD: 2844 case ARM::VLD4d8: 2845 case ARM::VLD4d16: 2846 case ARM::VLD4d32: 2847 case ARM::VLD1d64Q: 2848 case ARM::VLD4d8_UPD: 2849 case ARM::VLD4d16_UPD: 2850 case ARM::VLD4d32_UPD: 2851 case ARM::VLD1d64Qwb_fixed: 2852 case ARM::VLD1d64Qwb_register: 2853 case ARM::VLD4q8_UPD: 2854 case ARM::VLD4q16_UPD: 2855 case ARM::VLD4q32_UPD: 2856 case ARM::VLD1DUPq8: 2857 case ARM::VLD1DUPq16: 2858 case ARM::VLD1DUPq32: 2859 case ARM::VLD1DUPq8wb_fixed: 2860 case ARM::VLD1DUPq16wb_fixed: 2861 case ARM::VLD1DUPq32wb_fixed: 2862 case ARM::VLD1DUPq8wb_register: 2863 case ARM::VLD1DUPq16wb_register: 2864 case ARM::VLD1DUPq32wb_register: 2865 case ARM::VLD2DUPd8: 2866 case ARM::VLD2DUPd16: 2867 case ARM::VLD2DUPd32: 2868 case ARM::VLD2DUPd8wb_fixed: 2869 case ARM::VLD2DUPd16wb_fixed: 2870 case ARM::VLD2DUPd32wb_fixed: 2871 case ARM::VLD2DUPd8wb_register: 2872 case ARM::VLD2DUPd16wb_register: 2873 case ARM::VLD2DUPd32wb_register: 2874 case ARM::VLD4DUPd8: 2875 case ARM::VLD4DUPd16: 2876 case ARM::VLD4DUPd32: 2877 case ARM::VLD4DUPd8_UPD: 2878 case ARM::VLD4DUPd16_UPD: 2879 case ARM::VLD4DUPd32_UPD: 2880 case ARM::VLD1LNd8: 2881 case ARM::VLD1LNd16: 2882 case ARM::VLD1LNd32: 2883 case ARM::VLD1LNd8_UPD: 2884 case ARM::VLD1LNd16_UPD: 2885 case ARM::VLD1LNd32_UPD: 2886 case ARM::VLD2LNd8: 2887 case ARM::VLD2LNd16: 2888 case ARM::VLD2LNd32: 2889 case ARM::VLD2LNq16: 2890 case ARM::VLD2LNq32: 2891 case ARM::VLD2LNd8_UPD: 2892 case ARM::VLD2LNd16_UPD: 2893 case ARM::VLD2LNd32_UPD: 2894 case ARM::VLD2LNq16_UPD: 2895 case ARM::VLD2LNq32_UPD: 2896 case ARM::VLD4LNd8: 2897 case ARM::VLD4LNd16: 2898 case ARM::VLD4LNd32: 2899 case ARM::VLD4LNq16: 2900 case ARM::VLD4LNq32: 2901 case ARM::VLD4LNd8_UPD: 2902 case ARM::VLD4LNd16_UPD: 2903 case ARM::VLD4LNd32_UPD: 2904 case ARM::VLD4LNq16_UPD: 2905 case ARM::VLD4LNq32_UPD: 2906 // If the address is not 64-bit aligned, the latencies of these 2907 // instructions increases by one. 2908 ++Adjust; 2909 break; 2910 } 2911 } 2912 return Adjust; 2913} 2914 2915 2916 2917int 2918ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 2919 const MachineInstr *DefMI, unsigned DefIdx, 2920 const MachineInstr *UseMI, 2921 unsigned UseIdx) const { 2922 // No operand latency. The caller may fall back to getInstrLatency. 2923 if (!ItinData || ItinData->isEmpty()) 2924 return -1; 2925 2926 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 2927 unsigned Reg = DefMO.getReg(); 2928 const MCInstrDesc *DefMCID = &DefMI->getDesc(); 2929 const MCInstrDesc *UseMCID = &UseMI->getDesc(); 2930 2931 unsigned DefAdj = 0; 2932 if (DefMI->isBundle()) { 2933 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 2934 DefMCID = &DefMI->getDesc(); 2935 } 2936 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 2937 DefMI->isRegSequence() || DefMI->isImplicitDef()) { 2938 return 1; 2939 } 2940 2941 unsigned UseAdj = 0; 2942 if (UseMI->isBundle()) { 2943 unsigned NewUseIdx; 2944 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 2945 Reg, NewUseIdx, UseAdj); 2946 if (!NewUseMI) 2947 return -1; 2948 2949 UseMI = NewUseMI; 2950 UseIdx = NewUseIdx; 2951 UseMCID = &UseMI->getDesc(); 2952 } 2953 2954 if (Reg == ARM::CPSR) { 2955 if (DefMI->getOpcode() == ARM::FMSTAT) { 2956 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 2957 return Subtarget.isCortexA9() ? 1 : 20; 2958 } 2959 2960 // CPSR set and branch can be paired in the same cycle. 2961 if (UseMI->isBranch()) 2962 return 0; 2963 2964 // Otherwise it takes the instruction latency (generally one). 2965 unsigned Latency = getInstrLatency(ItinData, DefMI); 2966 2967 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 2968 // its uses. Instructions which are otherwise scheduled between them may 2969 // incur a code size penalty (not able to use the CPSR setting 16-bit 2970 // instructions). 2971 if (Latency > 0 && Subtarget.isThumb2()) { 2972 const MachineFunction *MF = DefMI->getParent()->getParent(); 2973 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2974 --Latency; 2975 } 2976 return Latency; 2977 } 2978 2979 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) 2980 return -1; 2981 2982 unsigned DefAlign = DefMI->hasOneMemOperand() 2983 ? (*DefMI->memoperands_begin())->getAlignment() : 0; 2984 unsigned UseAlign = UseMI->hasOneMemOperand() 2985 ? (*UseMI->memoperands_begin())->getAlignment() : 0; 2986 2987 // Get the itinerary's latency if possible, and handle variable_ops. 2988 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 2989 *UseMCID, UseIdx, UseAlign); 2990 // Unable to find operand latency. The caller may resort to getInstrLatency. 2991 if (Latency < 0) 2992 return Latency; 2993 2994 // Adjust for IT block position. 2995 int Adj = DefAdj + UseAdj; 2996 2997 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 2998 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); 2999 if (Adj >= 0 || (int)Latency > -Adj) { 3000 return Latency + Adj; 3001 } 3002 // Return the itinerary latency, which may be zero but not less than zero. 3003 return Latency; 3004} 3005 3006int 3007ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3008 SDNode *DefNode, unsigned DefIdx, 3009 SDNode *UseNode, unsigned UseIdx) const { 3010 if (!DefNode->isMachineOpcode()) 3011 return 1; 3012 3013 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 3014 3015 if (isZeroCost(DefMCID.Opcode)) 3016 return 0; 3017 3018 if (!ItinData || ItinData->isEmpty()) 3019 return DefMCID.mayLoad() ? 3 : 1; 3020 3021 if (!UseNode->isMachineOpcode()) { 3022 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 3023 if (Subtarget.isCortexA9()) 3024 return Latency <= 2 ? 1 : Latency - 1; 3025 else 3026 return Latency <= 3 ? 1 : Latency - 2; 3027 } 3028 3029 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 3030 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 3031 unsigned DefAlign = !DefMN->memoperands_empty() 3032 ? (*DefMN->memoperands_begin())->getAlignment() : 0; 3033 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 3034 unsigned UseAlign = !UseMN->memoperands_empty() 3035 ? (*UseMN->memoperands_begin())->getAlignment() : 0; 3036 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 3037 UseMCID, UseIdx, UseAlign); 3038 3039 if (Latency > 1 && 3040 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { 3041 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 3042 // variants are one cycle cheaper. 3043 switch (DefMCID.getOpcode()) { 3044 default: break; 3045 case ARM::LDRrs: 3046 case ARM::LDRBrs: { 3047 unsigned ShOpVal = 3048 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3049 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3050 if (ShImm == 0 || 3051 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3052 --Latency; 3053 break; 3054 } 3055 case ARM::t2LDRs: 3056 case ARM::t2LDRBs: 3057 case ARM::t2LDRHs: 3058 case ARM::t2LDRSHs: { 3059 // Thumb2 mode: lsl only. 3060 unsigned ShAmt = 3061 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3062 if (ShAmt == 0 || ShAmt == 2) 3063 --Latency; 3064 break; 3065 } 3066 } 3067 } 3068 3069 if (DefAlign < 8 && Subtarget.isCortexA9()) 3070 switch (DefMCID.getOpcode()) { 3071 default: break; 3072 case ARM::VLD1q8: 3073 case ARM::VLD1q16: 3074 case ARM::VLD1q32: 3075 case ARM::VLD1q64: 3076 case ARM::VLD1q8wb_register: 3077 case ARM::VLD1q16wb_register: 3078 case ARM::VLD1q32wb_register: 3079 case ARM::VLD1q64wb_register: 3080 case ARM::VLD1q8wb_fixed: 3081 case ARM::VLD1q16wb_fixed: 3082 case ARM::VLD1q32wb_fixed: 3083 case ARM::VLD1q64wb_fixed: 3084 case ARM::VLD2d8: 3085 case ARM::VLD2d16: 3086 case ARM::VLD2d32: 3087 case ARM::VLD2q8Pseudo: 3088 case ARM::VLD2q16Pseudo: 3089 case ARM::VLD2q32Pseudo: 3090 case ARM::VLD2d8wb_fixed: 3091 case ARM::VLD2d16wb_fixed: 3092 case ARM::VLD2d32wb_fixed: 3093 case ARM::VLD2q8PseudoWB_fixed: 3094 case ARM::VLD2q16PseudoWB_fixed: 3095 case ARM::VLD2q32PseudoWB_fixed: 3096 case ARM::VLD2d8wb_register: 3097 case ARM::VLD2d16wb_register: 3098 case ARM::VLD2d32wb_register: 3099 case ARM::VLD2q8PseudoWB_register: 3100 case ARM::VLD2q16PseudoWB_register: 3101 case ARM::VLD2q32PseudoWB_register: 3102 case ARM::VLD3d8Pseudo: 3103 case ARM::VLD3d16Pseudo: 3104 case ARM::VLD3d32Pseudo: 3105 case ARM::VLD1d64TPseudo: 3106 case ARM::VLD3d8Pseudo_UPD: 3107 case ARM::VLD3d16Pseudo_UPD: 3108 case ARM::VLD3d32Pseudo_UPD: 3109 case ARM::VLD3q8Pseudo_UPD: 3110 case ARM::VLD3q16Pseudo_UPD: 3111 case ARM::VLD3q32Pseudo_UPD: 3112 case ARM::VLD3q8oddPseudo: 3113 case ARM::VLD3q16oddPseudo: 3114 case ARM::VLD3q32oddPseudo: 3115 case ARM::VLD3q8oddPseudo_UPD: 3116 case ARM::VLD3q16oddPseudo_UPD: 3117 case ARM::VLD3q32oddPseudo_UPD: 3118 case ARM::VLD4d8Pseudo: 3119 case ARM::VLD4d16Pseudo: 3120 case ARM::VLD4d32Pseudo: 3121 case ARM::VLD1d64QPseudo: 3122 case ARM::VLD4d8Pseudo_UPD: 3123 case ARM::VLD4d16Pseudo_UPD: 3124 case ARM::VLD4d32Pseudo_UPD: 3125 case ARM::VLD4q8Pseudo_UPD: 3126 case ARM::VLD4q16Pseudo_UPD: 3127 case ARM::VLD4q32Pseudo_UPD: 3128 case ARM::VLD4q8oddPseudo: 3129 case ARM::VLD4q16oddPseudo: 3130 case ARM::VLD4q32oddPseudo: 3131 case ARM::VLD4q8oddPseudo_UPD: 3132 case ARM::VLD4q16oddPseudo_UPD: 3133 case ARM::VLD4q32oddPseudo_UPD: 3134 case ARM::VLD1DUPq8: 3135 case ARM::VLD1DUPq16: 3136 case ARM::VLD1DUPq32: 3137 case ARM::VLD1DUPq8wb_fixed: 3138 case ARM::VLD1DUPq16wb_fixed: 3139 case ARM::VLD1DUPq32wb_fixed: 3140 case ARM::VLD1DUPq8wb_register: 3141 case ARM::VLD1DUPq16wb_register: 3142 case ARM::VLD1DUPq32wb_register: 3143 case ARM::VLD2DUPd8: 3144 case ARM::VLD2DUPd16: 3145 case ARM::VLD2DUPd32: 3146 case ARM::VLD2DUPd8wb_fixed: 3147 case ARM::VLD2DUPd16wb_fixed: 3148 case ARM::VLD2DUPd32wb_fixed: 3149 case ARM::VLD2DUPd8wb_register: 3150 case ARM::VLD2DUPd16wb_register: 3151 case ARM::VLD2DUPd32wb_register: 3152 case ARM::VLD4DUPd8Pseudo: 3153 case ARM::VLD4DUPd16Pseudo: 3154 case ARM::VLD4DUPd32Pseudo: 3155 case ARM::VLD4DUPd8Pseudo_UPD: 3156 case ARM::VLD4DUPd16Pseudo_UPD: 3157 case ARM::VLD4DUPd32Pseudo_UPD: 3158 case ARM::VLD1LNq8Pseudo: 3159 case ARM::VLD1LNq16Pseudo: 3160 case ARM::VLD1LNq32Pseudo: 3161 case ARM::VLD1LNq8Pseudo_UPD: 3162 case ARM::VLD1LNq16Pseudo_UPD: 3163 case ARM::VLD1LNq32Pseudo_UPD: 3164 case ARM::VLD2LNd8Pseudo: 3165 case ARM::VLD2LNd16Pseudo: 3166 case ARM::VLD2LNd32Pseudo: 3167 case ARM::VLD2LNq16Pseudo: 3168 case ARM::VLD2LNq32Pseudo: 3169 case ARM::VLD2LNd8Pseudo_UPD: 3170 case ARM::VLD2LNd16Pseudo_UPD: 3171 case ARM::VLD2LNd32Pseudo_UPD: 3172 case ARM::VLD2LNq16Pseudo_UPD: 3173 case ARM::VLD2LNq32Pseudo_UPD: 3174 case ARM::VLD4LNd8Pseudo: 3175 case ARM::VLD4LNd16Pseudo: 3176 case ARM::VLD4LNd32Pseudo: 3177 case ARM::VLD4LNq16Pseudo: 3178 case ARM::VLD4LNq32Pseudo: 3179 case ARM::VLD4LNd8Pseudo_UPD: 3180 case ARM::VLD4LNd16Pseudo_UPD: 3181 case ARM::VLD4LNd32Pseudo_UPD: 3182 case ARM::VLD4LNq16Pseudo_UPD: 3183 case ARM::VLD4LNq32Pseudo_UPD: 3184 // If the address is not 64-bit aligned, the latencies of these 3185 // instructions increases by one. 3186 ++Latency; 3187 break; 3188 } 3189 3190 return Latency; 3191} 3192 3193unsigned 3194ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData, 3195 const MachineInstr *DefMI, unsigned DefIdx, 3196 const MachineInstr *DepMI) const { 3197 unsigned Reg = DefMI->getOperand(DefIdx).getReg(); 3198 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI)) 3199 return 1; 3200 3201 // If the second MI is predicated, then there is an implicit use dependency. 3202 return getInstrLatency(ItinData, DefMI); 3203} 3204 3205unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3206 const MachineInstr *MI, 3207 unsigned *PredCost) const { 3208 if (MI->isCopyLike() || MI->isInsertSubreg() || 3209 MI->isRegSequence() || MI->isImplicitDef()) 3210 return 1; 3211 3212 // An instruction scheduler typically runs on unbundled instructions, however 3213 // other passes may query the latency of a bundled instruction. 3214 if (MI->isBundle()) { 3215 unsigned Latency = 0; 3216 MachineBasicBlock::const_instr_iterator I = MI; 3217 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3218 while (++I != E && I->isInsideBundle()) { 3219 if (I->getOpcode() != ARM::t2IT) 3220 Latency += getInstrLatency(ItinData, I, PredCost); 3221 } 3222 return Latency; 3223 } 3224 3225 const MCInstrDesc &MCID = MI->getDesc(); 3226 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { 3227 // When predicated, CPSR is an additional source operand for CPSR updating 3228 // instructions, this apparently increases their latencies. 3229 *PredCost = 1; 3230 } 3231 // Be sure to call getStageLatency for an empty itinerary in case it has a 3232 // valid MinLatency property. 3233 if (!ItinData) 3234 return MI->mayLoad() ? 3 : 1; 3235 3236 unsigned Class = MCID.getSchedClass(); 3237 3238 // For instructions with variable uops, use uops as latency. 3239 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) 3240 return getNumMicroOps(ItinData, MI); 3241 3242 // For the common case, fall back on the itinerary's latency. 3243 unsigned Latency = ItinData->getStageLatency(Class); 3244 3245 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 3246 unsigned DefAlign = MI->hasOneMemOperand() 3247 ? (*MI->memoperands_begin())->getAlignment() : 0; 3248 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign); 3249 if (Adj >= 0 || (int)Latency > -Adj) { 3250 return Latency + Adj; 3251 } 3252 return Latency; 3253} 3254 3255int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3256 SDNode *Node) const { 3257 if (!Node->isMachineOpcode()) 3258 return 1; 3259 3260 if (!ItinData || ItinData->isEmpty()) 3261 return 1; 3262 3263 unsigned Opcode = Node->getMachineOpcode(); 3264 switch (Opcode) { 3265 default: 3266 return ItinData->getStageLatency(get(Opcode).getSchedClass()); 3267 case ARM::VLDMQIA: 3268 case ARM::VSTMQIA: 3269 return 2; 3270 } 3271} 3272 3273bool ARMBaseInstrInfo:: 3274hasHighOperandLatency(const InstrItineraryData *ItinData, 3275 const MachineRegisterInfo *MRI, 3276 const MachineInstr *DefMI, unsigned DefIdx, 3277 const MachineInstr *UseMI, unsigned UseIdx) const { 3278 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3279 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 3280 if (Subtarget.isCortexA8() && 3281 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 3282 // CortexA8 VFP instructions are not pipelined. 3283 return true; 3284 3285 // Hoist VFP / NEON instructions with 4 or higher latency. 3286 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx, 3287 /*FindMin=*/false); 3288 if (Latency < 0) 3289 Latency = getInstrLatency(ItinData, DefMI); 3290 if (Latency <= 3) 3291 return false; 3292 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 3293 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 3294} 3295 3296bool ARMBaseInstrInfo:: 3297hasLowDefLatency(const InstrItineraryData *ItinData, 3298 const MachineInstr *DefMI, unsigned DefIdx) const { 3299 if (!ItinData || ItinData->isEmpty()) 3300 return false; 3301 3302 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3303 if (DDomain == ARMII::DomainGeneral) { 3304 unsigned DefClass = DefMI->getDesc().getSchedClass(); 3305 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3306 return (DefCycle != -1 && DefCycle <= 2); 3307 } 3308 return false; 3309} 3310 3311bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 3312 StringRef &ErrInfo) const { 3313 if (convertAddSubFlagsOpcode(MI->getOpcode())) { 3314 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 3315 return false; 3316 } 3317 return true; 3318} 3319 3320bool 3321ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 3322 unsigned &AddSubOpc, 3323 bool &NegAcc, bool &HasLane) const { 3324 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 3325 if (I == MLxEntryMap.end()) 3326 return false; 3327 3328 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 3329 MulOpc = Entry.MulOpc; 3330 AddSubOpc = Entry.AddSubOpc; 3331 NegAcc = Entry.NegAcc; 3332 HasLane = Entry.HasLane; 3333 return true; 3334} 3335 3336//===----------------------------------------------------------------------===// 3337// Execution domains. 3338//===----------------------------------------------------------------------===// 3339// 3340// Some instructions go down the NEON pipeline, some go down the VFP pipeline, 3341// and some can go down both. The vmov instructions go down the VFP pipeline, 3342// but they can be changed to vorr equivalents that are executed by the NEON 3343// pipeline. 3344// 3345// We use the following execution domain numbering: 3346// 3347enum ARMExeDomain { 3348 ExeGeneric = 0, 3349 ExeVFP = 1, 3350 ExeNEON = 2 3351}; 3352// 3353// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 3354// 3355std::pair<uint16_t, uint16_t> 3356ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 3357 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON 3358 // if they are not predicated. 3359 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 3360 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 3361 3362 // Cortex-A9 is particularly picky about mixing the two and wants these 3363 // converted. 3364 if (Subtarget.isCortexA9() && !isPredicated(MI) && 3365 (MI->getOpcode() == ARM::VMOVRS || 3366 MI->getOpcode() == ARM::VMOVSR)) 3367 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 3368 3369 // No other instructions can be swizzled, so just determine their domain. 3370 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 3371 3372 if (Domain & ARMII::DomainNEON) 3373 return std::make_pair(ExeNEON, 0); 3374 3375 // Certain instructions can go either way on Cortex-A8. 3376 // Treat them as NEON instructions. 3377 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 3378 return std::make_pair(ExeNEON, 0); 3379 3380 if (Domain & ARMII::DomainVFP) 3381 return std::make_pair(ExeVFP, 0); 3382 3383 return std::make_pair(ExeGeneric, 0); 3384} 3385 3386void 3387ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 3388 unsigned DstReg, SrcReg, DReg; 3389 unsigned Lane; 3390 MachineInstrBuilder MIB(MI); 3391 const TargetRegisterInfo *TRI = &getRegisterInfo(); 3392 bool isKill; 3393 switch (MI->getOpcode()) { 3394 default: 3395 llvm_unreachable("cannot handle opcode!"); 3396 break; 3397 case ARM::VMOVD: 3398 if (Domain != ExeNEON) 3399 break; 3400 3401 // Zap the predicate operands. 3402 assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 3403 MI->RemoveOperand(3); 3404 MI->RemoveOperand(2); 3405 3406 // Change to a VORRd which requires two identical use operands. 3407 MI->setDesc(get(ARM::VORRd)); 3408 3409 // Add the extra source operand and new predicates. 3410 // This will go before any implicit ops. 3411 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1))); 3412 break; 3413 case ARM::VMOVRS: 3414 if (Domain != ExeNEON) 3415 break; 3416 assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); 3417 3418 DstReg = MI->getOperand(0).getReg(); 3419 SrcReg = MI->getOperand(1).getReg(); 3420 3421 DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_0, &ARM::DPRRegClass); 3422 Lane = 0; 3423 if (DReg == ARM::NoRegister) { 3424 DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_1, &ARM::DPRRegClass); 3425 Lane = 1; 3426 assert(DReg && "S-register with no D super-register?"); 3427 } 3428 3429 MI->RemoveOperand(3); 3430 MI->RemoveOperand(2); 3431 MI->RemoveOperand(1); 3432 3433 MI->setDesc(get(ARM::VGETLNi32)); 3434 MIB.addReg(DReg); 3435 MIB.addImm(Lane); 3436 3437 MIB->getOperand(1).setIsUndef(); 3438 MIB.addReg(SrcReg, RegState::Implicit); 3439 3440 AddDefaultPred(MIB); 3441 break; 3442 case ARM::VMOVSR: 3443 if (Domain != ExeNEON) 3444 break; 3445 assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); 3446 3447 DstReg = MI->getOperand(0).getReg(); 3448 SrcReg = MI->getOperand(1).getReg(); 3449 DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_0, &ARM::DPRRegClass); 3450 Lane = 0; 3451 if (DReg == ARM::NoRegister) { 3452 DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_1, &ARM::DPRRegClass); 3453 Lane = 1; 3454 assert(DReg && "S-register with no D super-register?"); 3455 } 3456 isKill = MI->getOperand(0).isKill(); 3457 3458 MI->RemoveOperand(3); 3459 MI->RemoveOperand(2); 3460 MI->RemoveOperand(1); 3461 MI->RemoveOperand(0); 3462 3463 MI->setDesc(get(ARM::VSETLNi32)); 3464 MIB.addReg(DReg); 3465 MIB.addReg(DReg); 3466 MIB.addReg(SrcReg); 3467 MIB.addImm(Lane); 3468 3469 MIB->getOperand(1).setIsUndef(); 3470 3471 if (isKill) 3472 MIB->addRegisterKilled(DstReg, TRI, true); 3473 MIB->addRegisterDefined(DstReg, TRI); 3474 3475 AddDefaultPred(MIB); 3476 break; 3477 } 3478 3479} 3480 3481bool ARMBaseInstrInfo::hasNOP() const { 3482 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 3483} 3484