ARMISelLowering.h revision 6aa7197fb5aa478a5c813d41a11689bb6d8f7abc 
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
18#include "ARMSubtarget.h"
19#include "llvm/Target/TargetLowering.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include <vector>
23
24namespace llvm {
25  class ARMConstantPoolValue;
26
27  namespace ARMISD {
28    // ARM Specific DAG Nodes
29    enum NodeType {
30      // Start the numbering where the builtin ops and target ops leave off.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
34                    // TargetExternalSymbol, and TargetGlobalAddress.
35      WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
36
37      CALL,         // Function call.
38      CALL_PRED,    // Function call that's predicable.
39      CALL_NOLINK,  // Function call with branch not branch-and-link.
40      tCALL,        // Thumb function call.
41      BRCOND,       // Conditional branch.
42      BR_JT,        // Jumptable branch.
43      RET_FLAG,     // Return with a flag operand.
44
45      PIC_ADD,      // Add with a PC operand and a PIC label.
46
47      CMP,          // ARM compare instructions.
48      CMPNZ,        // ARM compare that uses only N or Z flags.
49      CMPFP,        // ARM VFP compare instruction, sets FPSCR.
50      CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
51      FMSTAT,       // ARM fmstat instruction.
52      CMOV,         // ARM conditional move instructions.
53      CNEG,         // ARM conditional negate instructions.
54
55      FTOSI,        // FP to sint within a FP register.
56      FTOUI,        // FP to uint within a FP register.
57      SITOF,        // sint to FP within a FP register.
58      UITOF,        // uint to FP within a FP register.
59
60      SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
61      SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
62      RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
63
64      FMRRD,        // double to two gprs.
65      FMDRR,         // Two gprs to double.
66
67      BUILTIN_SETJMP,   // exception handling setjmp
68      BUILTIN_LONGJMP,  // exception handling longjmp
69
70      THREAD_POINTER
71    };
72  }
73
74  //===----------------------------------------------------------------------===//
75  //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
76
77  class ARMTargetLowering : public TargetLowering {
78    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
79  public:
80    explicit ARMTargetLowering(TargetMachine &TM);
81
82    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
83
84    /// ReplaceNodeResults - Replace the results of node with an illegal result
85    /// type with new values built out of custom code.
86    ///
87    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
88                                    SelectionDAG &DAG);
89
90    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91
92    virtual const char *getTargetNodeName(unsigned Opcode) const;
93
94    virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
95                                                  MachineBasicBlock *MBB) const;
96
97    /// isLegalAddressingMode - Return true if the addressing mode represented
98    /// by AM is legal for this target, for a load/store of the specified type.
99    virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
100
101    /// getPreIndexedAddressParts - returns true by value, base pointer and
102    /// offset pointer and addressing mode by reference if the node's address
103    /// can be legally represented as pre-indexed load / store address.
104    virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
105                                           SDValue &Offset,
106                                           ISD::MemIndexedMode &AM,
107                                           SelectionDAG &DAG) const;
108
109    /// getPostIndexedAddressParts - returns true by value, base pointer and
110    /// offset pointer and addressing mode by reference if this node can be
111    /// combined with a load / store to form a post-indexed load / store.
112    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
113                                            SDValue &Base, SDValue &Offset,
114                                            ISD::MemIndexedMode &AM,
115                                            SelectionDAG &DAG) const;
116
117    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
118                                                const APInt &Mask,
119                                                APInt &KnownZero,
120                                                APInt &KnownOne,
121                                                const SelectionDAG &DAG,
122                                                unsigned Depth) const;
123    ConstraintType getConstraintType(const std::string &Constraint) const;
124    std::pair<unsigned, const TargetRegisterClass*>
125      getRegForInlineAsmConstraint(const std::string &Constraint,
126                                   MVT VT) const;
127    std::vector<unsigned>
128    getRegClassForInlineAsmConstraint(const std::string &Constraint,
129                                      MVT VT) const;
130
131    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
132    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
133    /// true it means one of the asm constraint of the inline asm instruction
134    /// being processed is 'm'.
135    virtual void LowerAsmOperandForConstraint(SDValue Op,
136                                              char ConstraintLetter,
137                                              bool hasMemory,
138                                              std::vector<SDValue> &Ops,
139                                              SelectionDAG &DAG) const;
140
141    virtual const ARMSubtarget* getSubtarget() {
142      return Subtarget;
143    }
144
145  private:
146    /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
147    /// make the right decision when generating code for different targets.
148    const ARMSubtarget *Subtarget;
149
150    /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
151    ///
152    unsigned ARMPCLabelIndex;
153
154    SDValue LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
155                             const SDValue &StackPtr, const CCValAssign &VA,
156                             SDValue Chain, SDValue Arg, ISD::ArgFlagsTy Flags);
157    SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
158                            unsigned CallingConv, SelectionDAG &DAG);
159    SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
160    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
161    SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
162    SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
163    SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
164    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
165    SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
166                                            SelectionDAG &DAG);
167    SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
168                                   SelectionDAG &DAG);
169    SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
170    SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
171    SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
172    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
173
174    SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
175                                      SDValue Chain,
176                                      SDValue Dst, SDValue Src,
177                                      SDValue Size, unsigned Align,
178                                      bool AlwaysInline,
179                                      const Value *DstSV, uint64_t DstSVOff,
180                                      const Value *SrcSV, uint64_t SrcSVOff);
181  };
182}
183
184#endif  // ARMISELLOWERING_H
185