1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 16#define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 17 18#include "MCTargetDesc/MipsABIInfo.h" 19#include "MCTargetDesc/MipsBaseInfo.h" 20#include "Mips.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/IR/Function.h" 24#include "llvm/Target/TargetLowering.h" 25#include <deque> 26#include <string> 27 28namespace llvm { 29 namespace MipsISD { 30 enum NodeType { 31 // Start the numbering from where ISD NodeType finishes. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 // Jump and link (call) 35 JmpLink, 36 37 // Tail call 38 TailCall, 39 40 // Get the Higher 16 bits from a 32-bit immediate 41 // No relation with Mips Hi register 42 Hi, 43 44 // Get the Lower 16 bits from a 32-bit immediate 45 // No relation with Mips Lo register 46 Lo, 47 48 // Handle gp_rel (small data/bss sections) relocation. 49 GPRel, 50 51 // Thread Pointer 52 ThreadPointer, 53 54 // Floating Point Branch Conditional 55 FPBrcond, 56 57 // Floating Point Compare 58 FPCmp, 59 60 // Floating Point Conditional Moves 61 CMovFP_T, 62 CMovFP_F, 63 64 // FP-to-int truncation node. 65 TruncIntFP, 66 67 // Return 68 Ret, 69 70 EH_RETURN, 71 72 // Node used to extract integer from accumulator. 73 MFHI, 74 MFLO, 75 76 // Node used to insert integers to accumulator. 77 MTLOHI, 78 79 // Mult nodes. 80 Mult, 81 Multu, 82 83 // MAdd/Sub nodes 84 MAdd, 85 MAddu, 86 MSub, 87 MSubu, 88 89 // DivRem(u) 90 DivRem, 91 DivRemU, 92 DivRem16, 93 DivRemU16, 94 95 BuildPairF64, 96 ExtractElementF64, 97 98 Wrapper, 99 100 DynAlloc, 101 102 Sync, 103 104 Ext, 105 Ins, 106 107 // EXTR.W instrinsic nodes. 108 EXTP, 109 EXTPDP, 110 EXTR_S_H, 111 EXTR_W, 112 EXTR_R_W, 113 EXTR_RS_W, 114 SHILO, 115 MTHLIP, 116 117 // DPA.W intrinsic nodes. 118 MULSAQ_S_W_PH, 119 MAQ_S_W_PHL, 120 MAQ_S_W_PHR, 121 MAQ_SA_W_PHL, 122 MAQ_SA_W_PHR, 123 DPAU_H_QBL, 124 DPAU_H_QBR, 125 DPSU_H_QBL, 126 DPSU_H_QBR, 127 DPAQ_S_W_PH, 128 DPSQ_S_W_PH, 129 DPAQ_SA_L_W, 130 DPSQ_SA_L_W, 131 DPA_W_PH, 132 DPS_W_PH, 133 DPAQX_S_W_PH, 134 DPAQX_SA_W_PH, 135 DPAX_W_PH, 136 DPSX_W_PH, 137 DPSQX_S_W_PH, 138 DPSQX_SA_W_PH, 139 MULSA_W_PH, 140 141 MULT, 142 MULTU, 143 MADD_DSP, 144 MADDU_DSP, 145 MSUB_DSP, 146 MSUBU_DSP, 147 148 // DSP shift nodes. 149 SHLL_DSP, 150 SHRA_DSP, 151 SHRL_DSP, 152 153 // DSP setcc and select_cc nodes. 154 SETCC_DSP, 155 SELECT_CC_DSP, 156 157 // Vector comparisons. 158 // These take a vector and return a boolean. 159 VALL_ZERO, 160 VANY_ZERO, 161 VALL_NONZERO, 162 VANY_NONZERO, 163 164 // These take a vector and return a vector bitmask. 165 VCEQ, 166 VCLE_S, 167 VCLE_U, 168 VCLT_S, 169 VCLT_U, 170 171 // Element-wise vector max/min. 172 VSMAX, 173 VSMIN, 174 VUMAX, 175 VUMIN, 176 177 // Vector Shuffle with mask as an operand 178 VSHF, // Generic shuffle 179 SHF, // 4-element set shuffle. 180 ILVEV, // Interleave even elements 181 ILVOD, // Interleave odd elements 182 ILVL, // Interleave left elements 183 ILVR, // Interleave right elements 184 PCKEV, // Pack even elements 185 PCKOD, // Pack odd elements 186 187 // Vector Lane Copy 188 INSVE, // Copy element from one vector to another 189 190 // Combined (XOR (OR $a, $b), -1) 191 VNOR, 192 193 // Extended vector element extraction 194 VEXTRACT_SEXT_ELT, 195 VEXTRACT_ZEXT_ELT, 196 197 // Load/Store Left/Right nodes. 198 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 199 LWR, 200 SWL, 201 SWR, 202 LDL, 203 LDR, 204 SDL, 205 SDR 206 }; 207 } 208 209 //===--------------------------------------------------------------------===// 210 // TargetLowering Implementation 211 //===--------------------------------------------------------------------===// 212 class MipsFunctionInfo; 213 class MipsSubtarget; 214 class MipsCCState; 215 216 class MipsTargetLowering : public TargetLowering { 217 bool isMicroMips; 218 public: 219 explicit MipsTargetLowering(const MipsTargetMachine &TM, 220 const MipsSubtarget &STI); 221 222 static const MipsTargetLowering *create(const MipsTargetMachine &TM, 223 const MipsSubtarget &STI); 224 225 /// createFastISel - This method returns a target specific FastISel object, 226 /// or null if the target does not support "fast" ISel. 227 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 228 const TargetLibraryInfo *libInfo) const override; 229 230 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 231 232 void LowerOperationWrapper(SDNode *N, 233 SmallVectorImpl<SDValue> &Results, 234 SelectionDAG &DAG) const override; 235 236 /// LowerOperation - Provide custom lowering hooks for some operations. 237 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 238 239 /// ReplaceNodeResults - Replace the results of node with an illegal result 240 /// type with new values built out of custom code. 241 /// 242 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 243 SelectionDAG &DAG) const override; 244 245 /// getTargetNodeName - This method returns the name of a target specific 246 // DAG node. 247 const char *getTargetNodeName(unsigned Opcode) const override; 248 249 /// getSetCCResultType - get the ISD::SETCC result ValueType 250 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 251 252 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 253 254 MachineBasicBlock * 255 EmitInstrWithCustomInserter(MachineInstr *MI, 256 MachineBasicBlock *MBB) const override; 257 258 struct LTStr { 259 bool operator()(const char *S1, const char *S2) const { 260 return strcmp(S1, S2) < 0; 261 } 262 }; 263 264 void HandleByVal(CCState *, unsigned &, unsigned) const override; 265 266 unsigned getRegisterByName(const char* RegName, EVT VT) const override; 267 268 protected: 269 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 270 271 // This method creates the following nodes, which are necessary for 272 // computing a local symbol's address: 273 // 274 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 275 template <class NodeTy> 276 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, 277 bool IsN32OrN64) const { 278 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 279 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 280 getTargetNode(N, Ty, DAG, GOTFlag)); 281 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 282 MachinePointerInfo::getGOT(), false, false, 283 false, 0); 284 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 285 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 286 getTargetNode(N, Ty, DAG, LoFlag)); 287 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 288 } 289 290 // This method creates the following nodes, which are necessary for 291 // computing a global symbol's address: 292 // 293 // (load (wrapper $gp, %got(sym))) 294 template <class NodeTy> 295 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, 296 unsigned Flag, SDValue Chain, 297 const MachinePointerInfo &PtrInfo) const { 298 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 299 getTargetNode(N, Ty, DAG, Flag)); 300 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0); 301 } 302 303 // This method creates the following nodes, which are necessary for 304 // computing a global symbol's address in large-GOT mode: 305 // 306 // (load (wrapper (add %hi(sym), $gp), %lo(sym))) 307 template <class NodeTy> 308 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty, 309 SelectionDAG &DAG, unsigned HiFlag, 310 unsigned LoFlag, SDValue Chain, 311 const MachinePointerInfo &PtrInfo) const { 312 SDValue Hi = 313 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag)); 314 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 315 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 316 getTargetNode(N, Ty, DAG, LoFlag)); 317 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false, 318 0); 319 } 320 321 // This method creates the following nodes, which are necessary for 322 // computing a symbol's address in non-PIC mode: 323 // 324 // (add %hi(sym), %lo(sym)) 325 template <class NodeTy> 326 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, 327 SelectionDAG &DAG) const { 328 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 329 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 330 return DAG.getNode(ISD::ADD, DL, Ty, 331 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 332 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 333 } 334 335 // This method creates the following nodes, which are necessary for 336 // computing a symbol's address using gp-relative addressing: 337 // 338 // (add $gp, %gp_rel(sym)) 339 template <class NodeTy> 340 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const { 341 assert(Ty == MVT::i32); 342 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL); 343 return DAG.getNode(ISD::ADD, DL, Ty, 344 DAG.getRegister(Mips::GP, Ty), 345 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), 346 GPRel)); 347 } 348 349 /// This function fills Ops, which is the list of operands that will later 350 /// be used when a function call node is created. It also generates 351 /// copyToReg nodes to set up argument registers. 352 virtual void 353 getOpndList(SmallVectorImpl<SDValue> &Ops, 354 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 355 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 356 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 357 SDValue Chain) const; 358 359 protected: 360 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 361 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 362 363 // Subtarget Info 364 const MipsSubtarget &Subtarget; 365 // Cache the ABI from the TargetMachine, we use it everywhere. 366 const MipsABIInfo &ABI; 367 368 private: 369 // Create a TargetGlobalAddress node. 370 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 371 unsigned Flag) const; 372 373 // Create a TargetExternalSymbol node. 374 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 375 unsigned Flag) const; 376 377 // Create a TargetBlockAddress node. 378 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 379 unsigned Flag) const; 380 381 // Create a TargetJumpTable node. 382 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 383 unsigned Flag) const; 384 385 // Create a TargetConstantPool node. 386 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 387 unsigned Flag) const; 388 389 // Lower Operand helpers 390 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 391 CallingConv::ID CallConv, bool isVarArg, 392 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, 393 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 394 TargetLowering::CallLoweringInfo &CLI) const; 395 396 // Lower Operand specifics 397 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 398 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 399 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 400 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 401 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 402 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 403 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 404 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 405 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 406 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 407 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 408 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; 409 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 410 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 411 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 412 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 413 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 414 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 415 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 416 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 417 bool IsSRA) const; 418 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 419 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 420 421 /// isEligibleForTailCallOptimization - Check whether the call is eligible 422 /// for tail call optimization. 423 virtual bool 424 isEligibleForTailCallOptimization(const CCState &CCInfo, 425 unsigned NextStackOffset, 426 const MipsFunctionInfo &FI) const = 0; 427 428 /// copyByValArg - Copy argument registers which were used to pass a byval 429 /// argument to the stack. Create a stack frame object for the byval 430 /// argument. 431 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 432 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 433 SmallVectorImpl<SDValue> &InVals, 434 const Argument *FuncArg, unsigned FirstReg, 435 unsigned LastReg, const CCValAssign &VA, 436 MipsCCState &State) const; 437 438 /// passByValArg - Pass a byval argument in registers or on stack. 439 void passByValArg(SDValue Chain, SDLoc DL, 440 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 441 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 442 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 443 unsigned FirstReg, unsigned LastReg, 444 const ISD::ArgFlagsTy &Flags, bool isLittle, 445 const CCValAssign &VA) const; 446 447 /// writeVarArgRegs - Write variable function arguments passed in registers 448 /// to the stack. Also create a stack frame object for the first variable 449 /// argument. 450 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, 451 SDLoc DL, SelectionDAG &DAG, CCState &State) const; 452 453 SDValue 454 LowerFormalArguments(SDValue Chain, 455 CallingConv::ID CallConv, bool isVarArg, 456 const SmallVectorImpl<ISD::InputArg> &Ins, 457 SDLoc dl, SelectionDAG &DAG, 458 SmallVectorImpl<SDValue> &InVals) const override; 459 460 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 461 SDValue Arg, SDLoc DL, bool IsTailCall, 462 SelectionDAG &DAG) const; 463 464 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 465 SmallVectorImpl<SDValue> &InVals) const override; 466 467 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 468 bool isVarArg, 469 const SmallVectorImpl<ISD::OutputArg> &Outs, 470 LLVMContext &Context) const override; 471 472 SDValue LowerReturn(SDValue Chain, 473 CallingConv::ID CallConv, bool isVarArg, 474 const SmallVectorImpl<ISD::OutputArg> &Outs, 475 const SmallVectorImpl<SDValue> &OutVals, 476 SDLoc dl, SelectionDAG &DAG) const override; 477 478 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 479 480 // Inline asm support 481 ConstraintType 482 getConstraintType(const std::string &Constraint) const override; 483 484 /// Examine constraint string and operand type and determine a weight value. 485 /// The operand object must already have been set up with the operand type. 486 ConstraintWeight getSingleConstraintMatchWeight( 487 AsmOperandInfo &info, const char *constraint) const override; 488 489 /// This function parses registers that appear in inline-asm constraints. 490 /// It returns pair (0, 0) on failure. 491 std::pair<unsigned, const TargetRegisterClass *> 492 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const; 493 494 std::pair<unsigned, const TargetRegisterClass *> 495 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 496 const std::string &Constraint, 497 MVT VT) const override; 498 499 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 500 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 501 /// true it means one of the asm constraint of the inline asm instruction 502 /// being processed is 'm'. 503 void LowerAsmOperandForConstraint(SDValue Op, 504 std::string &Constraint, 505 std::vector<SDValue> &Ops, 506 SelectionDAG &DAG) const override; 507 508 unsigned getInlineAsmMemConstraint( 509 const std::string &ConstraintCode) const override { 510 if (ConstraintCode == "R") 511 return InlineAsm::Constraint_R; 512 else if (ConstraintCode == "ZC") 513 return InlineAsm::Constraint_ZC; 514 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 515 } 516 517 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 518 519 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 520 521 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 522 unsigned SrcAlign, 523 bool IsMemset, bool ZeroMemset, 524 bool MemcpyStrSrc, 525 MachineFunction &MF) const override; 526 527 /// isFPImmLegal - Returns true if the target can instruction select the 528 /// specified FP immediate natively. If false, the legalizer will 529 /// materialize the FP immediate as a load from a constant pool. 530 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 531 532 unsigned getJumpTableEncoding() const override; 533 534 /// Emit a sign-extension using sll/sra, seb, or seh appropriately. 535 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI, 536 MachineBasicBlock *BB, 537 unsigned Size, unsigned DstReg, 538 unsigned SrcRec) const; 539 540 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 541 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 542 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 543 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 544 bool Nand = false) const; 545 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 546 MachineBasicBlock *BB, unsigned Size) const; 547 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 548 MachineBasicBlock *BB, unsigned Size) const; 549 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const; 550 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI, 551 MachineBasicBlock *BB, bool isFPCmp, 552 unsigned Opc) const; 553 }; 554 555 /// Create MipsTargetLowering objects. 556 const MipsTargetLowering * 557 createMips16TargetLowering(const MipsTargetMachine &TM, 558 const MipsSubtarget &STI); 559 const MipsTargetLowering * 560 createMipsSETargetLowering(const MipsTargetMachine &TM, 561 const MipsSubtarget &STI); 562 563 namespace Mips { 564 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 565 const TargetLibraryInfo *libInfo); 566 } 567} 568 569#endif 570