MipsInstrInfo.h revision 01a76ce8d910c0ffee89beaa3819d3448791950f
1//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef MIPSINSTRUCTIONINFO_H 15#define MIPSINSTRUCTIONINFO_H 16 17#include "Mips.h" 18#include "llvm/Support/ErrorHandling.h" 19#include "llvm/Target/TargetInstrInfo.h" 20#include "MipsRegisterInfo.h" 21 22namespace llvm { 23 24namespace Mips { 25 26 // Mips Branch Codes 27 enum FPBranchCode { 28 BRANCH_F, 29 BRANCH_T, 30 BRANCH_FL, 31 BRANCH_TL, 32 BRANCH_INVALID 33 }; 34 35 // Mips Condition Codes 36 enum CondCode { 37 // To be used with float branch True 38 FCOND_F, 39 FCOND_UN, 40 FCOND_EQ, 41 FCOND_UEQ, 42 FCOND_OLT, 43 FCOND_ULT, 44 FCOND_OLE, 45 FCOND_ULE, 46 FCOND_SF, 47 FCOND_NGLE, 48 FCOND_SEQ, 49 FCOND_NGL, 50 FCOND_LT, 51 FCOND_NGE, 52 FCOND_LE, 53 FCOND_NGT, 54 55 // To be used with float branch False 56 // This conditions have the same mnemonic as the 57 // above ones, but are used with a branch False; 58 FCOND_T, 59 FCOND_OR, 60 FCOND_NEQ, 61 FCOND_OGL, 62 FCOND_UGE, 63 FCOND_OGE, 64 FCOND_UGT, 65 FCOND_OGT, 66 FCOND_ST, 67 FCOND_GLE, 68 FCOND_SNE, 69 FCOND_GL, 70 FCOND_NLT, 71 FCOND_GE, 72 FCOND_NLE, 73 FCOND_GT, 74 75 // Only integer conditions 76 COND_E, 77 COND_GZ, 78 COND_GEZ, 79 COND_LZ, 80 COND_LEZ, 81 COND_NE, 82 COND_INVALID 83 }; 84 85 // Turn condition code into conditional branch opcode. 86 unsigned GetCondBranchFromCond(CondCode CC); 87 88 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 89 /// e.g. turning COND_E to COND_NE. 90 CondCode GetOppositeBranchCondition(Mips::CondCode CC); 91 92 /// MipsCCToString - Map each FP condition code to its string 93 inline static const char *MipsFCCToString(Mips::CondCode CC) 94 { 95 switch (CC) { 96 default: llvm_unreachable("Unknown condition code"); 97 case FCOND_F: 98 case FCOND_T: return "f"; 99 case FCOND_UN: 100 case FCOND_OR: return "un"; 101 case FCOND_EQ: 102 case FCOND_NEQ: return "eq"; 103 case FCOND_UEQ: 104 case FCOND_OGL: return "ueq"; 105 case FCOND_OLT: 106 case FCOND_UGE: return "olt"; 107 case FCOND_ULT: 108 case FCOND_OGE: return "ult"; 109 case FCOND_OLE: 110 case FCOND_UGT: return "ole"; 111 case FCOND_ULE: 112 case FCOND_OGT: return "ule"; 113 case FCOND_SF: 114 case FCOND_ST: return "sf"; 115 case FCOND_NGLE: 116 case FCOND_GLE: return "ngle"; 117 case FCOND_SEQ: 118 case FCOND_SNE: return "seq"; 119 case FCOND_NGL: 120 case FCOND_GL: return "ngl"; 121 case FCOND_LT: 122 case FCOND_NLT: return "lt"; 123 case FCOND_NGE: 124 case FCOND_GE: return "ge"; 125 case FCOND_LE: 126 case FCOND_NLE: return "nle"; 127 case FCOND_NGT: 128 case FCOND_GT: return "gt"; 129 } 130 } 131} 132 133/// MipsII - This namespace holds all of the target specific flags that 134/// instruction info tracks. 135/// 136namespace MipsII { 137 /// Target Operand Flag enum. 138 enum TOF { 139 //===------------------------------------------------------------------===// 140 // Mips Specific MachineOperand flags. 141 142 MO_NO_FLAG, 143 144 /// MO_GOT - Represents the offset into the global offset table at which 145 /// the address the relocation entry symbol resides during execution. 146 MO_GOT, 147 148 /// MO_GOT_CALL - Represents the offset into the global offset table at 149 /// which the address of a call site relocation entry symbol resides 150 /// during execution. This is different from the above since this flag 151 /// can only be present in call instructions. 152 MO_GOT_CALL, 153 154 /// MO_GPREL - Represents the offset from the current gp value to be used 155 /// for the relocatable object file being produced. 156 MO_GPREL, 157 158 /// MO_ABS_HILO - Represents the hi or low part of an absolute symbol 159 /// address. 160 MO_ABS_HILO 161 162 }; 163} 164 165class MipsInstrInfo : public TargetInstrInfoImpl { 166 MipsTargetMachine &TM; 167 const MipsRegisterInfo RI; 168public: 169 explicit MipsInstrInfo(MipsTargetMachine &TM); 170 171 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 172 /// such, whenever a client has an instance of instruction info, it should 173 /// always be able to get register info as well (through this method). 174 /// 175 virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; } 176 177 /// Return true if the instruction is a register to register move and return 178 /// the source and dest operands and their sub-register indices by reference. 179 virtual bool isMoveInstr(const MachineInstr &MI, 180 unsigned &SrcReg, unsigned &DstReg, 181 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 182 183 /// isLoadFromStackSlot - If the specified machine instruction is a direct 184 /// load from a stack slot, return the virtual or physical register number of 185 /// the destination along with the FrameIndex of the loaded stack slot. If 186 /// not, return 0. This predicate must return 0 if the instruction has 187 /// any side effects other than loading from the stack slot. 188 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 189 int &FrameIndex) const; 190 191 /// isStoreToStackSlot - If the specified machine instruction is a direct 192 /// store to a stack slot, return the virtual or physical register number of 193 /// the source reg along with the FrameIndex of the loaded stack slot. If 194 /// not, return 0. This predicate must return 0 if the instruction has 195 /// any side effects other than storing to the stack slot. 196 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 197 int &FrameIndex) const; 198 199 /// Branch Analysis 200 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 201 MachineBasicBlock *&FBB, 202 SmallVectorImpl<MachineOperand> &Cond, 203 bool AllowModify) const; 204 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 205 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 206 MachineBasicBlock *FBB, 207 const SmallVectorImpl<MachineOperand> &Cond) const; 208 virtual bool copyRegToReg(MachineBasicBlock &MBB, 209 MachineBasicBlock::iterator I, 210 unsigned DestReg, unsigned SrcReg, 211 const TargetRegisterClass *DestRC, 212 const TargetRegisterClass *SrcRC) const; 213 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 214 MachineBasicBlock::iterator MBBI, 215 unsigned SrcReg, bool isKill, int FrameIndex, 216 const TargetRegisterClass *RC) const; 217 218 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 219 MachineBasicBlock::iterator MBBI, 220 unsigned DestReg, int FrameIndex, 221 const TargetRegisterClass *RC) const; 222 223 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 224 MachineInstr* MI, 225 const SmallVectorImpl<unsigned> &Ops, 226 int FrameIndex) const; 227 228 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 229 MachineInstr* MI, 230 const SmallVectorImpl<unsigned> &Ops, 231 MachineInstr* LoadMI) const { 232 return 0; 233 } 234 235 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 236 virtual 237 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 238 239 /// Insert nop instruction when hazard condition is found 240 virtual void insertNoop(MachineBasicBlock &MBB, 241 MachineBasicBlock::iterator MI) const; 242 243 /// getGlobalBaseReg - Return a virtual register initialized with the 244 /// the global base register value. Output instructions required to 245 /// initialize the register in the function entry block, if necessary. 246 /// 247 unsigned getGlobalBaseReg(MachineFunction *MF) const; 248}; 249 250} 251 252#endif 253