1//===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8/// \file 9//===----------------------------------------------------------------------===// 10 11 12#include "SIMachineFunctionInfo.h" 13#include "AMDGPUSubtarget.h" 14#include "SIInstrInfo.h" 15#include "llvm/CodeGen/MachineInstrBuilder.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineRegisterInfo.h" 18#include "llvm/IR/Function.h" 19#include "llvm/IR/LLVMContext.h" 20 21#define MAX_LANES 64 22 23using namespace llvm; 24 25 26// Pin the vtable to this file. 27void SIMachineFunctionInfo::anchor() {} 28 29SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) 30 : AMDGPUMachineFunction(MF), 31 TIDReg(AMDGPU::NoRegister), 32 HasSpilledVGPRs(false), 33 PSInputAddr(0), 34 NumUserSGPRs(0), 35 LDSWaveSpillSize(0) { } 36 37SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg( 38 MachineFunction *MF, 39 unsigned FrameIndex, 40 unsigned SubIdx) { 41 const MachineFrameInfo *FrameInfo = MF->getFrameInfo(); 42 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( 43 MF->getSubtarget<AMDGPUSubtarget>().getRegisterInfo()); 44 MachineRegisterInfo &MRI = MF->getRegInfo(); 45 int64_t Offset = FrameInfo->getObjectOffset(FrameIndex); 46 Offset += SubIdx * 4; 47 48 unsigned LaneVGPRIdx = Offset / (64 * 4); 49 unsigned Lane = (Offset / 4) % 64; 50 51 struct SpilledReg Spill; 52 53 if (!LaneVGPRs.count(LaneVGPRIdx)) { 54 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass); 55 LaneVGPRs[LaneVGPRIdx] = LaneVGPR; 56 MRI.setPhysRegUsed(LaneVGPR); 57 58 // Add this register as live-in to all blocks to avoid machine verifer 59 // complaining about use of an undefined physical register. 60 for (MachineFunction::iterator BI = MF->begin(), BE = MF->end(); 61 BI != BE; ++BI) { 62 BI->addLiveIn(LaneVGPR); 63 } 64 } 65 66 Spill.VGPR = LaneVGPRs[LaneVGPRIdx]; 67 Spill.Lane = Lane; 68 return Spill; 69} 70 71unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize( 72 const MachineFunction &MF) const { 73 const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>(); 74 // FIXME: We should get this information from kernel attributes if it 75 // is available. 76 return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize(); 77} 78