1//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13#include "SparcTargetMachine.h" 14#include "SparcTargetObjectFile.h" 15#include "Sparc.h" 16#include "llvm/CodeGen/Passes.h" 17#include "llvm/IR/LegacyPassManager.h" 18#include "llvm/Support/TargetRegistry.h" 19using namespace llvm; 20 21extern "C" void LLVMInitializeSparcTarget() { 22 // Register the target. 23 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); 24 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); 25} 26 27static std::string computeDataLayout(bool is64Bit) { 28 // Sparc is big endian. 29 std::string Ret = "E-m:e"; 30 31 // Some ABIs have 32bit pointers. 32 if (!is64Bit) 33 Ret += "-p:32:32"; 34 35 // Alignments for 64 bit integers. 36 Ret += "-i64:64"; 37 38 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. 39 // On SparcV9 registers can hold 64 or 32 bits, on others only 32. 40 if (is64Bit) 41 Ret += "-n32:64"; 42 else 43 Ret += "-f128:64-n32"; 44 45 if (is64Bit) 46 Ret += "-S128"; 47 else 48 Ret += "-S64"; 49 50 return Ret; 51} 52 53/// SparcTargetMachine ctor - Create an ILP32 architecture model 54/// 55SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, 56 StringRef CPU, StringRef FS, 57 const TargetOptions &Options, 58 Reloc::Model RM, CodeModel::Model CM, 59 CodeGenOpt::Level OL, bool is64bit) 60 : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM, 61 CM, OL), 62 TLOF(make_unique<SparcELFTargetObjectFile>()), 63 Subtarget(TT, CPU, FS, *this, is64bit) { 64 initAsmInfo(); 65} 66 67SparcTargetMachine::~SparcTargetMachine() {} 68 69namespace { 70/// Sparc Code Generator Pass Configuration Options. 71class SparcPassConfig : public TargetPassConfig { 72public: 73 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) 74 : TargetPassConfig(TM, PM) {} 75 76 SparcTargetMachine &getSparcTargetMachine() const { 77 return getTM<SparcTargetMachine>(); 78 } 79 80 void addIRPasses() override; 81 bool addInstSelector() override; 82 void addPreEmitPass() override; 83}; 84} // namespace 85 86TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { 87 return new SparcPassConfig(this, PM); 88} 89 90void SparcPassConfig::addIRPasses() { 91 addPass(createAtomicExpandPass(&getSparcTargetMachine())); 92 93 TargetPassConfig::addIRPasses(); 94} 95 96bool SparcPassConfig::addInstSelector() { 97 addPass(createSparcISelDag(getSparcTargetMachine())); 98 return false; 99} 100 101void SparcPassConfig::addPreEmitPass(){ 102 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine())); 103} 104 105void SparcV8TargetMachine::anchor() { } 106 107SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, 108 StringRef TT, StringRef CPU, 109 StringRef FS, 110 const TargetOptions &Options, 111 Reloc::Model RM, 112 CodeModel::Model CM, 113 CodeGenOpt::Level OL) 114 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 115} 116 117void SparcV9TargetMachine::anchor() { } 118 119SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, 120 StringRef TT, StringRef CPU, 121 StringRef FS, 122 const TargetOptions &Options, 123 Reloc::Model RM, 124 CodeModel::Model CM, 125 CodeGenOpt::Level OL) 126 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 127} 128