RegisterInfoEmitter.cpp revision 2036835346ddf983d66b49505bd52db1d3f8b49d
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of a target 11// register file for a code generator. It uses instances of the Register, 12// RegisterAliases, and RegisterClass classes to gather this information. 13// 14//===----------------------------------------------------------------------===// 15 16#include "RegisterInfoEmitter.h" 17#include "CodeGenTarget.h" 18#include "CodeGenRegisters.h" 19#include "Record.h" 20#include "llvm/ADT/StringExtras.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/Support/Streams.h" 23#include <set> 24#include <algorithm> 25using namespace llvm; 26 27// runEnums - Print out enum values for all of the registers. 28void RegisterInfoEmitter::runEnums(std::ostream &OS) { 29 CodeGenTarget Target; 30 const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 31 32 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace"); 33 34 EmitSourceFileHeader("Target Register Enum Values", OS); 35 OS << "namespace llvm {\n\n"; 36 37 if (!Namespace.empty()) 38 OS << "namespace " << Namespace << " {\n"; 39 OS << " enum {\n NoRegister,\n"; 40 41 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 42 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n"; 43 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 44 OS << " };\n"; 45 if (!Namespace.empty()) 46 OS << "}\n"; 47 OS << "} // End llvm namespace \n"; 48} 49 50void RegisterInfoEmitter::runHeader(std::ostream &OS) { 51 EmitSourceFileHeader("Register Information Header Fragment", OS); 52 CodeGenTarget Target; 53 const std::string &TargetName = Target.getName(); 54 std::string ClassName = TargetName + "GenRegisterInfo"; 55 56 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; 57 OS << "#include <string>\n\n"; 58 59 OS << "namespace llvm {\n\n"; 60 61 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 62 << " explicit " << ClassName 63 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" 64 << " virtual int getDwarfRegNumFull(unsigned RegNum, " 65 << "unsigned Flavour) const;\n" 66 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" 67 << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 68 << " { return false; }\n" 69 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" 70 << "};\n\n"; 71 72 const std::vector<CodeGenRegisterClass> &RegisterClasses = 73 Target.getRegisterClasses(); 74 75 if (!RegisterClasses.empty()) { 76 OS << "namespace " << RegisterClasses[0].Namespace 77 << " { // Register classes\n"; 78 79 OS << " enum {\n"; 80 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 81 if (i) OS << ",\n"; 82 OS << " " << RegisterClasses[i].getName() << "RegClassID"; 83 OS << " = " << (i+1); 84 } 85 OS << "\n };\n\n"; 86 87 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 88 const std::string &Name = RegisterClasses[i].getName(); 89 90 // Output the register class definition. 91 OS << " struct " << Name << "Class : public TargetRegisterClass {\n" 92 << " " << Name << "Class();\n" 93 << RegisterClasses[i].MethodProtos << " };\n"; 94 95 // Output the extern for the instance. 96 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; 97 // Output the extern for the pointer to the instance (should remove). 98 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" 99 << Name << "RegClass;\n"; 100 } 101 OS << "} // end of namespace " << TargetName << "\n\n"; 102 } 103 OS << "} // End llvm namespace \n"; 104} 105 106bool isSubRegisterClass(const CodeGenRegisterClass &RC, 107 std::set<Record*> &RegSet) { 108 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 109 Record *Reg = RC.Elements[i]; 110 if (!RegSet.count(Reg)) 111 return false; 112 } 113 return true; 114} 115 116static void addSuperReg(Record *R, Record *S, 117 std::map<Record*, std::set<Record*> > &SubRegs, 118 std::map<Record*, std::set<Record*> > &SuperRegs, 119 std::map<Record*, std::set<Record*> > &Aliases) { 120 if (R == S) { 121 cerr << "Error: recursive sub-register relationship between" 122 << " register " << getQualifiedName(R) 123 << " and its sub-registers?\n"; 124 abort(); 125 } 126 if (!SuperRegs[R].insert(S).second) 127 return; 128 SubRegs[S].insert(R); 129 Aliases[R].insert(S); 130 Aliases[S].insert(R); 131 if (SuperRegs.count(S)) 132 for (std::set<Record*>::iterator I = SuperRegs[S].begin(), 133 E = SuperRegs[S].end(); I != E; ++I) 134 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases); 135} 136 137static void addSubSuperReg(Record *R, Record *S, 138 std::map<Record*, std::set<Record*> > &SubRegs, 139 std::map<Record*, std::set<Record*> > &SuperRegs, 140 std::map<Record*, std::set<Record*> > &Aliases) { 141 if (R == S) { 142 cerr << "Error: recursive sub-register relationship between" 143 << " register " << getQualifiedName(R) 144 << " and its sub-registers?\n"; 145 abort(); 146 } 147 148 if (!SubRegs[R].insert(S).second) 149 return; 150 addSuperReg(S, R, SubRegs, SuperRegs, Aliases); 151 Aliases[R].insert(S); 152 Aliases[S].insert(R); 153 if (SubRegs.count(S)) 154 for (std::set<Record*>::iterator I = SubRegs[S].begin(), 155 E = SubRegs[S].end(); I != E; ++I) 156 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); 157} 158 159class RegisterSorter { 160private: 161 std::map<Record*, std::set<Record*> > &RegisterSubRegs; 162 163public: 164 RegisterSorter(std::map<Record*, std::set<Record*> > &RS) 165 : RegisterSubRegs(RS) {}; 166 167 bool operator()(Record *RegA, Record *RegB) { 168 // B is sub-register of A. 169 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB); 170 } 171}; 172 173// RegisterInfoEmitter::run - Main register file description emitter. 174// 175void RegisterInfoEmitter::run(std::ostream &OS) { 176 CodeGenTarget Target; 177 EmitSourceFileHeader("Register Information Source Fragment", OS); 178 179 OS << "namespace llvm {\n\n"; 180 181 // Start out by emitting each of the register classes... to do this, we build 182 // a set of registers which belong to a register class, this is to ensure that 183 // each register is only in a single register class. 184 // 185 const std::vector<CodeGenRegisterClass> &RegisterClasses = 186 Target.getRegisterClasses(); 187 188 // Loop over all of the register classes... emitting each one. 189 OS << "namespace { // Register classes...\n"; 190 191 // RegClassesBelongedTo - Keep track of which register classes each reg 192 // belongs to. 193 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo; 194 195 // Emit the register enum value arrays for each RegisterClass 196 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 197 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 198 199 // Give the register class a legal C name if it's anonymous. 200 std::string Name = RC.TheDef->getName(); 201 202 // Emit the register list now. 203 OS << " // " << Name << " Register Class...\n" 204 << " static const unsigned " << Name 205 << "[] = {\n "; 206 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 207 Record *Reg = RC.Elements[i]; 208 OS << getQualifiedName(Reg) << ", "; 209 210 // Keep track of which regclasses this register is in. 211 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC)); 212 } 213 OS << "\n };\n\n"; 214 } 215 216 // Emit the ValueType arrays for each RegisterClass 217 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 218 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 219 220 // Give the register class a legal C name if it's anonymous. 221 std::string Name = RC.TheDef->getName() + "VTs"; 222 223 // Emit the register list now. 224 OS << " // " << Name 225 << " Register Class Value Types...\n" 226 << " static const MVT " << Name 227 << "[] = {\n "; 228 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) 229 OS << getEnumName(RC.VTs[i]) << ", "; 230 OS << "MVT::Other\n };\n\n"; 231 } 232 OS << "} // end anonymous namespace\n\n"; 233 234 // Now that all of the structs have been emitted, emit the instances. 235 if (!RegisterClasses.empty()) { 236 OS << "namespace " << RegisterClasses[0].Namespace 237 << " { // Register class instances\n"; 238 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 239 OS << " " << RegisterClasses[i].getName() << "Class\t" 240 << RegisterClasses[i].getName() << "RegClass;\n"; 241 242 std::map<unsigned, std::set<unsigned> > SuperClassMap; 243 std::map<unsigned, std::set<unsigned> > SuperRegClassMap; 244 OS << "\n"; 245 246 // Emit the sub-register classes for each RegisterClass 247 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 248 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 249 250 // Give the register class a legal C name if it's anonymous. 251 std::string Name = RC.TheDef->getName(); 252 253 OS << " // " << Name 254 << " Sub-register Classess...\n" 255 << " static const TargetRegisterClass* const " 256 << Name << "SubRegClasses [] = {\n "; 257 258 bool Empty = true; 259 260 for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size(); 261 subrc != subrcMax; ++subrc) { 262 unsigned rc2 = 0, e2 = RegisterClasses.size(); 263 for (; rc2 != e2; ++rc2) { 264 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 265 if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) { 266 if (!Empty) 267 OS << ", "; 268 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 269 Empty = false; 270 271 std::map<unsigned, std::set<unsigned> >::iterator SCMI = 272 SuperRegClassMap.find(rc2); 273 if (SCMI == SuperRegClassMap.end()) { 274 SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); 275 SCMI = SuperRegClassMap.find(rc2); 276 } 277 SCMI->second.insert(rc); 278 break; 279 } 280 } 281 if (rc2 == e2) 282 throw "Register Class member '" + 283 RC.SubRegClasses[subrc]->getName() + 284 "' is not a valid RegisterClass!"; 285 } 286 287 OS << (!Empty ? ", " : "") << "NULL"; 288 OS << "\n };\n\n"; 289 } 290 291 // Emit the super-register classes for each RegisterClass 292 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 293 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 294 295 // Give the register class a legal C name if it's anonymous. 296 std::string Name = RC.TheDef->getName(); 297 298 OS << " // " << Name 299 << " Super-register Classess...\n" 300 << " static const TargetRegisterClass* const " 301 << Name << "SuperRegClasses [] = {\n "; 302 303 bool Empty = true; 304 std::map<unsigned, std::set<unsigned> >::iterator I = 305 SuperRegClassMap.find(rc); 306 if (I != SuperRegClassMap.end()) { 307 for (std::set<unsigned>::iterator II = I->second.begin(), 308 EE = I->second.end(); II != EE; ++II) { 309 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 310 if (!Empty) 311 OS << ", "; 312 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 313 Empty = false; 314 } 315 } 316 317 OS << (!Empty ? ", " : "") << "NULL"; 318 OS << "\n };\n\n"; 319 } 320 321 // Emit the sub-classes array for each RegisterClass 322 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 323 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 324 325 // Give the register class a legal C name if it's anonymous. 326 std::string Name = RC.TheDef->getName(); 327 328 std::set<Record*> RegSet; 329 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 330 Record *Reg = RC.Elements[i]; 331 RegSet.insert(Reg); 332 } 333 334 OS << " // " << Name 335 << " Register Class sub-classes...\n" 336 << " static const TargetRegisterClass* const " 337 << Name << "Subclasses [] = {\n "; 338 339 bool Empty = true; 340 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 341 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 342 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() || 343 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet)) 344 continue; 345 346 if (!Empty) OS << ", "; 347 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 348 Empty = false; 349 350 std::map<unsigned, std::set<unsigned> >::iterator SCMI = 351 SuperClassMap.find(rc2); 352 if (SCMI == SuperClassMap.end()) { 353 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); 354 SCMI = SuperClassMap.find(rc2); 355 } 356 SCMI->second.insert(rc); 357 } 358 359 OS << (!Empty ? ", " : "") << "NULL"; 360 OS << "\n };\n\n"; 361 } 362 363 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 364 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 365 366 // Give the register class a legal C name if it's anonymous. 367 std::string Name = RC.TheDef->getName(); 368 369 OS << " // " << Name 370 << " Register Class super-classes...\n" 371 << " static const TargetRegisterClass* const " 372 << Name << "Superclasses [] = {\n "; 373 374 bool Empty = true; 375 std::map<unsigned, std::set<unsigned> >::iterator I = 376 SuperClassMap.find(rc); 377 if (I != SuperClassMap.end()) { 378 for (std::set<unsigned>::iterator II = I->second.begin(), 379 EE = I->second.end(); II != EE; ++II) { 380 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 381 if (!Empty) OS << ", "; 382 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 383 Empty = false; 384 } 385 } 386 387 OS << (!Empty ? ", " : "") << "NULL"; 388 OS << "\n };\n\n"; 389 } 390 391 392 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 393 const CodeGenRegisterClass &RC = RegisterClasses[i]; 394 OS << RC.MethodBodies << "\n"; 395 OS << RC.getName() << "Class::" << RC.getName() 396 << "Class() : TargetRegisterClass(" 397 << RC.getName() + "RegClassID" << ", " 398 << RC.getName() + "VTs" << ", " 399 << RC.getName() + "Subclasses" << ", " 400 << RC.getName() + "Superclasses" << ", " 401 << RC.getName() + "SubRegClasses" << ", " 402 << RC.getName() + "SuperRegClasses" << ", " 403 << RC.SpillSize/8 << ", " 404 << RC.SpillAlignment/8 << ", " 405 << RC.CopyCost << ", " 406 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() 407 << ") {}\n"; 408 } 409 410 OS << "}\n"; 411 } 412 413 OS << "\nnamespace {\n"; 414 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 415 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 416 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) 417 << "RegClass,\n"; 418 OS << " };\n"; 419 420 // Emit register sub-registers / super-registers, aliases... 421 std::map<Record*, std::set<Record*> > RegisterSubRegs; 422 std::map<Record*, std::set<Record*> > RegisterSuperRegs; 423 std::map<Record*, std::set<Record*> > RegisterAliases; 424 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors; 425 std::map<Record*, std::vector<int> > DwarfRegNums; 426 427 const std::vector<CodeGenRegister> &Regs = Target.getRegisters(); 428 429 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 430 Record *R = Regs[i].TheDef; 431 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases"); 432 // Add information that R aliases all of the elements in the list... and 433 // that everything in the list aliases R. 434 for (unsigned j = 0, e = LI.size(); j != e; ++j) { 435 Record *Reg = LI[j]; 436 if (RegisterAliases[R].count(Reg)) 437 cerr << "Warning: register alias between " << getQualifiedName(R) 438 << " and " << getQualifiedName(Reg) 439 << " specified multiple times!\n"; 440 RegisterAliases[R].insert(Reg); 441 442 if (RegisterAliases[Reg].count(R)) 443 cerr << "Warning: register alias between " << getQualifiedName(R) 444 << " and " << getQualifiedName(Reg) 445 << " specified multiple times!\n"; 446 RegisterAliases[Reg].insert(R); 447 } 448 } 449 450 // Process sub-register sets. 451 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 452 Record *R = Regs[i].TheDef; 453 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs"); 454 // Process sub-register set and add aliases information. 455 for (unsigned j = 0, e = LI.size(); j != e; ++j) { 456 Record *SubReg = LI[j]; 457 if (RegisterSubRegs[R].count(SubReg)) 458 cerr << "Warning: register " << getQualifiedName(SubReg) 459 << " specified as a sub-register of " << getQualifiedName(R) 460 << " multiple times!\n"; 461 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, 462 RegisterAliases); 463 } 464 } 465 466 if (!RegisterAliases.empty()) 467 OS << "\n\n // Register Alias Sets...\n"; 468 469 // Emit the empty alias list 470 OS << " const unsigned Empty_AliasSet[] = { 0 };\n"; 471 // Loop over all of the registers which have aliases, emitting the alias list 472 // to memory. 473 for (std::map<Record*, std::set<Record*> >::iterator 474 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { 475 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; 476 for (std::set<Record*>::iterator ASI = I->second.begin(), 477 E = I->second.end(); ASI != E; ++ASI) 478 OS << getQualifiedName(*ASI) << ", "; 479 OS << "0 };\n"; 480 } 481 482 if (!RegisterSubRegs.empty()) 483 OS << "\n\n // Register Sub-registers Sets...\n"; 484 485 // Emit the empty sub-registers list 486 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; 487 // Loop over all of the registers which have sub-registers, emitting the 488 // sub-registers list to memory. 489 for (std::map<Record*, std::set<Record*> >::iterator 490 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { 491 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; 492 std::vector<Record*> SubRegsVector; 493 for (std::set<Record*>::iterator ASI = I->second.begin(), 494 E = I->second.end(); ASI != E; ++ASI) 495 SubRegsVector.push_back(*ASI); 496 RegisterSorter RS(RegisterSubRegs); 497 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS); 498 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i) 499 OS << getQualifiedName(SubRegsVector[i]) << ", "; 500 OS << "0 };\n"; 501 } 502 503 if (!RegisterSuperRegs.empty()) 504 OS << "\n\n // Register Super-registers Sets...\n"; 505 506 // Emit the empty super-registers list 507 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; 508 // Loop over all of the registers which have super-registers, emitting the 509 // super-registers list to memory. 510 for (std::map<Record*, std::set<Record*> >::iterator 511 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { 512 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; 513 514 std::vector<Record*> SuperRegsVector; 515 for (std::set<Record*>::iterator ASI = I->second.begin(), 516 E = I->second.end(); ASI != E; ++ASI) 517 SuperRegsVector.push_back(*ASI); 518 RegisterSorter RS(RegisterSubRegs); 519 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS); 520 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i) 521 OS << getQualifiedName(SuperRegsVector[i]) << ", "; 522 OS << "0 };\n"; 523 } 524 525 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; 526 OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n"; 527 528 // Now that register alias and sub-registers sets have been emitted, emit the 529 // register descriptors now. 530 const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 531 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 532 const CodeGenRegister &Reg = Registers[i]; 533 OS << " { \""; 534 if (!Reg.TheDef->getValueAsString("AsmName").empty()) 535 OS << Reg.TheDef->getValueAsString("AsmName"); 536 else 537 OS << Reg.getName(); 538 OS << "\",\t\""; 539 if (!Reg.TheDef->getValueAsString("Name").empty()) { 540 OS << Reg.TheDef->getValueAsString("Name"); 541 } else { 542 // Default to "name". 543 if (!Reg.TheDef->getValueAsString("AsmName").empty()) 544 OS << Reg.TheDef->getValueAsString("AsmName"); 545 else 546 OS << Reg.getName(); 547 } 548 OS << "\",\t"; 549 if (RegisterAliases.count(Reg.TheDef)) 550 OS << Reg.getName() << "_AliasSet,\t"; 551 else 552 OS << "Empty_AliasSet,\t"; 553 if (RegisterSubRegs.count(Reg.TheDef)) 554 OS << Reg.getName() << "_SubRegsSet,\t"; 555 else 556 OS << "Empty_SubRegsSet,\t"; 557 if (RegisterSuperRegs.count(Reg.TheDef)) 558 OS << Reg.getName() << "_SuperRegsSet },\n"; 559 else 560 OS << "Empty_SuperRegsSet },\n"; 561 } 562 OS << " };\n"; // End of register descriptors... 563 OS << "}\n\n"; // End of anonymous namespace... 564 565 std::string ClassName = Target.getName() + "GenRegisterInfo"; 566 567 // Calculate the mapping of subregister+index pairs to physical registers. 568 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet"); 569 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) { 570 int subRegIndex = SubRegs[i]->getValueAsInt("index"); 571 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From"); 572 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To"); 573 574 if (From.size() != To.size()) { 575 cerr << "Error: register list and sub-register list not of equal length" 576 << " in SubRegSet\n"; 577 exit(1); 578 } 579 580 // For each entry in from/to vectors, insert the to register at index 581 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii) 582 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii])); 583 } 584 585 // Emit the subregister + index mapping function based on the information 586 // calculated above. 587 OS << "unsigned " << ClassName 588 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" 589 << " switch (RegNo) {\n" 590 << " default: abort(); break;\n"; 591 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator 592 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) { 593 OS << " case " << getQualifiedName(I->first) << ":\n"; 594 OS << " switch (Index) {\n"; 595 OS << " default: abort(); break;\n"; 596 for (unsigned i = 0, e = I->second.size(); i != e; ++i) 597 OS << " case " << (I->second)[i].first << ": return " 598 << getQualifiedName((I->second)[i].second) << ";\n"; 599 OS << " }; break;\n"; 600 } 601 OS << " };\n"; 602 OS << " return 0;\n"; 603 OS << "}\n\n"; 604 605 // Emit the constructor of the class... 606 OS << ClassName << "::" << ClassName 607 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" 608 << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 609 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " 610 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n"; 611 612 // Collect all information about dwarf register numbers 613 614 // First, just pull all provided information to the map 615 unsigned maxLength = 0; 616 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 617 Record *Reg = Registers[i].TheDef; 618 std::vector<int> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 619 maxLength = std::max((size_t)maxLength, RegNums.size()); 620 if (DwarfRegNums.count(Reg)) 621 cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg) 622 << "specified multiple times\n"; 623 DwarfRegNums[Reg] = RegNums; 624 } 625 626 // Now we know maximal length of number list. Append -1's, where needed 627 for (std::map<Record*, std::vector<int> >::iterator 628 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 629 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 630 I->second.push_back(-1); 631 632 // Emit information about the dwarf register numbers. 633 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, " 634 << "unsigned Flavour) const {\n" 635 << " switch (Flavour) {\n" 636 << " default:\n" 637 << " assert(0 && \"Unknown DWARF flavour\");\n" 638 << " return -1;\n"; 639 640 for (unsigned i = 0, e = maxLength; i != e; ++i) { 641 OS << " case " << i << ":\n" 642 << " switch (RegNum) {\n" 643 << " default:\n" 644 << " assert(0 && \"Invalid RegNum\");\n" 645 << " return -1;\n"; 646 647 for (std::map<Record*, std::vector<int> >::iterator 648 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 649 int RegNo = I->second[i]; 650 if (RegNo != -2) 651 OS << " case " << getQualifiedName(I->first) << ":\n" 652 << " return " << RegNo << ";\n"; 653 else 654 OS << " case " << getQualifiedName(I->first) << ":\n" 655 << " assert(0 && \"Invalid register for this mode\");\n" 656 << " return -1;\n"; 657 } 658 OS << " };\n"; 659 } 660 661 OS << " };\n}\n\n"; 662 663 OS << "} // End llvm namespace \n"; 664} 665