RegisterInfoEmitter.cpp revision 9b1b25f0631b22cd09c2fa7383ce28721fa3e212 
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of a target
11// register file for a code generator.  It uses instances of the Register,
12// RegisterAliases, and RegisterClass classes to gather this information.
13//
14//===----------------------------------------------------------------------===//
15
16#include "RegisterInfoEmitter.h"
17#include "CodeGenTarget.h"
18#include "CodeGenRegisters.h"
19#include "SequenceToOffsetTable.h"
20#include "llvm/TableGen/Record.h"
21#include "llvm/ADT/BitVector.h"
22#include "llvm/ADT/StringExtras.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/Support/Format.h"
25#include <algorithm>
26#include <set>
27using namespace llvm;
28
29// runEnums - Print out enum values for all of the registers.
30void
31RegisterInfoEmitter::runEnums(raw_ostream &OS,
32                              CodeGenTarget &Target, CodeGenRegBank &Bank) {
33  const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
34
35  // Register enums are stored as uint16_t in the tables. Make sure we'll fit
36  assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
37
38  std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
39
40  EmitSourceFileHeader("Target Register Enum Values", OS);
41
42  OS << "\n#ifdef GET_REGINFO_ENUM\n";
43  OS << "#undef GET_REGINFO_ENUM\n";
44
45  OS << "namespace llvm {\n\n";
46
47  OS << "class MCRegisterClass;\n"
48     << "extern const MCRegisterClass " << Namespace
49     << "MCRegisterClasses[];\n\n";
50
51  if (!Namespace.empty())
52    OS << "namespace " << Namespace << " {\n";
53  OS << "enum {\n  NoRegister,\n";
54
55  for (unsigned i = 0, e = Registers.size(); i != e; ++i)
56    OS << "  " << Registers[i]->getName() << " = " <<
57      Registers[i]->EnumValue << ",\n";
58  assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
59         "Register enum value mismatch!");
60  OS << "  NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
61  OS << "};\n";
62  if (!Namespace.empty())
63    OS << "}\n";
64
65  ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
66  if (!RegisterClasses.empty()) {
67
68    // RegisterClass enums are stored as uint16_t in the tables.
69    assert(RegisterClasses.size() <= 0xffff &&
70           "Too many register classes to fit in tables");
71
72    OS << "\n// Register classes\n";
73    if (!Namespace.empty())
74      OS << "namespace " << Namespace << " {\n";
75    OS << "enum {\n";
76    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
77      if (i) OS << ",\n";
78      OS << "  " << RegisterClasses[i]->getName() << "RegClassID";
79      OS << " = " << i;
80    }
81    OS << "\n  };\n";
82    if (!Namespace.empty())
83      OS << "}\n";
84  }
85
86  const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
87  // If the only definition is the default NoRegAltName, we don't need to
88  // emit anything.
89  if (RegAltNameIndices.size() > 1) {
90    OS << "\n// Register alternate name indices\n";
91    if (!Namespace.empty())
92      OS << "namespace " << Namespace << " {\n";
93    OS << "enum {\n";
94    for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
95      OS << "  " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
96    OS << "  NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
97    OS << "};\n";
98    if (!Namespace.empty())
99      OS << "}\n";
100  }
101
102  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
103  if (!SubRegIndices.empty()) {
104    OS << "\n// Subregister indices\n";
105    std::string Namespace =
106      SubRegIndices[0]->getNamespace();
107    if (!Namespace.empty())
108      OS << "namespace " << Namespace << " {\n";
109    OS << "enum {\n  NoSubRegister,\n";
110    for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
111      OS << "  " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
112    OS << "  NUM_TARGET_NAMED_SUBREGS\n};\n";
113    if (!Namespace.empty())
114      OS << "}\n";
115  }
116
117  OS << "} // End llvm namespace \n";
118  OS << "#endif // GET_REGINFO_ENUM\n\n";
119}
120
121
122void
123RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
124                                       const std::vector<CodeGenRegister*> &Regs,
125                                          bool isCtor) {
126  // Collect all information about dwarf register numbers
127  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
128  DwarfRegNumsMapTy DwarfRegNums;
129
130  // First, just pull all provided information to the map
131  unsigned maxLength = 0;
132  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
133    Record *Reg = Regs[i]->TheDef;
134    std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
135    maxLength = std::max((size_t)maxLength, RegNums.size());
136    if (DwarfRegNums.count(Reg))
137      errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
138             << "specified multiple times\n";
139    DwarfRegNums[Reg] = RegNums;
140  }
141
142  if (!maxLength)
143    return;
144
145  // Now we know maximal length of number list. Append -1's, where needed
146  for (DwarfRegNumsMapTy::iterator
147       I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
148    for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
149      I->second.push_back(-1);
150
151  std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
152
153  OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
154
155  // Emit reverse information about the dwarf register numbers.
156  for (unsigned j = 0; j < 2; ++j) {
157    for (unsigned i = 0, e = maxLength; i != e; ++i) {
158      OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
159      OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
160      OS << i << "Dwarf2L[]";
161
162      if (!isCtor) {
163        OS << " = {\n";
164
165        // Store the mapping sorted by the LLVM reg num so lookup can be done
166        // with a binary search.
167        std::map<uint64_t, Record*> Dwarf2LMap;
168        for (DwarfRegNumsMapTy::iterator
169               I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
170          int DwarfRegNo = I->second[i];
171          if (DwarfRegNo < 0)
172            continue;
173          Dwarf2LMap[DwarfRegNo] = I->first;
174        }
175
176        for (std::map<uint64_t, Record*>::iterator
177               I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
178          OS << "  { " << I->first << "U, " << getQualifiedName(I->second)
179             << " },\n";
180
181        OS << "};\n";
182      } else {
183        OS << ";\n";
184      }
185
186      // We have to store the size in a const global, it's used in multiple
187      // places.
188      OS << "extern const unsigned " << Namespace
189         << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
190      if (!isCtor)
191        OS << " = sizeof(" << Namespace
192           << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
193           << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
194      else
195        OS << ";\n\n";
196    }
197  }
198
199  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
200    Record *Reg = Regs[i]->TheDef;
201    const RecordVal *V = Reg->getValue("DwarfAlias");
202    if (!V || !V->getValue())
203      continue;
204
205    DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
206    Record *Alias = DI->getDef();
207    DwarfRegNums[Reg] = DwarfRegNums[Alias];
208  }
209
210  // Emit information about the dwarf register numbers.
211  for (unsigned j = 0; j < 2; ++j) {
212    for (unsigned i = 0, e = maxLength; i != e; ++i) {
213      OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
214      OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
215      OS << i << "L2Dwarf[]";
216      if (!isCtor) {
217        OS << " = {\n";
218        // Store the mapping sorted by the Dwarf reg num so lookup can be done
219        // with a binary search.
220        for (DwarfRegNumsMapTy::iterator
221               I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
222          int RegNo = I->second[i];
223          if (RegNo == -1) // -1 is the default value, don't emit a mapping.
224            continue;
225
226          OS << "  { " << getQualifiedName(I->first) << ", " << RegNo
227             << "U },\n";
228        }
229        OS << "};\n";
230      } else {
231        OS << ";\n";
232      }
233
234      // We have to store the size in a const global, it's used in multiple
235      // places.
236      OS << "extern const unsigned " << Namespace
237         << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
238      if (!isCtor)
239        OS << " = sizeof(" << Namespace
240           << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
241           << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
242      else
243        OS << ";\n\n";
244    }
245  }
246}
247
248void
249RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
250                                    const std::vector<CodeGenRegister*> &Regs,
251                                    bool isCtor) {
252  // Emit the initializer so the tables from EmitRegMappingTables get wired up
253  // to the MCRegisterInfo object.
254  unsigned maxLength = 0;
255  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
256    Record *Reg = Regs[i]->TheDef;
257    maxLength = std::max((size_t)maxLength,
258                         Reg->getValueAsListOfInts("DwarfNumbers").size());
259  }
260
261  if (!maxLength)
262    return;
263
264  std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
265
266  // Emit reverse information about the dwarf register numbers.
267  for (unsigned j = 0; j < 2; ++j) {
268    OS << "  switch (";
269    if (j == 0)
270      OS << "DwarfFlavour";
271    else
272      OS << "EHFlavour";
273    OS << ") {\n"
274     << "  default:\n"
275     << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
276
277    for (unsigned i = 0, e = maxLength; i != e; ++i) {
278      OS << "  case " << i << ":\n";
279      OS << "    ";
280      if (!isCtor)
281        OS << "RI->";
282      std::string Tmp;
283      raw_string_ostream(Tmp) << Namespace
284                              << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
285                              << "Dwarf2L";
286      OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
287      if (j == 0)
288          OS << "false";
289        else
290          OS << "true";
291      OS << ");\n";
292      OS << "    break;\n";
293    }
294    OS << "  }\n";
295  }
296
297  // Emit information about the dwarf register numbers.
298  for (unsigned j = 0; j < 2; ++j) {
299    OS << "  switch (";
300    if (j == 0)
301      OS << "DwarfFlavour";
302    else
303      OS << "EHFlavour";
304    OS << ") {\n"
305       << "  default:\n"
306       << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
307
308    for (unsigned i = 0, e = maxLength; i != e; ++i) {
309      OS << "  case " << i << ":\n";
310      OS << "    ";
311      if (!isCtor)
312        OS << "RI->";
313      std::string Tmp;
314      raw_string_ostream(Tmp) << Namespace
315                              << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
316                              << "L2Dwarf";
317      OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
318      if (j == 0)
319          OS << "false";
320        else
321          OS << "true";
322      OS << ");\n";
323      OS << "    break;\n";
324    }
325    OS << "  }\n";
326  }
327}
328
329// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
330// Width is the number of bits per hex number.
331static void printBitVectorAsHex(raw_ostream &OS,
332                                const BitVector &Bits,
333                                unsigned Width) {
334  assert(Width <= 32 && "Width too large");
335  unsigned Digits = (Width + 3) / 4;
336  for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
337    unsigned Value = 0;
338    for (unsigned j = 0; j != Width && i + j != e; ++j)
339      Value |= Bits.test(i + j) << j;
340    OS << format("0x%0*x, ", Digits, Value);
341  }
342}
343
344// Helper to emit a set of bits into a constant byte array.
345class BitVectorEmitter {
346  BitVector Values;
347public:
348  void add(unsigned v) {
349    if (v >= Values.size())
350      Values.resize(((v/8)+1)*8); // Round up to the next byte.
351    Values[v] = true;
352  }
353
354  void print(raw_ostream &OS) {
355    printBitVectorAsHex(OS, Values, 8);
356  }
357};
358
359static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
360  OS << getQualifiedName(Reg->TheDef);
361}
362
363static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
364  OS << getEnumName(VT);
365}
366
367//
368// runMCDesc - Print out MC register descriptions.
369//
370void
371RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
372                               CodeGenRegBank &RegBank) {
373  EmitSourceFileHeader("MC Register Information", OS);
374
375  OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
376  OS << "#undef GET_REGINFO_MC_DESC\n";
377
378  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
379  std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
380  RegBank.computeOverlaps(Overlaps);
381
382  // The lists of sub-registers, super-registers, and overlaps all go in the
383  // same array. That allows us to share suffixes.
384  typedef std::vector<const CodeGenRegister*> RegVec;
385  SmallVector<RegVec, 4> SubRegLists(Regs.size());
386  SmallVector<RegVec, 4> OverlapLists(Regs.size());
387  SequenceToOffsetTable<RegVec, CodeGenRegister::Less> RegSeqs;
388
389  // Precompute register lists for the SequenceToOffsetTable.
390  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
391    const CodeGenRegister *Reg = Regs[i];
392
393    // Compute the ordered sub-register list.
394    SetVector<const CodeGenRegister*> SR;
395    Reg->addSubRegsPreOrder(SR, RegBank);
396    RegVec &SubRegList = SubRegLists[i];
397    SubRegList.assign(SR.begin(), SR.end());
398    RegSeqs.add(SubRegList);
399
400    // Super-registers are already computed.
401    const RegVec &SuperRegList = Reg->getSuperRegs();
402    RegSeqs.add(SuperRegList);
403
404    // The list of overlaps doesn't need to have any particular order, except
405    // Reg itself must be the first element. Pick an ordering that has one of
406    // the other lists as a suffix.
407    RegVec &OverlapList = OverlapLists[i];
408    const RegVec &Suffix = SubRegList.size() > SuperRegList.size() ?
409                           SubRegList : SuperRegList;
410    CodeGenRegister::Set Omit(Suffix.begin(), Suffix.end());
411
412    // First element is Reg itself.
413    OverlapList.push_back(Reg);
414    Omit.insert(Reg);
415
416    // Any elements not in Suffix.
417    const CodeGenRegister::Set &OSet = Overlaps[Reg];
418    std::set_difference(OSet.begin(), OSet.end(),
419                        Omit.begin(), Omit.end(),
420                        std::back_inserter(OverlapList),
421                        CodeGenRegister::Less());
422
423    // Finally, Suffix itself.
424    OverlapList.insert(OverlapList.end(), Suffix.begin(), Suffix.end());
425    RegSeqs.add(OverlapList);
426  }
427
428  // Compute the final layout of the sequence table.
429  RegSeqs.layout();
430
431  OS << "namespace llvm {\n\n";
432
433  const std::string &TargetName = Target.getName();
434
435  // Emit the shared table of register lists.
436  OS << "extern const uint16_t " << TargetName << "RegLists[] = {\n";
437  RegSeqs.emit(OS, printRegister);
438  OS << "};\n\n";
439
440  OS << "extern const MCRegisterDesc " << TargetName
441     << "RegDesc[] = { // Descriptors\n";
442  OS << "  { \"NOREG\", 0, 0, 0 },\n";
443
444  // Emit the register descriptors now.
445  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
446    const CodeGenRegister *Reg = Regs[i];
447    OS << "  { \"" << Reg->getName() << "\", "
448       << RegSeqs.get(OverlapLists[i]) << ", "
449       << RegSeqs.get(SubRegLists[i]) << ", "
450       << RegSeqs.get(Reg->getSuperRegs()) << " },\n";
451  }
452  OS << "};\n\n";      // End of register descriptors...
453
454  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
455
456  // Loop over all of the register classes... emitting each one.
457  OS << "namespace {     // Register classes...\n";
458
459  // Emit the register enum value arrays for each RegisterClass
460  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
461    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
462    ArrayRef<Record*> Order = RC.getOrder();
463
464    // Give the register class a legal C name if it's anonymous.
465    std::string Name = RC.getName();
466
467    // Emit the register list now.
468    OS << "  // " << Name << " Register Class...\n"
469       << "  const uint16_t " << Name
470       << "[] = {\n    ";
471    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
472      Record *Reg = Order[i];
473      OS << getQualifiedName(Reg) << ", ";
474    }
475    OS << "\n  };\n\n";
476
477    OS << "  // " << Name << " Bit set.\n"
478       << "  const uint8_t " << Name
479       << "Bits[] = {\n    ";
480    BitVectorEmitter BVE;
481    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
482      Record *Reg = Order[i];
483      BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
484    }
485    BVE.print(OS);
486    OS << "\n  };\n\n";
487
488  }
489  OS << "}\n\n";
490
491  OS << "extern const MCRegisterClass " << TargetName
492     << "MCRegisterClasses[] = {\n";
493
494  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
495    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
496
497    // Asserts to make sure values will fit in table assuming types from
498    // MCRegisterInfo.h
499    assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
500    assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
501    assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
502
503    OS << "  { " << '\"' << RC.getName() << "\", "
504       << RC.getName() << ", " << RC.getName() << "Bits, "
505       << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
506       << RC.getQualifiedName() + "RegClassID" << ", "
507       << RC.SpillSize/8 << ", "
508       << RC.SpillAlignment/8 << ", "
509       << RC.CopyCost << ", "
510       << RC.Allocatable << " },\n";
511  }
512
513  OS << "};\n\n";
514
515  // Emit the data table for getSubReg().
516  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
517  if (SubRegIndices.size()) {
518    OS << "const uint16_t " << TargetName << "SubRegTable[]["
519       << SubRegIndices.size() << "] = {\n";
520    for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
521      const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
522      OS << "  /* " << Regs[i]->TheDef->getName() << " */\n";
523      if (SRM.empty()) {
524        OS << "  {0},\n";
525        continue;
526      }
527      OS << "  {";
528      for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
529        // FIXME: We really should keep this to 80 columns...
530        CodeGenRegister::SubRegMap::const_iterator SubReg =
531          SRM.find(SubRegIndices[j]);
532        if (SubReg != SRM.end())
533          OS << getQualifiedName(SubReg->second->TheDef);
534        else
535          OS << "0";
536        if (j != je - 1)
537          OS << ", ";
538      }
539      OS << "}" << (i != e ? "," : "") << "\n";
540    }
541    OS << "};\n\n";
542    OS << "const uint16_t *get" << TargetName
543       << "SubRegTable() {\n  return (const uint16_t *)" << TargetName
544       << "SubRegTable;\n}\n\n";
545  }
546
547  EmitRegMappingTables(OS, Regs, false);
548
549  // MCRegisterInfo initialization routine.
550  OS << "static inline void Init" << TargetName
551     << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
552     << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
553  OS << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
554     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
555     << RegisterClasses.size() << ", " << TargetName << "RegLists, ";
556  if (SubRegIndices.size() != 0)
557    OS << "(uint16_t*)" << TargetName << "SubRegTable, "
558       << SubRegIndices.size() << ");\n\n";
559  else
560    OS << "NULL, 0);\n\n";
561
562  EmitRegMapping(OS, Regs, false);
563
564  OS << "}\n\n";
565
566  OS << "} // End llvm namespace \n";
567  OS << "#endif // GET_REGINFO_MC_DESC\n\n";
568}
569
570void
571RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
572                                     CodeGenRegBank &RegBank) {
573  EmitSourceFileHeader("Register Information Header Fragment", OS);
574
575  OS << "\n#ifdef GET_REGINFO_HEADER\n";
576  OS << "#undef GET_REGINFO_HEADER\n";
577
578  const std::string &TargetName = Target.getName();
579  std::string ClassName = TargetName + "GenRegisterInfo";
580
581  OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
582
583  OS << "namespace llvm {\n\n";
584
585  OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
586     << "  explicit " << ClassName
587     << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
588     << "  virtual bool needsStackRealignment(const MachineFunction &) const\n"
589     << "     { return false; }\n"
590     << "  unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
591     << "  const TargetRegisterClass *"
592        "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
593     << "  const TargetRegisterClass *getMatchingSuperRegClass("
594        "const TargetRegisterClass*, const TargetRegisterClass*, "
595        "unsigned) const;\n"
596     << "};\n\n";
597
598  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
599
600  if (!RegisterClasses.empty()) {
601    OS << "namespace " << RegisterClasses[0]->Namespace
602       << " { // Register classes\n";
603
604    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
605      const CodeGenRegisterClass &RC = *RegisterClasses[i];
606      const std::string &Name = RC.getName();
607
608      // Output the extern for the instance.
609      OS << "  extern const TargetRegisterClass " << Name << "RegClass;\n";
610      // Output the extern for the pointer to the instance (should remove).
611      OS << "  static const TargetRegisterClass * const " << Name
612         << "RegisterClass = &" << Name << "RegClass;\n";
613    }
614    OS << "} // end of namespace " << TargetName << "\n\n";
615  }
616  OS << "} // End llvm namespace \n";
617  OS << "#endif // GET_REGINFO_HEADER\n\n";
618}
619
620//
621// runTargetDesc - Output the target register and register file descriptions.
622//
623void
624RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
625                                   CodeGenRegBank &RegBank){
626  EmitSourceFileHeader("Target Register and Register Classes Information", OS);
627
628  OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
629  OS << "#undef GET_REGINFO_TARGET_DESC\n";
630
631  OS << "namespace llvm {\n\n";
632
633  // Get access to MCRegisterClass data.
634  OS << "extern const MCRegisterClass " << Target.getName()
635     << "MCRegisterClasses[];\n";
636
637  // Start out by emitting each of the register classes.
638  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
639
640  // Collect all registers belonging to any allocatable class.
641  std::set<Record*> AllocatableRegs;
642
643  // Collect allocatable registers.
644  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
645    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
646    ArrayRef<Record*> Order = RC.getOrder();
647
648    if (RC.Allocatable)
649      AllocatableRegs.insert(Order.begin(), Order.end());
650  }
651
652  // Build a shared array of value types.
653  SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
654  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
655    VTSeqs.add(RegisterClasses[rc]->VTs);
656  VTSeqs.layout();
657  OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
658  VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
659  OS << "};\n";
660
661  // Now that all of the structs have been emitted, emit the instances.
662  if (!RegisterClasses.empty()) {
663    std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
664
665    OS << "\nstatic const TargetRegisterClass *const "
666       << "NullRegClasses[] = { NULL };\n\n";
667
668    unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
669
670    if (NumSubRegIndices) {
671      // Compute the super-register classes for each RegisterClass
672      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
673        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
674        for (DenseMap<Record*,Record*>::const_iterator
675             i = RC.SubRegClasses.begin(),
676             e = RC.SubRegClasses.end(); i != e; ++i) {
677          // Find the register class number of i->second for SuperRegClassMap.
678          const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
679          assert(RC2 && "Invalid register class in SubRegClasses");
680          SuperRegClassMap[RC2->EnumValue].insert(rc);
681        }
682      }
683
684      // Emit the super-register classes for each RegisterClass
685      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
686        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
687
688        // Give the register class a legal C name if it's anonymous.
689        std::string Name = RC.getName();
690
691        OS << "// " << Name
692           << " Super-register Classes...\n"
693           << "static const TargetRegisterClass *const "
694           << Name << "SuperRegClasses[] = {\n  ";
695
696        bool Empty = true;
697        std::map<unsigned, std::set<unsigned> >::iterator I =
698          SuperRegClassMap.find(rc);
699        if (I != SuperRegClassMap.end()) {
700          for (std::set<unsigned>::iterator II = I->second.begin(),
701                 EE = I->second.end(); II != EE; ++II) {
702            const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
703            if (!Empty)
704              OS << ", ";
705            OS << "&" << RC2.getQualifiedName() << "RegClass";
706            Empty = false;
707          }
708        }
709
710        OS << (!Empty ? ", " : "") << "NULL";
711        OS << "\n};\n\n";
712      }
713    }
714
715    // Emit the sub-classes array for each RegisterClass
716    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
717      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
718
719      // Give the register class a legal C name if it's anonymous.
720      std::string Name = RC.getName();
721
722      OS << "static const uint32_t " << Name << "SubclassMask[] = {\n  ";
723      printBitVectorAsHex(OS, RC.getSubClasses(), 32);
724      OS << "\n};\n\n";
725    }
726
727    // Emit NULL terminated super-class lists.
728    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
729      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
730      ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
731
732      // Skip classes without supers.  We can reuse NullRegClasses.
733      if (Supers.empty())
734        continue;
735
736      OS << "static const TargetRegisterClass *const "
737         << RC.getName() << "Superclasses[] = {\n";
738      for (unsigned i = 0; i != Supers.size(); ++i)
739        OS << "  &" << Supers[i]->getQualifiedName() << "RegClass,\n";
740      OS << "  NULL\n};\n\n";
741    }
742
743    // Emit methods.
744    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
745      const CodeGenRegisterClass &RC = *RegisterClasses[i];
746      if (!RC.AltOrderSelect.empty()) {
747        OS << "\nstatic inline unsigned " << RC.getName()
748           << "AltOrderSelect(const MachineFunction &MF) {"
749           << RC.AltOrderSelect << "}\n\n"
750           << "static ArrayRef<uint16_t> " << RC.getName()
751           << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
752        for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
753          ArrayRef<Record*> Elems = RC.getOrder(oi);
754          if (!Elems.empty()) {
755            OS << "  static const uint16_t AltOrder" << oi << "[] = {";
756            for (unsigned elem = 0; elem != Elems.size(); ++elem)
757              OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
758            OS << " };\n";
759          }
760        }
761        OS << "  const MCRegisterClass &MCR = " << Target.getName()
762           << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
763           << "  const ArrayRef<uint16_t> Order[] = {\n"
764           << "    makeArrayRef(MCR.begin(), MCR.getNumRegs()";
765        for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
766          if (RC.getOrder(oi).empty())
767            OS << "),\n    ArrayRef<uint16_t>(";
768          else
769            OS << "),\n    makeArrayRef(AltOrder" << oi;
770        OS << ")\n  };\n  const unsigned Select = " << RC.getName()
771           << "AltOrderSelect(MF);\n  assert(Select < " << RC.getNumOrders()
772           << ");\n  return Order[Select];\n}\n";
773        }
774    }
775
776    // Now emit the actual value-initialized register class instances.
777    OS << "namespace " << RegisterClasses[0]->Namespace
778       << " {   // Register class instances\n";
779
780    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
781      const CodeGenRegisterClass &RC = *RegisterClasses[i];
782      OS << "  extern const TargetRegisterClass "
783         << RegisterClasses[i]->getName() << "RegClass = {\n    "
784         << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
785         << "RegClassID],\n    "
786         << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n    "
787         << RC.getName() << "SubclassMask,\n    ";
788      if (RC.getSuperClasses().empty())
789        OS << "NullRegClasses,\n    ";
790      else
791        OS << RC.getName() << "Superclasses,\n    ";
792      OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
793         << "RegClasses,\n    ";
794      if (RC.AltOrderSelect.empty())
795        OS << "0\n";
796      else
797        OS << RC.getName() << "GetRawAllocationOrder\n";
798      OS << "  };\n\n";
799    }
800
801    OS << "}\n";
802  }
803
804  OS << "\nnamespace {\n";
805  OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
806  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
807    OS << "    &" << RegisterClasses[i]->getQualifiedName()
808       << "RegClass,\n";
809  OS << "  };\n";
810  OS << "}\n";       // End of anonymous namespace...
811
812  // Emit extra information about registers.
813  const std::string &TargetName = Target.getName();
814  OS << "\nstatic const TargetRegisterInfoDesc "
815     << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
816  OS << "  { 0, 0 },\n";
817
818  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
819  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
820    const CodeGenRegister &Reg = *Regs[i];
821    OS << "  { ";
822    OS << Reg.CostPerUse << ", "
823       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
824  }
825  OS << "};\n";      // End of register descriptors...
826
827
828  // Calculate the mapping of subregister+index pairs to physical registers.
829  // This will also create further anonymous indices.
830  unsigned NamedIndices = RegBank.getNumNamedIndices();
831
832  // Emit SubRegIndex names, skipping 0
833  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
834  OS << "\nstatic const char *const " << TargetName
835     << "SubRegIndexTable[] = { \"";
836  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
837    OS << SubRegIndices[i]->getName();
838    if (i+1 != e)
839      OS << "\", \"";
840  }
841  OS << "\" };\n\n";
842
843  // Emit names of the anonymous subreg indices.
844  if (SubRegIndices.size() > NamedIndices) {
845    OS << "  enum {";
846    for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
847      OS << "\n    " << SubRegIndices[i]->getName() << " = " << i+1;
848      if (i+1 != e)
849        OS << ',';
850    }
851    OS << "\n  };\n\n";
852  }
853  OS << "\n";
854
855  std::string ClassName = Target.getName() + "GenRegisterInfo";
856
857  // Emit composeSubRegIndices
858  OS << "unsigned " << ClassName
859     << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
860     << "  switch (IdxA) {\n"
861     << "  default:\n    return IdxB;\n";
862  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
863    bool Open = false;
864    for (unsigned j = 0; j != e; ++j) {
865      if (CodeGenSubRegIndex *Comp =
866            SubRegIndices[i]->compose(SubRegIndices[j])) {
867        if (!Open) {
868          OS << "  case " << SubRegIndices[i]->getQualifiedName()
869             << ": switch(IdxB) {\n    default: return IdxB;\n";
870          Open = true;
871        }
872        OS << "    case " << SubRegIndices[j]->getQualifiedName()
873           << ": return " << Comp->getQualifiedName() << ";\n";
874      }
875    }
876    if (Open)
877      OS << "    }\n";
878  }
879  OS << "  }\n}\n\n";
880
881  // Emit getSubClassWithSubReg.
882  OS << "const TargetRegisterClass *" << ClassName
883     << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
884        " const {\n";
885  if (SubRegIndices.empty()) {
886    OS << "  assert(Idx == 0 && \"Target has no sub-registers\");\n"
887       << "  return RC;\n";
888  } else {
889    // Use the smallest type that can hold a regclass ID with room for a
890    // sentinel.
891    if (RegisterClasses.size() < UINT8_MAX)
892      OS << "  static const uint8_t Table[";
893    else if (RegisterClasses.size() < UINT16_MAX)
894      OS << "  static const uint16_t Table[";
895    else
896      throw "Too many register classes.";
897    OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
898    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
899      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
900      OS << "    {\t// " << RC.getName() << "\n";
901      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
902        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
903        if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
904          OS << "      " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
905             << " -> " << SRC->getName() << "\n";
906        else
907          OS << "      0,\t// " << Idx->getName() << "\n";
908      }
909      OS << "    },\n";
910    }
911    OS << "  };\n  assert(RC && \"Missing regclass\");\n"
912       << "  if (!Idx) return RC;\n  --Idx;\n"
913       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
914       << "  unsigned TV = Table[RC->getID()][Idx];\n"
915       << "  return TV ? getRegClass(TV - 1) : 0;\n";
916  }
917  OS << "}\n\n";
918
919  // Emit getMatchingSuperRegClass.
920  OS << "const TargetRegisterClass *" << ClassName
921     << "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
922        " const TargetRegisterClass *B, unsigned Idx) const {\n";
923  if (SubRegIndices.empty()) {
924    OS << "  llvm_unreachable(\"Target has no sub-registers\");\n";
925  } else {
926    // We need to find the largest sub-class of A such that every register has
927    // an Idx sub-register in B.  Map (B, Idx) to a bit-vector of
928    // super-register classes that map into B. Then compute the largest common
929    // sub-class with A by taking advantage of the register class ordering,
930    // like getCommonSubClass().
931
932    // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
933    // the number of 32-bit words required to represent all register classes.
934    const unsigned BVWords = (RegisterClasses.size()+31)/32;
935    BitVector BV(RegisterClasses.size());
936
937    OS << "  static const uint32_t Table[" << RegisterClasses.size()
938       << "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
939    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
940      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
941      OS << "    {\t// " << RC.getName() << "\n";
942      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
943        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
944        BV.reset();
945        RC.getSuperRegClasses(Idx, BV);
946        OS << "      { ";
947        printBitVectorAsHex(OS, BV, 32);
948        OS << "},\t// " << Idx->getName() << '\n';
949      }
950      OS << "    },\n";
951    }
952    OS << "  };\n  assert(A && B && \"Missing regclass\");\n"
953       << "  --Idx;\n"
954       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
955       << "  const uint32_t *TV = Table[B->getID()][Idx];\n"
956       << "  const uint32_t *SC = A->getSubClassMask();\n"
957       << "  for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
958       << "    if (unsigned Common = TV[i] & SC[i])\n"
959       << "      return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
960       << "  return 0;\n";
961  }
962  OS << "}\n\n";
963
964  // Emit the constructor of the class...
965  OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
966  OS << "extern const uint16_t " << TargetName << "RegLists[];\n";
967  if (SubRegIndices.size() != 0)
968    OS << "extern const uint16_t *get" << TargetName
969       << "SubRegTable();\n";
970
971  EmitRegMappingTables(OS, Regs, true);
972
973  OS << ClassName << "::\n" << ClassName
974     << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
975     << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
976     << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
977     << "             " << TargetName << "SubRegIndexTable) {\n"
978     << "  InitMCRegisterInfo(" << TargetName << "RegDesc, "
979     << Regs.size()+1 << ", RA,\n                     " << TargetName
980     << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
981     << "                     " << TargetName << "RegLists,\n"
982     << "                     ";
983  if (SubRegIndices.size() != 0)
984    OS << "get" << TargetName << "SubRegTable(), "
985       << SubRegIndices.size() << ");\n\n";
986  else
987    OS << "NULL, 0);\n\n";
988
989  EmitRegMapping(OS, Regs, true);
990
991  OS << "}\n\n";
992
993
994  // Emit CalleeSavedRegs information.
995  std::vector<Record*> CSRSets =
996    Records.getAllDerivedDefinitions("CalleeSavedRegs");
997  for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
998    Record *CSRSet = CSRSets[i];
999    const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1000    assert(Regs && "Cannot expand CalleeSavedRegs instance");
1001
1002    // Emit the *_SaveList list of callee-saved registers.
1003    OS << "static const uint16_t " << CSRSet->getName()
1004       << "_SaveList[] = { ";
1005    for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1006      OS << getQualifiedName((*Regs)[r]) << ", ";
1007    OS << "0 };\n";
1008
1009    // Emit the *_RegMask bit mask of call-preserved registers.
1010    OS << "static const uint32_t " << CSRSet->getName()
1011       << "_RegMask[] = { ";
1012    printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1013    OS << "};\n";
1014  }
1015  OS << "\n\n";
1016
1017  OS << "} // End llvm namespace \n";
1018  OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1019}
1020
1021void RegisterInfoEmitter::run(raw_ostream &OS) {
1022  CodeGenTarget Target(Records);
1023  CodeGenRegBank &RegBank = Target.getRegBank();
1024  RegBank.computeDerivedInfo();
1025
1026  runEnums(OS, Target, RegBank);
1027  runMCDesc(OS, Target, RegBank);
1028  runTargetHeader(OS, Target, RegBank);
1029  runTargetDesc(OS, Target, RegBank);
1030}
1031