RegisterInfoEmitter.cpp revision 9d91c5d31c6758124559c0916d852295f47a2bec 
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of a target
11// register file for a code generator.  It uses instances of the Register,
12// RegisterAliases, and RegisterClass classes to gather this information.
13//
14//===----------------------------------------------------------------------===//
15
16#include "RegisterInfoEmitter.h"
17#include "CodeGenTarget.h"
18#include "CodeGenRegisters.h"
19#include "llvm/TableGen/Record.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/Support/Format.h"
24#include <algorithm>
25#include <set>
26using namespace llvm;
27
28// runEnums - Print out enum values for all of the registers.
29void
30RegisterInfoEmitter::runEnums(raw_ostream &OS,
31                              CodeGenTarget &Target, CodeGenRegBank &Bank) {
32  const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33
34  std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
35
36  EmitSourceFileHeader("Target Register Enum Values", OS);
37
38  OS << "\n#ifdef GET_REGINFO_ENUM\n";
39  OS << "#undef GET_REGINFO_ENUM\n";
40
41  OS << "namespace llvm {\n\n";
42
43  OS << "class MCRegisterClass;\n"
44     << "extern const MCRegisterClass " << Namespace
45     << "MCRegisterClasses[];\n\n";
46
47  if (!Namespace.empty())
48    OS << "namespace " << Namespace << " {\n";
49  OS << "enum {\n  NoRegister,\n";
50
51  for (unsigned i = 0, e = Registers.size(); i != e; ++i)
52    OS << "  " << Registers[i]->getName() << " = " <<
53      Registers[i]->EnumValue << ",\n";
54  assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
55         "Register enum value mismatch!");
56  OS << "  NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
57  OS << "};\n";
58  if (!Namespace.empty())
59    OS << "}\n";
60
61  ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
62  if (!RegisterClasses.empty()) {
63    OS << "\n// Register classes\n";
64    if (!Namespace.empty())
65      OS << "namespace " << Namespace << " {\n";
66    OS << "enum {\n";
67    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
68      if (i) OS << ",\n";
69      OS << "  " << RegisterClasses[i]->getName() << "RegClassID";
70      OS << " = " << i;
71    }
72    OS << "\n  };\n";
73    if (!Namespace.empty())
74      OS << "}\n";
75  }
76
77  const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
78  // If the only definition is the default NoRegAltName, we don't need to
79  // emit anything.
80  if (RegAltNameIndices.size() > 1) {
81    OS << "\n// Register alternate name indices\n";
82    if (!Namespace.empty())
83      OS << "namespace " << Namespace << " {\n";
84    OS << "enum {\n";
85    for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
86      OS << "  " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
87    OS << "  NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
88    OS << "};\n";
89    if (!Namespace.empty())
90      OS << "}\n";
91  }
92
93
94  OS << "} // End llvm namespace \n";
95  OS << "#endif // GET_REGINFO_ENUM\n\n";
96}
97
98void
99RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
100                                    const std::vector<CodeGenRegister*> &Regs,
101                                    bool isCtor) {
102
103  // Collect all information about dwarf register numbers
104  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
105  DwarfRegNumsMapTy DwarfRegNums;
106
107  // First, just pull all provided information to the map
108  unsigned maxLength = 0;
109  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
110    Record *Reg = Regs[i]->TheDef;
111    std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
112    maxLength = std::max((size_t)maxLength, RegNums.size());
113    if (DwarfRegNums.count(Reg))
114      errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
115             << "specified multiple times\n";
116    DwarfRegNums[Reg] = RegNums;
117  }
118
119  if (!maxLength)
120    return;
121
122  // Now we know maximal length of number list. Append -1's, where needed
123  for (DwarfRegNumsMapTy::iterator
124       I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
125    for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
126      I->second.push_back(-1);
127
128  // Emit reverse information about the dwarf register numbers.
129  for (unsigned j = 0; j < 2; ++j) {
130    OS << "  switch (";
131    if (j == 0)
132      OS << "DwarfFlavour";
133    else
134      OS << "EHFlavour";
135    OS << ") {\n"
136     << "  default:\n"
137     << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
138
139    for (unsigned i = 0, e = maxLength; i != e; ++i) {
140      OS << "  case " << i << ":\n";
141      for (DwarfRegNumsMapTy::iterator
142             I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
143        int DwarfRegNo = I->second[i];
144        if (DwarfRegNo < 0)
145          continue;
146        OS << "    ";
147        if (!isCtor)
148          OS << "RI->";
149        OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
150           << getQualifiedName(I->first) << ", ";
151        if (j == 0)
152          OS << "false";
153        else
154          OS << "true";
155        OS << " );\n";
156      }
157      OS << "    break;\n";
158    }
159    OS << "  }\n";
160  }
161
162  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
163    Record *Reg = Regs[i]->TheDef;
164    const RecordVal *V = Reg->getValue("DwarfAlias");
165    if (!V || !V->getValue())
166      continue;
167
168    DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
169    Record *Alias = DI->getDef();
170    DwarfRegNums[Reg] = DwarfRegNums[Alias];
171  }
172
173  // Emit information about the dwarf register numbers.
174  for (unsigned j = 0; j < 2; ++j) {
175    OS << "  switch (";
176    if (j == 0)
177      OS << "DwarfFlavour";
178    else
179      OS << "EHFlavour";
180    OS << ") {\n"
181       << "  default:\n"
182       << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
183
184    for (unsigned i = 0, e = maxLength; i != e; ++i) {
185      OS << "  case " << i << ":\n";
186      // Sort by name to get a stable order.
187      for (DwarfRegNumsMapTy::iterator
188             I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
189        int RegNo = I->second[i];
190        if (RegNo == -1) // -1 is the default value, don't emit a mapping.
191          continue;
192
193        OS << "    ";
194        if (!isCtor)
195          OS << "RI->";
196        OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
197           <<  RegNo << ", ";
198        if (j == 0)
199          OS << "false";
200        else
201          OS << "true";
202        OS << " );\n";
203      }
204      OS << "    break;\n";
205    }
206    OS << "  }\n";
207  }
208}
209
210// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
211// Width is the number of bits per hex number.
212static void printBitVectorAsHex(raw_ostream &OS,
213                                const BitVector &Bits,
214                                unsigned Width) {
215  assert(Width <= 32 && "Width too large");
216  unsigned Digits = (Width + 3) / 4;
217  for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
218    unsigned Value = 0;
219    for (unsigned j = 0; j != Width && i + j != e; ++j)
220      Value |= Bits.test(i + j) << j;
221    OS << format("0x%0*x, ", Digits, Value);
222  }
223}
224
225// Helper to emit a set of bits into a constant byte array.
226class BitVectorEmitter {
227  BitVector Values;
228public:
229  void add(unsigned v) {
230    if (v >= Values.size())
231      Values.resize(((v/8)+1)*8); // Round up to the next byte.
232    Values[v] = true;
233  }
234
235  void print(raw_ostream &OS) {
236    printBitVectorAsHex(OS, Values, 8);
237  }
238};
239
240//
241// runMCDesc - Print out MC register descriptions.
242//
243void
244RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
245                               CodeGenRegBank &RegBank) {
246  EmitSourceFileHeader("MC Register Information", OS);
247
248  OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
249  OS << "#undef GET_REGINFO_MC_DESC\n";
250
251  std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
252  RegBank.computeOverlaps(Overlaps);
253
254  OS << "namespace llvm {\n\n";
255
256  const std::string &TargetName = Target.getName();
257
258  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
259
260  OS << "extern const unsigned " << TargetName << "RegOverlaps[] = {\n";
261
262  // Emit an overlap list for all registers.
263  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
264    const CodeGenRegister *Reg = Regs[i];
265    const CodeGenRegister::Set &O = Overlaps[Reg];
266    // Move Reg to the front so TRI::getAliasSet can share the list.
267    OS << "  /* " << Reg->getName() << "_Overlaps */ "
268       << getQualifiedName(Reg->TheDef) << ", ";
269    for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
270         I != E; ++I)
271      if (*I != Reg)
272        OS << getQualifiedName((*I)->TheDef) << ", ";
273    OS << "0,\n";
274  }
275  OS << "};\n\n";
276
277  OS << "extern const unsigned " << TargetName << "SubRegsSet[] = {\n";
278  // Emit the empty sub-registers list
279  OS << "  /* Empty_SubRegsSet */ 0,\n";
280  // Loop over all of the registers which have sub-registers, emitting the
281  // sub-registers list to memory.
282  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
283    const CodeGenRegister &Reg = *Regs[i];
284    if (Reg.getSubRegs().empty())
285     continue;
286    // getSubRegs() orders by SubRegIndex. We want a topological order.
287    SetVector<CodeGenRegister*> SR;
288    Reg.addSubRegsPreOrder(SR, RegBank);
289    OS << "  /* " << Reg.getName() << "_SubRegsSet */ ";
290    for (unsigned j = 0, je = SR.size(); j != je; ++j)
291      OS << getQualifiedName(SR[j]->TheDef) << ", ";
292    OS << "0,\n";
293  }
294  OS << "};\n\n";
295
296  OS << "extern const unsigned " << TargetName << "SuperRegsSet[] = {\n";
297  // Emit the empty super-registers list
298  OS << "  /* Empty_SuperRegsSet */ 0,\n";
299  // Loop over all of the registers which have super-registers, emitting the
300  // super-registers list to memory.
301  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
302    const CodeGenRegister &Reg = *Regs[i];
303    const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
304    if (SR.empty())
305      continue;
306    OS << "  /* " << Reg.getName() << "_SuperRegsSet */ ";
307    for (unsigned j = 0, je = SR.size(); j != je; ++j)
308      OS << getQualifiedName(SR[j]->TheDef) << ", ";
309    OS << "0,\n";
310  }
311  OS << "};\n\n";
312
313  OS << "extern const MCRegisterDesc " << TargetName
314     << "RegDesc[] = { // Descriptors\n";
315  OS << "  { \"NOREG\", 0, 0, 0 },\n";
316
317  // Now that register alias and sub-registers sets have been emitted, emit the
318  // register descriptors now.
319  unsigned OverlapsIndex = 0;
320  unsigned SubRegIndex = 1; // skip 1 for empty set
321  unsigned SuperRegIndex = 1; // skip 1 for empty set
322  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
323    const CodeGenRegister *Reg = Regs[i];
324    OS << "  { \"";
325    OS << Reg->getName() << "\", /* " << Reg->getName() << "_Overlaps */ "
326       << OverlapsIndex << ", ";
327    OverlapsIndex += Overlaps[Reg].size() + 1;
328    if (!Reg->getSubRegs().empty()) {
329      OS << "/* " << Reg->getName() << "_SubRegsSet */ " << SubRegIndex
330         << ", ";
331      // FIXME not very nice to recalculate this
332      SetVector<CodeGenRegister*> SR;
333      Reg->addSubRegsPreOrder(SR, RegBank);
334      SubRegIndex += SR.size() + 1;
335    } else
336      OS << "/* Empty_SubRegsSet */ 0, ";
337    if (!Reg->getSuperRegs().empty()) {
338      OS << "/* " << Reg->getName() << "_SuperRegsSet */ " << SuperRegIndex;
339      SuperRegIndex += Reg->getSuperRegs().size() + 1;
340    } else
341      OS << "/* Empty_SuperRegsSet */ 0";
342    OS << " },\n";
343  }
344  OS << "};\n\n";      // End of register descriptors...
345
346  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
347
348  // Loop over all of the register classes... emitting each one.
349  OS << "namespace {     // Register classes...\n";
350
351  // Emit the register enum value arrays for each RegisterClass
352  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
353    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
354    ArrayRef<Record*> Order = RC.getOrder();
355
356    // Give the register class a legal C name if it's anonymous.
357    std::string Name = RC.getName();
358
359    // Emit the register list now.
360    OS << "  // " << Name << " Register Class...\n"
361       << "  const unsigned " << Name
362       << "[] = {\n    ";
363    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
364      Record *Reg = Order[i];
365      OS << getQualifiedName(Reg) << ", ";
366    }
367    OS << "\n  };\n\n";
368
369    OS << "  // " << Name << " Bit set.\n"
370       << "  const unsigned char " << Name
371       << "Bits[] = {\n    ";
372    BitVectorEmitter BVE;
373    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
374      Record *Reg = Order[i];
375      BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
376    }
377    BVE.print(OS);
378    OS << "\n  };\n\n";
379
380  }
381  OS << "}\n\n";
382
383  OS << "extern const MCRegisterClass " << TargetName
384     << "MCRegisterClasses[] = {\n";
385
386  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
387    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
388    OS << "  { " << RC.getQualifiedName() + "RegClassID" << ", "
389       << '\"' << RC.getName() << "\", "
390       << RC.SpillSize/8 << ", "
391       << RC.SpillAlignment/8 << ", "
392       << RC.CopyCost << ", "
393       << RC.Allocatable << ", "
394       << RC.getName() << ", " << RC.getName() << "Bits, "
395       << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits) },\n";
396  }
397
398  OS << "};\n\n";
399
400  // MCRegisterInfo initialization routine.
401  OS << "static inline void Init" << TargetName
402     << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
403     << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
404  OS << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
405     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
406     << RegisterClasses.size() << ", " << TargetName << "RegOverlaps, "
407     << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet);\n\n";
408
409  EmitRegMapping(OS, Regs, false);
410
411  OS << "}\n\n";
412
413
414  OS << "} // End llvm namespace \n";
415  OS << "#endif // GET_REGINFO_MC_DESC\n\n";
416}
417
418void
419RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
420                                     CodeGenRegBank &RegBank) {
421  EmitSourceFileHeader("Register Information Header Fragment", OS);
422
423  OS << "\n#ifdef GET_REGINFO_HEADER\n";
424  OS << "#undef GET_REGINFO_HEADER\n";
425
426  const std::string &TargetName = Target.getName();
427  std::string ClassName = TargetName + "GenRegisterInfo";
428
429  OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
430  OS << "#include <string>\n\n";
431
432  OS << "namespace llvm {\n\n";
433
434  OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
435     << "  explicit " << ClassName
436     << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
437     << "  virtual bool needsStackRealignment(const MachineFunction &) const\n"
438     << "     { return false; }\n"
439     << "  unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
440     << "  unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
441     << "  unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
442     << "  const TargetRegisterClass *"
443        "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
444     << "  const TargetRegisterClass *getMatchingSuperRegClass("
445        "const TargetRegisterClass*, const TargetRegisterClass*, "
446        "unsigned) const;\n"
447     << "};\n\n";
448
449  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
450  if (!SubRegIndices.empty()) {
451    OS << "\n// Subregister indices\n";
452    std::string Namespace =
453      SubRegIndices[0]->getNamespace();
454    if (!Namespace.empty())
455      OS << "namespace " << Namespace << " {\n";
456    OS << "enum {\n  NoSubRegister,\n";
457    for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
458      OS << "  " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
459    OS << "  NUM_TARGET_NAMED_SUBREGS\n};\n";
460    if (!Namespace.empty())
461      OS << "}\n";
462  }
463
464  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
465
466  if (!RegisterClasses.empty()) {
467    OS << "namespace " << RegisterClasses[0]->Namespace
468       << " { // Register classes\n";
469
470    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
471      const CodeGenRegisterClass &RC = *RegisterClasses[i];
472      const std::string &Name = RC.getName();
473
474      // Output the register class definition.
475      OS << "  struct " << Name << "Class : public TargetRegisterClass {\n"
476         << "    " << Name << "Class();\n";
477      if (!RC.AltOrderSelect.empty())
478        OS << "    ArrayRef<unsigned> "
479              "getRawAllocationOrder(const MachineFunction&) const;\n";
480      OS << "  };\n";
481
482      // Output the extern for the instance.
483      OS << "  extern const " << Name << "Class " << Name << "RegClass;\n";
484      // Output the extern for the pointer to the instance (should remove).
485      OS << "  static const TargetRegisterClass * const " << Name
486         << "RegisterClass = &" << Name << "RegClass;\n";
487    }
488    OS << "} // end of namespace " << TargetName << "\n\n";
489  }
490  OS << "} // End llvm namespace \n";
491  OS << "#endif // GET_REGINFO_HEADER\n\n";
492}
493
494//
495// runTargetDesc - Output the target register and register file descriptions.
496//
497void
498RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
499                                   CodeGenRegBank &RegBank){
500  EmitSourceFileHeader("Target Register and Register Classes Information", OS);
501
502  OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
503  OS << "#undef GET_REGINFO_TARGET_DESC\n";
504
505  OS << "namespace llvm {\n\n";
506
507  // Get access to MCRegisterClass data.
508  OS << "extern const MCRegisterClass " << Target.getName()
509     << "MCRegisterClasses[];\n";
510
511  // Start out by emitting each of the register classes.
512  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
513
514  // Collect all registers belonging to any allocatable class.
515  std::set<Record*> AllocatableRegs;
516
517  // Collect allocatable registers.
518  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
519    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
520    ArrayRef<Record*> Order = RC.getOrder();
521
522    if (RC.Allocatable)
523      AllocatableRegs.insert(Order.begin(), Order.end());
524  }
525
526  OS << "namespace {     // Register classes...\n";
527
528  // Emit the ValueType arrays for each RegisterClass
529  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
530    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
531
532    // Give the register class a legal C name if it's anonymous.
533    std::string Name = RC.getName() + "VTs";
534
535    // Emit the register list now.
536    OS << "  // " << Name
537       << " Register Class Value Types...\n"
538       << "  const MVT::SimpleValueType " << Name
539       << "[] = {\n    ";
540    for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
541      OS << getEnumName(RC.VTs[i]) << ", ";
542    OS << "MVT::Other\n  };\n\n";
543  }
544  OS << "}  // end anonymous namespace\n\n";
545
546  // Now that all of the structs have been emitted, emit the instances.
547  if (!RegisterClasses.empty()) {
548    OS << "namespace " << RegisterClasses[0]->Namespace
549       << " {   // Register class instances\n";
550    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
551      OS << "  extern const " << RegisterClasses[i]->getName()  << "Class "
552         << RegisterClasses[i]->getName() << "RegClass = "
553         << RegisterClasses[i]->getName() << "Class();\n";
554
555    std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
556
557    OS << "\n  static const TargetRegisterClass* const "
558      << "NullRegClasses[] = { NULL };\n\n";
559
560    unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
561
562    if (NumSubRegIndices) {
563      // Compute the super-register classes for each RegisterClass
564      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
565        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
566        for (DenseMap<Record*,Record*>::const_iterator
567             i = RC.SubRegClasses.begin(),
568             e = RC.SubRegClasses.end(); i != e; ++i) {
569          // Find the register class number of i->second for SuperRegClassMap.
570          const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
571          assert(RC2 && "Invalid register class in SubRegClasses");
572          SuperRegClassMap[RC2->EnumValue].insert(rc);
573        }
574      }
575
576      // Emit the super-register classes for each RegisterClass
577      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
578        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
579
580        // Give the register class a legal C name if it's anonymous.
581        std::string Name = RC.getName();
582
583        OS << "  // " << Name
584           << " Super-register Classes...\n"
585           << "  static const TargetRegisterClass* const "
586           << Name << "SuperRegClasses[] = {\n    ";
587
588        bool Empty = true;
589        std::map<unsigned, std::set<unsigned> >::iterator I =
590          SuperRegClassMap.find(rc);
591        if (I != SuperRegClassMap.end()) {
592          for (std::set<unsigned>::iterator II = I->second.begin(),
593                 EE = I->second.end(); II != EE; ++II) {
594            const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
595            if (!Empty)
596              OS << ", ";
597            OS << "&" << RC2.getQualifiedName() << "RegClass";
598            Empty = false;
599          }
600        }
601
602        OS << (!Empty ? ", " : "") << "NULL";
603        OS << "\n  };\n\n";
604      }
605    }
606
607    // Emit the sub-classes array for each RegisterClass
608    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
609      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
610
611      // Give the register class a legal C name if it's anonymous.
612      std::string Name = RC.getName();
613
614      OS << "  static const unsigned " << Name << "SubclassMask[] = { ";
615      printBitVectorAsHex(OS, RC.getSubClasses(), 32);
616      OS << "};\n\n";
617    }
618
619    // Emit NULL terminated super-class lists.
620    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
621      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
622      ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
623
624      // Skip classes without supers.  We can reuse NullRegClasses.
625      if (Supers.empty())
626        continue;
627
628      OS << "  static const TargetRegisterClass* const "
629         << RC.getName() << "Superclasses[] = {\n";
630      for (unsigned i = 0; i != Supers.size(); ++i)
631        OS << "    &" << Supers[i]->getQualifiedName() << "RegClass,\n";
632      OS << "    NULL\n  };\n\n";
633    }
634
635    // Emit methods.
636    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
637      const CodeGenRegisterClass &RC = *RegisterClasses[i];
638      OS << RC.getName() << "Class::" << RC.getName()
639         << "Class()  : TargetRegisterClass(&"
640         << Target.getName() << "MCRegisterClasses["
641         << RC.getName() + "RegClassID" << "], "
642         << RC.getName() + "VTs" << ", "
643         << RC.getName() + "SubclassMask" << ", ";
644      if (RC.getSuperClasses().empty())
645        OS << "NullRegClasses, ";
646      else
647        OS << RC.getName() + "Superclasses, ";
648      OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
649         << "RegClasses"
650         << ") {}\n";
651      if (!RC.AltOrderSelect.empty()) {
652        OS << "\nstatic inline unsigned " << RC.getName()
653           << "AltOrderSelect(const MachineFunction &MF) {"
654           << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
655           << RC.getName() << "Class::"
656           << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
657        for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
658          ArrayRef<Record*> Elems = RC.getOrder(oi);
659          if (!Elems.empty()) {
660            OS << "  static const unsigned AltOrder" << oi << "[] = {";
661            for (unsigned elem = 0; elem != Elems.size(); ++elem)
662              OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
663            OS << " };\n";
664          }
665        }
666        OS << "  const MCRegisterClass &MCR = " << Target.getName()
667           << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
668           << "  static const ArrayRef<unsigned> Order[] = {\n"
669           << "    makeArrayRef(MCR.begin(), MCR.getNumRegs()";
670        for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
671          if (RC.getOrder(oi).empty())
672            OS << "),\n    ArrayRef<unsigned>(";
673          else
674            OS << "),\n    makeArrayRef(AltOrder" << oi;
675        OS << ")\n  };\n  const unsigned Select = " << RC.getName()
676           << "AltOrderSelect(MF);\n  assert(Select < " << RC.getNumOrders()
677           << ");\n  return Order[Select];\n}\n";
678        }
679    }
680
681    OS << "}\n";
682  }
683
684  OS << "\nnamespace {\n";
685  OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
686  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
687    OS << "    &" << RegisterClasses[i]->getQualifiedName()
688       << "RegClass,\n";
689  OS << "  };\n";
690  OS << "}\n";       // End of anonymous namespace...
691
692  // Emit extra information about registers.
693  const std::string &TargetName = Target.getName();
694  OS << "\n  static const TargetRegisterInfoDesc "
695     << TargetName << "RegInfoDesc[] = "
696     << "{ // Extra Descriptors\n";
697  OS << "    { 0, 0 },\n";
698
699  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
700  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
701    const CodeGenRegister &Reg = *Regs[i];
702    OS << "    { ";
703    OS << Reg.CostPerUse << ", "
704       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
705  }
706  OS << "  };\n";      // End of register descriptors...
707
708
709  // Calculate the mapping of subregister+index pairs to physical registers.
710  // This will also create further anonymous indexes.
711  unsigned NamedIndices = RegBank.getNumNamedIndices();
712
713  // Emit SubRegIndex names, skipping 0
714  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
715  OS << "\n  static const char *const " << TargetName
716     << "SubRegIndexTable[] = { \"";
717  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
718    OS << SubRegIndices[i]->getName();
719    if (i+1 != e)
720      OS << "\", \"";
721  }
722  OS << "\" };\n\n";
723
724  // Emit names of the anonymus subreg indexes.
725  if (SubRegIndices.size() > NamedIndices) {
726    OS << "  enum {";
727    for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
728      OS << "\n    " << SubRegIndices[i]->getName() << " = " << i+1;
729      if (i+1 != e)
730        OS << ',';
731    }
732    OS << "\n  };\n\n";
733  }
734  OS << "\n";
735
736  std::string ClassName = Target.getName() + "GenRegisterInfo";
737
738  // Emit the subregister + index mapping function based on the information
739  // calculated above.
740  OS << "unsigned " << ClassName
741     << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
742     << "  switch (RegNo) {\n"
743     << "  default:\n    return 0;\n";
744  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
745    const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
746    if (SRM.empty())
747      continue;
748    OS << "  case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
749    OS << "    switch (Index) {\n";
750    OS << "    default: return 0;\n";
751    for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
752         ie = SRM.end(); ii != ie; ++ii)
753      OS << "    case " << ii->first->getQualifiedName()
754         << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
755    OS << "    };\n" << "    break;\n";
756  }
757  OS << "  };\n";
758  OS << "  return 0;\n";
759  OS << "}\n\n";
760
761  OS << "unsigned " << ClassName
762     << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
763     << "  switch (RegNo) {\n"
764     << "  default:\n    return 0;\n";
765   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
766     const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
767     if (SRM.empty())
768       continue;
769    OS << "  case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
770    for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
771         ie = SRM.end(); ii != ie; ++ii)
772      OS << "    if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
773         << ")  return " << ii->first->getQualifiedName() << ";\n";
774    OS << "    return 0;\n";
775  }
776  OS << "  };\n";
777  OS << "  return 0;\n";
778  OS << "}\n\n";
779
780  // Emit composeSubRegIndices
781  OS << "unsigned " << ClassName
782     << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
783     << "  switch (IdxA) {\n"
784     << "  default:\n    return IdxB;\n";
785  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
786    bool Open = false;
787    for (unsigned j = 0; j != e; ++j) {
788      if (CodeGenSubRegIndex *Comp =
789            SubRegIndices[i]->compose(SubRegIndices[j])) {
790        if (!Open) {
791          OS << "  case " << SubRegIndices[i]->getQualifiedName()
792             << ": switch(IdxB) {\n    default: return IdxB;\n";
793          Open = true;
794        }
795        OS << "    case " << SubRegIndices[j]->getQualifiedName()
796           << ": return " << Comp->getQualifiedName() << ";\n";
797      }
798    }
799    if (Open)
800      OS << "    }\n";
801  }
802  OS << "  }\n}\n\n";
803
804  // Emit getSubClassWithSubReg.
805  OS << "const TargetRegisterClass *" << ClassName
806     << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
807        " const {\n";
808  if (SubRegIndices.empty()) {
809    OS << "  assert(Idx == 0 && \"Target has no sub-registers\");\n"
810       << "  return RC;\n";
811  } else {
812    // Use the smallest type that can hold a regclass ID with room for a
813    // sentinel.
814    if (RegisterClasses.size() < UINT8_MAX)
815      OS << "  static const uint8_t Table[";
816    else if (RegisterClasses.size() < UINT16_MAX)
817      OS << "  static const uint16_t Table[";
818    else
819      throw "Too many register classes.";
820    OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
821    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
822      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
823      OS << "    {\t// " << RC.getName() << "\n";
824      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
825        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
826        if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
827          OS << "      " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
828             << " -> " << SRC->getName() << "\n";
829        else
830          OS << "      0,\t// " << Idx->getName() << "\n";
831      }
832      OS << "    },\n";
833    }
834    OS << "  };\n  assert(RC && \"Missing regclass\");\n"
835       << "  if (!Idx) return RC;\n  --Idx;\n"
836       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
837       << "  unsigned TV = Table[RC->getID()][Idx];\n"
838       << "  return TV ? getRegClass(TV - 1) : 0;\n";
839  }
840  OS << "}\n\n";
841
842  // Emit getMatchingSuperRegClass.
843  OS << "const TargetRegisterClass *" << ClassName
844     << "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
845        " const TargetRegisterClass *B, unsigned Idx) const {\n";
846  if (SubRegIndices.empty()) {
847    OS << "  llvm_unreachable(\"Target has no sub-registers\");\n";
848  } else {
849    // We need to find the largest sub-class of A such that every register has
850    // an Idx sub-register in B.  Map (B, Idx) to a bit-vector of
851    // super-register classes that map into B. Then compute the largest common
852    // sub-class with A by taking advantage of the register class ordering,
853    // like getCommonSubClass().
854
855    // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
856    // the number of 32-bit words required to represent all register classes.
857    const unsigned BVWords = (RegisterClasses.size()+31)/32;
858    BitVector BV(RegisterClasses.size());
859
860    OS << "  static const unsigned Table[" << RegisterClasses.size()
861       << "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
862    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
863      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
864      OS << "    {\t// " << RC.getName() << "\n";
865      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
866        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
867        BV.reset();
868        RC.getSuperRegClasses(Idx, BV);
869        OS << "      { ";
870        printBitVectorAsHex(OS, BV, 32);
871        OS << "},\t// " << Idx->getName() << '\n';
872      }
873      OS << "    },\n";
874    }
875    OS << "  };\n  assert(A && B && \"Missing regclass\");\n"
876       << "  --Idx;\n"
877       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
878       << "  const unsigned *TV = Table[B->getID()][Idx];\n"
879       << "  const unsigned *SC = A->getSubClassMask();\n"
880       << "  for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
881       << "    if (unsigned Common = TV[i] & SC[i])\n"
882       << "      return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
883       << "  return 0;\n";
884  }
885  OS << "}\n\n";
886
887  // Emit the constructor of the class...
888  OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
889  OS << "extern const unsigned " << TargetName << "RegOverlaps[];\n";
890  OS << "extern const unsigned " << TargetName << "SubRegsSet[];\n";
891  OS << "extern const unsigned " << TargetName << "SuperRegsSet[];\n";
892
893  OS << ClassName << "::" << ClassName
894     << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
895     << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
896     << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
897     << "                 " << TargetName << "SubRegIndexTable) {\n"
898     << "  InitMCRegisterInfo(" << TargetName << "RegDesc, "
899     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
900     << RegisterClasses.size() << ", " << TargetName << "RegOverlaps, "
901     << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet);\n\n";
902
903  EmitRegMapping(OS, Regs, true);
904
905  OS << "}\n\n";
906
907
908  // Emit CalleeSavedRegs information.
909  std::vector<Record*> CSRSets =
910    Records.getAllDerivedDefinitions("CalleeSavedRegs");
911  for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
912    Record *CSRSet = CSRSets[i];
913    const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
914    assert(Regs && "Cannot expand CalleeSavedRegs instance");
915
916    // Emit the *_SaveList list of callee-saved registers.
917    OS << "static const unsigned " << CSRSet->getName()
918       << "_SaveList[] = { ";
919    for (unsigned r = 0, re = Regs->size(); r != re; ++r)
920      OS << getQualifiedName((*Regs)[r]) << ", ";
921    OS << "0 };\n";
922
923    // Emit the *_RegMask bit mask of call-preserved registers.
924    OS << "static const uint32_t " << CSRSet->getName()
925       << "_RegMask[] = { ";
926    printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
927    OS << "};\n";
928  }
929  OS << "\n\n";
930
931  OS << "} // End llvm namespace \n";
932  OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
933}
934
935void RegisterInfoEmitter::run(raw_ostream &OS) {
936  CodeGenTarget Target(Records);
937  CodeGenRegBank &RegBank = Target.getRegBank();
938  RegBank.computeDerivedInfo();
939
940  runEnums(OS, Target, RegBank);
941  runMCDesc(OS, Target, RegBank);
942  runTargetHeader(OS, Target, RegBank);
943  runTargetDesc(OS, Target, RegBank);
944}
945