RegisterInfoEmitter.cpp revision ccc8d3ba06408feff0ca6e58973c20d15010e3fc 
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of a target
11// register file for a code generator.  It uses instances of the Register,
12// RegisterAliases, and RegisterClass classes to gather this information.
13//
14//===----------------------------------------------------------------------===//
15
16#include "RegisterInfoEmitter.h"
17#include "CodeGenTarget.h"
18#include "CodeGenRegisters.h"
19#include "llvm/TableGen/Record.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/Support/Format.h"
24#include <algorithm>
25#include <set>
26using namespace llvm;
27
28// runEnums - Print out enum values for all of the registers.
29void
30RegisterInfoEmitter::runEnums(raw_ostream &OS,
31                              CodeGenTarget &Target, CodeGenRegBank &Bank) {
32  const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33
34  std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
35
36  EmitSourceFileHeader("Target Register Enum Values", OS);
37
38  OS << "\n#ifdef GET_REGINFO_ENUM\n";
39  OS << "#undef GET_REGINFO_ENUM\n";
40
41  OS << "namespace llvm {\n\n";
42
43  OS << "class MCRegisterClass;\n"
44     << "extern const MCRegisterClass " << Namespace
45     << "MCRegisterClasses[];\n\n";
46
47  if (!Namespace.empty())
48    OS << "namespace " << Namespace << " {\n";
49  OS << "enum {\n  NoRegister,\n";
50
51  for (unsigned i = 0, e = Registers.size(); i != e; ++i)
52    OS << "  " << Registers[i]->getName() << " = " <<
53      Registers[i]->EnumValue << ",\n";
54  assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
55         "Register enum value mismatch!");
56  OS << "  NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
57  OS << "};\n";
58  if (!Namespace.empty())
59    OS << "}\n";
60
61  ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
62  if (!RegisterClasses.empty()) {
63    OS << "\n// Register classes\n";
64    if (!Namespace.empty())
65      OS << "namespace " << Namespace << " {\n";
66    OS << "enum {\n";
67    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
68      if (i) OS << ",\n";
69      OS << "  " << RegisterClasses[i]->getName() << "RegClassID";
70      OS << " = " << i;
71    }
72    OS << "\n  };\n";
73    if (!Namespace.empty())
74      OS << "}\n";
75  }
76
77  const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
78  // If the only definition is the default NoRegAltName, we don't need to
79  // emit anything.
80  if (RegAltNameIndices.size() > 1) {
81    OS << "\n// Register alternate name indices\n";
82    if (!Namespace.empty())
83      OS << "namespace " << Namespace << " {\n";
84    OS << "enum {\n";
85    for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
86      OS << "  " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
87    OS << "  NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
88    OS << "};\n";
89    if (!Namespace.empty())
90      OS << "}\n";
91  }
92
93  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
94  if (!SubRegIndices.empty()) {
95    OS << "\n// Subregister indices\n";
96    std::string Namespace =
97      SubRegIndices[0]->getNamespace();
98    if (!Namespace.empty())
99      OS << "namespace " << Namespace << " {\n";
100    OS << "enum {\n  NoSubRegister,\n";
101    for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
102      OS << "  " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
103    OS << "  NUM_TARGET_NAMED_SUBREGS\n};\n";
104    if (!Namespace.empty())
105      OS << "}\n";
106  }
107
108  OS << "} // End llvm namespace \n";
109  OS << "#endif // GET_REGINFO_ENUM\n\n";
110}
111
112void
113RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
114                                    const std::vector<CodeGenRegister*> &Regs,
115                                    bool isCtor) {
116
117  // Collect all information about dwarf register numbers
118  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
119  DwarfRegNumsMapTy DwarfRegNums;
120
121  // First, just pull all provided information to the map
122  unsigned maxLength = 0;
123  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
124    Record *Reg = Regs[i]->TheDef;
125    std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
126    maxLength = std::max((size_t)maxLength, RegNums.size());
127    if (DwarfRegNums.count(Reg))
128      errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
129             << "specified multiple times\n";
130    DwarfRegNums[Reg] = RegNums;
131  }
132
133  if (!maxLength)
134    return;
135
136  // Now we know maximal length of number list. Append -1's, where needed
137  for (DwarfRegNumsMapTy::iterator
138       I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
139    for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
140      I->second.push_back(-1);
141
142  // Emit reverse information about the dwarf register numbers.
143  for (unsigned j = 0; j < 2; ++j) {
144    OS << "  switch (";
145    if (j == 0)
146      OS << "DwarfFlavour";
147    else
148      OS << "EHFlavour";
149    OS << ") {\n"
150     << "  default:\n"
151     << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
152
153    for (unsigned i = 0, e = maxLength; i != e; ++i) {
154      OS << "  case " << i << ":\n";
155      for (DwarfRegNumsMapTy::iterator
156             I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
157        int DwarfRegNo = I->second[i];
158        if (DwarfRegNo < 0)
159          continue;
160        OS << "    ";
161        if (!isCtor)
162          OS << "RI->";
163        OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
164           << getQualifiedName(I->first) << ", ";
165        if (j == 0)
166          OS << "false";
167        else
168          OS << "true";
169        OS << " );\n";
170      }
171      OS << "    break;\n";
172    }
173    OS << "  }\n";
174  }
175
176  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
177    Record *Reg = Regs[i]->TheDef;
178    const RecordVal *V = Reg->getValue("DwarfAlias");
179    if (!V || !V->getValue())
180      continue;
181
182    DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
183    Record *Alias = DI->getDef();
184    DwarfRegNums[Reg] = DwarfRegNums[Alias];
185  }
186
187  // Emit information about the dwarf register numbers.
188  for (unsigned j = 0; j < 2; ++j) {
189    OS << "  switch (";
190    if (j == 0)
191      OS << "DwarfFlavour";
192    else
193      OS << "EHFlavour";
194    OS << ") {\n"
195       << "  default:\n"
196       << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
197
198    for (unsigned i = 0, e = maxLength; i != e; ++i) {
199      OS << "  case " << i << ":\n";
200      // Sort by name to get a stable order.
201      for (DwarfRegNumsMapTy::iterator
202             I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
203        int RegNo = I->second[i];
204        if (RegNo == -1) // -1 is the default value, don't emit a mapping.
205          continue;
206
207        OS << "    ";
208        if (!isCtor)
209          OS << "RI->";
210        OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
211           <<  RegNo << ", ";
212        if (j == 0)
213          OS << "false";
214        else
215          OS << "true";
216        OS << " );\n";
217      }
218      OS << "    break;\n";
219    }
220    OS << "  }\n";
221  }
222}
223
224// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
225// Width is the number of bits per hex number.
226static void printBitVectorAsHex(raw_ostream &OS,
227                                const BitVector &Bits,
228                                unsigned Width) {
229  assert(Width <= 32 && "Width too large");
230  unsigned Digits = (Width + 3) / 4;
231  for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
232    unsigned Value = 0;
233    for (unsigned j = 0; j != Width && i + j != e; ++j)
234      Value |= Bits.test(i + j) << j;
235    OS << format("0x%0*x, ", Digits, Value);
236  }
237}
238
239// Helper to emit a set of bits into a constant byte array.
240class BitVectorEmitter {
241  BitVector Values;
242public:
243  void add(unsigned v) {
244    if (v >= Values.size())
245      Values.resize(((v/8)+1)*8); // Round up to the next byte.
246    Values[v] = true;
247  }
248
249  void print(raw_ostream &OS) {
250    printBitVectorAsHex(OS, Values, 8);
251  }
252};
253
254//
255// runMCDesc - Print out MC register descriptions.
256//
257void
258RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
259                               CodeGenRegBank &RegBank) {
260  EmitSourceFileHeader("MC Register Information", OS);
261
262  OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
263  OS << "#undef GET_REGINFO_MC_DESC\n";
264
265  std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
266  RegBank.computeOverlaps(Overlaps);
267
268  OS << "namespace llvm {\n\n";
269
270  const std::string &TargetName = Target.getName();
271
272  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
273
274  OS << "extern const unsigned " << TargetName << "RegOverlaps[] = {\n";
275
276  // Emit an overlap list for all registers.
277  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
278    const CodeGenRegister *Reg = Regs[i];
279    const CodeGenRegister::Set &O = Overlaps[Reg];
280    // Move Reg to the front so TRI::getAliasSet can share the list.
281    OS << "  /* " << Reg->getName() << "_Overlaps */ "
282       << getQualifiedName(Reg->TheDef) << ", ";
283    for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
284         I != E; ++I)
285      if (*I != Reg)
286        OS << getQualifiedName((*I)->TheDef) << ", ";
287    OS << "0,\n";
288  }
289  OS << "};\n\n";
290
291  OS << "extern const unsigned " << TargetName << "SubRegsSet[] = {\n";
292  // Emit the empty sub-registers list
293  OS << "  /* Empty_SubRegsSet */ 0,\n";
294  // Loop over all of the registers which have sub-registers, emitting the
295  // sub-registers list to memory.
296  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
297    const CodeGenRegister &Reg = *Regs[i];
298    if (Reg.getSubRegs().empty())
299     continue;
300    // getSubRegs() orders by SubRegIndex. We want a topological order.
301    SetVector<CodeGenRegister*> SR;
302    Reg.addSubRegsPreOrder(SR, RegBank);
303    OS << "  /* " << Reg.getName() << "_SubRegsSet */ ";
304    for (unsigned j = 0, je = SR.size(); j != je; ++j)
305      OS << getQualifiedName(SR[j]->TheDef) << ", ";
306    OS << "0,\n";
307  }
308  OS << "};\n\n";
309
310  OS << "extern const unsigned " << TargetName << "SuperRegsSet[] = {\n";
311  // Emit the empty super-registers list
312  OS << "  /* Empty_SuperRegsSet */ 0,\n";
313  // Loop over all of the registers which have super-registers, emitting the
314  // super-registers list to memory.
315  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
316    const CodeGenRegister &Reg = *Regs[i];
317    const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
318    if (SR.empty())
319      continue;
320    OS << "  /* " << Reg.getName() << "_SuperRegsSet */ ";
321    for (unsigned j = 0, je = SR.size(); j != je; ++j)
322      OS << getQualifiedName(SR[j]->TheDef) << ", ";
323    OS << "0,\n";
324  }
325  OS << "};\n\n";
326
327  OS << "extern const MCRegisterDesc " << TargetName
328     << "RegDesc[] = { // Descriptors\n";
329  OS << "  { \"NOREG\", 0, 0, 0 },\n";
330
331  // Now that register alias and sub-registers sets have been emitted, emit the
332  // register descriptors now.
333  unsigned OverlapsIndex = 0;
334  unsigned SubRegIndex = 1; // skip 1 for empty set
335  unsigned SuperRegIndex = 1; // skip 1 for empty set
336  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
337    const CodeGenRegister *Reg = Regs[i];
338    OS << "  { \"";
339    OS << Reg->getName() << "\", /* " << Reg->getName() << "_Overlaps */ "
340       << OverlapsIndex << ", ";
341    OverlapsIndex += Overlaps[Reg].size() + 1;
342    if (!Reg->getSubRegs().empty()) {
343      OS << "/* " << Reg->getName() << "_SubRegsSet */ " << SubRegIndex
344         << ", ";
345      // FIXME not very nice to recalculate this
346      SetVector<CodeGenRegister*> SR;
347      Reg->addSubRegsPreOrder(SR, RegBank);
348      SubRegIndex += SR.size() + 1;
349    } else
350      OS << "/* Empty_SubRegsSet */ 0, ";
351    if (!Reg->getSuperRegs().empty()) {
352      OS << "/* " << Reg->getName() << "_SuperRegsSet */ " << SuperRegIndex;
353      SuperRegIndex += Reg->getSuperRegs().size() + 1;
354    } else
355      OS << "/* Empty_SuperRegsSet */ 0";
356    OS << " },\n";
357  }
358  OS << "};\n\n";      // End of register descriptors...
359
360  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
361
362  // Loop over all of the register classes... emitting each one.
363  OS << "namespace {     // Register classes...\n";
364
365  // Emit the register enum value arrays for each RegisterClass
366  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
367    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
368    ArrayRef<Record*> Order = RC.getOrder();
369
370    // Give the register class a legal C name if it's anonymous.
371    std::string Name = RC.getName();
372
373    // Emit the register list now.
374    OS << "  // " << Name << " Register Class...\n"
375       << "  const unsigned " << Name
376       << "[] = {\n    ";
377    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
378      Record *Reg = Order[i];
379      OS << getQualifiedName(Reg) << ", ";
380    }
381    OS << "\n  };\n\n";
382
383    OS << "  // " << Name << " Bit set.\n"
384       << "  const unsigned char " << Name
385       << "Bits[] = {\n    ";
386    BitVectorEmitter BVE;
387    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
388      Record *Reg = Order[i];
389      BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
390    }
391    BVE.print(OS);
392    OS << "\n  };\n\n";
393
394  }
395  OS << "}\n\n";
396
397  OS << "extern const MCRegisterClass " << TargetName
398     << "MCRegisterClasses[] = {\n";
399
400  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
401    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
402    OS << "  { " << RC.getQualifiedName() + "RegClassID" << ", "
403       << '\"' << RC.getName() << "\", "
404       << RC.SpillSize/8 << ", "
405       << RC.SpillAlignment/8 << ", "
406       << RC.CopyCost << ", "
407       << RC.Allocatable << ", "
408       << RC.getName() << ", " << RC.getName() << "Bits, "
409       << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits) },\n";
410  }
411
412  OS << "};\n\n";
413
414  // MCRegisterInfo initialization routine.
415  OS << "static inline void Init" << TargetName
416     << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
417     << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
418  OS << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
419     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
420     << RegisterClasses.size() << ", " << TargetName << "RegOverlaps, "
421     << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet);\n\n";
422
423  EmitRegMapping(OS, Regs, false);
424
425  OS << "}\n\n";
426
427
428  OS << "} // End llvm namespace \n";
429  OS << "#endif // GET_REGINFO_MC_DESC\n\n";
430}
431
432void
433RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
434                                     CodeGenRegBank &RegBank) {
435  EmitSourceFileHeader("Register Information Header Fragment", OS);
436
437  OS << "\n#ifdef GET_REGINFO_HEADER\n";
438  OS << "#undef GET_REGINFO_HEADER\n";
439
440  const std::string &TargetName = Target.getName();
441  std::string ClassName = TargetName + "GenRegisterInfo";
442
443  OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
444  OS << "#include <string>\n\n";
445
446  OS << "namespace llvm {\n\n";
447
448  OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
449     << "  explicit " << ClassName
450     << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
451     << "  virtual bool needsStackRealignment(const MachineFunction &) const\n"
452     << "     { return false; }\n"
453     << "  unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
454     << "  unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
455     << "  unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
456     << "  const TargetRegisterClass *"
457        "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
458     << "  const TargetRegisterClass *getMatchingSuperRegClass("
459        "const TargetRegisterClass*, const TargetRegisterClass*, "
460        "unsigned) const;\n"
461     << "};\n\n";
462
463  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
464
465  if (!RegisterClasses.empty()) {
466    OS << "namespace " << RegisterClasses[0]->Namespace
467       << " { // Register classes\n";
468
469    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
470      const CodeGenRegisterClass &RC = *RegisterClasses[i];
471      const std::string &Name = RC.getName();
472
473      // Output the extern for the instance.
474      OS << "  extern const TargetRegisterClass " << Name << "RegClass;\n";
475      // Output the extern for the pointer to the instance (should remove).
476      OS << "  static const TargetRegisterClass * const " << Name
477         << "RegisterClass = &" << Name << "RegClass;\n";
478    }
479    OS << "} // end of namespace " << TargetName << "\n\n";
480  }
481  OS << "} // End llvm namespace \n";
482  OS << "#endif // GET_REGINFO_HEADER\n\n";
483}
484
485//
486// runTargetDesc - Output the target register and register file descriptions.
487//
488void
489RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
490                                   CodeGenRegBank &RegBank){
491  EmitSourceFileHeader("Target Register and Register Classes Information", OS);
492
493  OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
494  OS << "#undef GET_REGINFO_TARGET_DESC\n";
495
496  OS << "namespace llvm {\n\n";
497
498  // Get access to MCRegisterClass data.
499  OS << "extern const MCRegisterClass " << Target.getName()
500     << "MCRegisterClasses[];\n";
501
502  // Start out by emitting each of the register classes.
503  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
504
505  // Collect all registers belonging to any allocatable class.
506  std::set<Record*> AllocatableRegs;
507
508  // Collect allocatable registers.
509  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
510    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
511    ArrayRef<Record*> Order = RC.getOrder();
512
513    if (RC.Allocatable)
514      AllocatableRegs.insert(Order.begin(), Order.end());
515  }
516
517  OS << "namespace {     // Register classes...\n";
518
519  // Emit the ValueType arrays for each RegisterClass
520  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
521    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
522
523    // Give the register class a legal C name if it's anonymous.
524    std::string Name = RC.getName() + "VTs";
525
526    // Emit the register list now.
527    OS << "  // " << Name
528       << " Register Class Value Types...\n"
529       << "  const MVT::SimpleValueType " << Name
530       << "[] = {\n    ";
531    for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
532      OS << getEnumName(RC.VTs[i]) << ", ";
533    OS << "MVT::Other\n  };\n\n";
534  }
535  OS << "}  // end anonymous namespace\n\n";
536
537  // Now that all of the structs have been emitted, emit the instances.
538  if (!RegisterClasses.empty()) {
539    std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
540
541    OS << "\nstatic const TargetRegisterClass *const "
542       << "NullRegClasses[] = { NULL };\n\n";
543
544    unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
545
546    if (NumSubRegIndices) {
547      // Compute the super-register classes for each RegisterClass
548      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
549        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
550        for (DenseMap<Record*,Record*>::const_iterator
551             i = RC.SubRegClasses.begin(),
552             e = RC.SubRegClasses.end(); i != e; ++i) {
553          // Find the register class number of i->second for SuperRegClassMap.
554          const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
555          assert(RC2 && "Invalid register class in SubRegClasses");
556          SuperRegClassMap[RC2->EnumValue].insert(rc);
557        }
558      }
559
560      // Emit the super-register classes for each RegisterClass
561      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
562        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
563
564        // Give the register class a legal C name if it's anonymous.
565        std::string Name = RC.getName();
566
567        OS << "// " << Name
568           << " Super-register Classes...\n"
569           << "static const TargetRegisterClass *const "
570           << Name << "SuperRegClasses[] = {\n  ";
571
572        bool Empty = true;
573        std::map<unsigned, std::set<unsigned> >::iterator I =
574          SuperRegClassMap.find(rc);
575        if (I != SuperRegClassMap.end()) {
576          for (std::set<unsigned>::iterator II = I->second.begin(),
577                 EE = I->second.end(); II != EE; ++II) {
578            const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
579            if (!Empty)
580              OS << ", ";
581            OS << "&" << RC2.getQualifiedName() << "RegClass";
582            Empty = false;
583          }
584        }
585
586        OS << (!Empty ? ", " : "") << "NULL";
587        OS << "\n};\n\n";
588      }
589    }
590
591    // Emit the sub-classes array for each RegisterClass
592    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
593      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
594
595      // Give the register class a legal C name if it's anonymous.
596      std::string Name = RC.getName();
597
598      OS << "static const unsigned " << Name << "SubclassMask[] = {\n  ";
599      printBitVectorAsHex(OS, RC.getSubClasses(), 32);
600      OS << "\n};\n\n";
601    }
602
603    // Emit NULL terminated super-class lists.
604    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
605      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
606      ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
607
608      // Skip classes without supers.  We can reuse NullRegClasses.
609      if (Supers.empty())
610        continue;
611
612      OS << "static const TargetRegisterClass *const "
613         << RC.getName() << "Superclasses[] = {\n";
614      for (unsigned i = 0; i != Supers.size(); ++i)
615        OS << "  &" << Supers[i]->getQualifiedName() << "RegClass,\n";
616      OS << "  NULL\n};\n\n";
617    }
618
619    // Emit methods.
620    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
621      const CodeGenRegisterClass &RC = *RegisterClasses[i];
622      if (!RC.AltOrderSelect.empty()) {
623        OS << "\nstatic inline unsigned " << RC.getName()
624           << "AltOrderSelect(const MachineFunction &MF) {"
625           << RC.AltOrderSelect << "}\n\n"
626           << "static ArrayRef<unsigned> " << RC.getName()
627           << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
628        for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
629          ArrayRef<Record*> Elems = RC.getOrder(oi);
630          if (!Elems.empty()) {
631            OS << "  static const unsigned AltOrder" << oi << "[] = {";
632            for (unsigned elem = 0; elem != Elems.size(); ++elem)
633              OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
634            OS << " };\n";
635          }
636        }
637        OS << "  const MCRegisterClass &MCR = " << Target.getName()
638           << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
639           << "  const ArrayRef<unsigned> Order[] = {\n"
640           << "    makeArrayRef(MCR.begin(), MCR.getNumRegs()";
641        for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
642          if (RC.getOrder(oi).empty())
643            OS << "),\n    ArrayRef<unsigned>(";
644          else
645            OS << "),\n    makeArrayRef(AltOrder" << oi;
646        OS << ")\n  };\n  const unsigned Select = " << RC.getName()
647           << "AltOrderSelect(MF);\n  assert(Select < " << RC.getNumOrders()
648           << ");\n  return Order[Select];\n}\n";
649        }
650    }
651
652    // Now emit the actual value-initialized register class instances.
653    OS << "namespace " << RegisterClasses[0]->Namespace
654       << " {   // Register class instances\n";
655
656    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
657      const CodeGenRegisterClass &RC = *RegisterClasses[i];
658      OS << "  extern const TargetRegisterClass "
659         << RegisterClasses[i]->getName() << "RegClass = {\n    "
660         << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
661         << "RegClassID],\n    "
662         << RC.getName() << "VTs,\n    "
663         << RC.getName() << "SubclassMask,\n    ";
664      if (RC.getSuperClasses().empty())
665        OS << "NullRegClasses,\n    ";
666      else
667        OS << RC.getName() << "Superclasses,\n    ";
668      OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
669         << "RegClasses,\n    ";
670      if (RC.AltOrderSelect.empty())
671        OS << "0\n";
672      else
673        OS << RC.getName() << "GetRawAllocationOrder\n";
674      OS << "  };\n\n";
675    }
676
677    OS << "}\n";
678  }
679
680  OS << "\nnamespace {\n";
681  OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
682  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
683    OS << "    &" << RegisterClasses[i]->getQualifiedName()
684       << "RegClass,\n";
685  OS << "  };\n";
686  OS << "}\n";       // End of anonymous namespace...
687
688  // Emit extra information about registers.
689  const std::string &TargetName = Target.getName();
690  OS << "\n  static const TargetRegisterInfoDesc "
691     << TargetName << "RegInfoDesc[] = "
692     << "{ // Extra Descriptors\n";
693  OS << "    { 0, 0 },\n";
694
695  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
696  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
697    const CodeGenRegister &Reg = *Regs[i];
698    OS << "    { ";
699    OS << Reg.CostPerUse << ", "
700       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
701  }
702  OS << "  };\n";      // End of register descriptors...
703
704
705  // Calculate the mapping of subregister+index pairs to physical registers.
706  // This will also create further anonymous indices.
707  unsigned NamedIndices = RegBank.getNumNamedIndices();
708
709  // Emit SubRegIndex names, skipping 0
710  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
711  OS << "\n  static const char *const " << TargetName
712     << "SubRegIndexTable[] = { \"";
713  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
714    OS << SubRegIndices[i]->getName();
715    if (i+1 != e)
716      OS << "\", \"";
717  }
718  OS << "\" };\n\n";
719
720  // Emit names of the anonymous subreg indices.
721  if (SubRegIndices.size() > NamedIndices) {
722    OS << "  enum {";
723    for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
724      OS << "\n    " << SubRegIndices[i]->getName() << " = " << i+1;
725      if (i+1 != e)
726        OS << ',';
727    }
728    OS << "\n  };\n\n";
729  }
730  OS << "\n";
731
732  std::string ClassName = Target.getName() + "GenRegisterInfo";
733
734  // Emit the data table for getSubReg().
735  if (SubRegIndices.size()) {
736    OS << "static const " << getMinimalTypeForRange(Regs.size()) << ' '
737       << TargetName << "SubRegTable[][" << SubRegIndices.size() << "] = {\n";
738    for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
739      const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
740      OS << "  /* " << Regs[i]->TheDef->getName() << " */\n";
741      if (SRM.empty()) {
742        OS << "  {0},\n";
743        continue;
744      }
745      OS << "  {";
746      for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
747        // FIXME: We really should keep this to 80 columns...
748        CodeGenRegister::SubRegMap::const_iterator SubReg =
749          SRM.find(SubRegIndices[j]);
750        if (SubReg != SRM.end())
751          OS << getQualifiedName(SubReg->second->TheDef);
752        else
753          OS << "0";
754        if (j != je - 1)
755          OS << ", ";
756      }
757      OS << "}" << (i != e ? "," : "") << "\n";
758    }
759    OS << "};\n\n";
760  }
761
762  // Emit the subregister + index mapping function based on the information
763  // calculated above.
764  OS << "unsigned " << ClassName
765     << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
766     << "  assert(RegNo > 0 && Index > 0 && \"invalid subreg query!\");\n";
767  if (SubRegIndices.size())
768     OS << "  return " << TargetName << "SubRegTable[RegNo - 1][Index - 1];\n"
769        << "}\n\n";
770  else
771    OS << "  return 0;\n}\n\n";
772
773  OS << "unsigned " << ClassName
774     << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n";
775  if (SubRegIndices.size()) {
776    OS << "  for (unsigned I = 0; I != array_lengthof("
777       << TargetName << "SubRegTable[0]); ++I)\n"
778       << "    if (" << TargetName << "SubRegTable[RegNo - 1][I] == SubRegNo)\n"
779       << "      return I + 1;\n";
780  }
781  OS << "  return 0;\n";
782  OS << "}\n\n";
783
784  // Emit composeSubRegIndices
785  OS << "unsigned " << ClassName
786     << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
787     << "  switch (IdxA) {\n"
788     << "  default:\n    return IdxB;\n";
789  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
790    bool Open = false;
791    for (unsigned j = 0; j != e; ++j) {
792      if (CodeGenSubRegIndex *Comp =
793            SubRegIndices[i]->compose(SubRegIndices[j])) {
794        if (!Open) {
795          OS << "  case " << SubRegIndices[i]->getQualifiedName()
796             << ": switch(IdxB) {\n    default: return IdxB;\n";
797          Open = true;
798        }
799        OS << "    case " << SubRegIndices[j]->getQualifiedName()
800           << ": return " << Comp->getQualifiedName() << ";\n";
801      }
802    }
803    if (Open)
804      OS << "    }\n";
805  }
806  OS << "  }\n}\n\n";
807
808  // Emit getSubClassWithSubReg.
809  OS << "const TargetRegisterClass *" << ClassName
810     << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
811        " const {\n";
812  if (SubRegIndices.empty()) {
813    OS << "  assert(Idx == 0 && \"Target has no sub-registers\");\n"
814       << "  return RC;\n";
815  } else {
816    // Use the smallest type that can hold a regclass ID with room for a
817    // sentinel.
818    if (RegisterClasses.size() < UINT8_MAX)
819      OS << "  static const uint8_t Table[";
820    else if (RegisterClasses.size() < UINT16_MAX)
821      OS << "  static const uint16_t Table[";
822    else
823      throw "Too many register classes.";
824    OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
825    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
826      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
827      OS << "    {\t// " << RC.getName() << "\n";
828      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
829        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
830        if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
831          OS << "      " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
832             << " -> " << SRC->getName() << "\n";
833        else
834          OS << "      0,\t// " << Idx->getName() << "\n";
835      }
836      OS << "    },\n";
837    }
838    OS << "  };\n  assert(RC && \"Missing regclass\");\n"
839       << "  if (!Idx) return RC;\n  --Idx;\n"
840       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
841       << "  unsigned TV = Table[RC->getID()][Idx];\n"
842       << "  return TV ? getRegClass(TV - 1) : 0;\n";
843  }
844  OS << "}\n\n";
845
846  // Emit getMatchingSuperRegClass.
847  OS << "const TargetRegisterClass *" << ClassName
848     << "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
849        " const TargetRegisterClass *B, unsigned Idx) const {\n";
850  if (SubRegIndices.empty()) {
851    OS << "  llvm_unreachable(\"Target has no sub-registers\");\n";
852  } else {
853    // We need to find the largest sub-class of A such that every register has
854    // an Idx sub-register in B.  Map (B, Idx) to a bit-vector of
855    // super-register classes that map into B. Then compute the largest common
856    // sub-class with A by taking advantage of the register class ordering,
857    // like getCommonSubClass().
858
859    // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
860    // the number of 32-bit words required to represent all register classes.
861    const unsigned BVWords = (RegisterClasses.size()+31)/32;
862    BitVector BV(RegisterClasses.size());
863
864    OS << "  static const unsigned Table[" << RegisterClasses.size()
865       << "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
866    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
867      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
868      OS << "    {\t// " << RC.getName() << "\n";
869      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
870        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
871        BV.reset();
872        RC.getSuperRegClasses(Idx, BV);
873        OS << "      { ";
874        printBitVectorAsHex(OS, BV, 32);
875        OS << "},\t// " << Idx->getName() << '\n';
876      }
877      OS << "    },\n";
878    }
879    OS << "  };\n  assert(A && B && \"Missing regclass\");\n"
880       << "  --Idx;\n"
881       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
882       << "  const unsigned *TV = Table[B->getID()][Idx];\n"
883       << "  const unsigned *SC = A->getSubClassMask();\n"
884       << "  for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
885       << "    if (unsigned Common = TV[i] & SC[i])\n"
886       << "      return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
887       << "  return 0;\n";
888  }
889  OS << "}\n\n";
890
891  // Emit the constructor of the class...
892  OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
893  OS << "extern const unsigned " << TargetName << "RegOverlaps[];\n";
894  OS << "extern const unsigned " << TargetName << "SubRegsSet[];\n";
895  OS << "extern const unsigned " << TargetName << "SuperRegsSet[];\n";
896
897  OS << ClassName << "::" << ClassName
898     << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
899     << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
900     << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
901     << "                 " << TargetName << "SubRegIndexTable) {\n"
902     << "  InitMCRegisterInfo(" << TargetName << "RegDesc, "
903     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
904     << RegisterClasses.size() << ", " << TargetName << "RegOverlaps, "
905     << TargetName << "SubRegsSet, " << TargetName << "SuperRegsSet);\n\n";
906
907  EmitRegMapping(OS, Regs, true);
908
909  OS << "}\n\n";
910
911
912  // Emit CalleeSavedRegs information.
913  std::vector<Record*> CSRSets =
914    Records.getAllDerivedDefinitions("CalleeSavedRegs");
915  for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
916    Record *CSRSet = CSRSets[i];
917    const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
918    assert(Regs && "Cannot expand CalleeSavedRegs instance");
919
920    // Emit the *_SaveList list of callee-saved registers.
921    OS << "static const unsigned " << CSRSet->getName()
922       << "_SaveList[] = { ";
923    for (unsigned r = 0, re = Regs->size(); r != re; ++r)
924      OS << getQualifiedName((*Regs)[r]) << ", ";
925    OS << "0 };\n";
926
927    // Emit the *_RegMask bit mask of call-preserved registers.
928    OS << "static const uint32_t " << CSRSet->getName()
929       << "_RegMask[] = { ";
930    printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
931    OS << "};\n";
932  }
933  OS << "\n\n";
934
935  OS << "} // End llvm namespace \n";
936  OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
937}
938
939void RegisterInfoEmitter::run(raw_ostream &OS) {
940  CodeGenTarget Target(Records);
941  CodeGenRegBank &RegBank = Target.getRegBank();
942  RegBank.computeDerivedInfo();
943
944  runEnums(OS, Target, RegBank);
945  runMCDesc(OS, Target, RegBank);
946  runTargetHeader(OS, Target, RegBank);
947  runTargetDesc(OS, Target, RegBank);
948}
949