RegisterInfoEmitter.cpp revision f9a4bb78dadc12c7c1e604c6f17b63a71305c2ca 
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of a target
11// register file for a code generator.  It uses instances of the Register,
12// RegisterAliases, and RegisterClass classes to gather this information.
13//
14//===----------------------------------------------------------------------===//
15
16#include "RegisterInfoEmitter.h"
17#include "CodeGenTarget.h"
18#include "CodeGenRegisters.h"
19#include "Record.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/Support/Format.h"
24#include <algorithm>
25#include <set>
26using namespace llvm;
27
28// runEnums - Print out enum values for all of the registers.
29void
30RegisterInfoEmitter::runEnums(raw_ostream &OS,
31                              CodeGenTarget &Target, CodeGenRegBank &Bank) {
32  const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33
34  std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
35
36  EmitSourceFileHeader("Target Register Enum Values", OS);
37
38  OS << "\n#ifdef GET_REGINFO_ENUM\n";
39  OS << "#undef GET_REGINFO_ENUM\n";
40
41  OS << "namespace llvm {\n\n";
42
43  OS << "class MCRegisterClass;\n"
44     << "extern MCRegisterClass " << Namespace << "MCRegisterClasses[];\n\n";
45
46  if (!Namespace.empty())
47    OS << "namespace " << Namespace << " {\n";
48  OS << "enum {\n  NoRegister,\n";
49
50  for (unsigned i = 0, e = Registers.size(); i != e; ++i)
51    OS << "  " << Registers[i]->getName() << " = " <<
52      Registers[i]->EnumValue << ",\n";
53  assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
54         "Register enum value mismatch!");
55  OS << "  NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
56  OS << "};\n";
57  if (!Namespace.empty())
58    OS << "}\n";
59
60  ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
61  if (!RegisterClasses.empty()) {
62    OS << "\n// Register classes\n";
63    if (!Namespace.empty())
64      OS << "namespace " << Namespace << " {\n";
65    OS << "enum {\n";
66    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
67      if (i) OS << ",\n";
68      OS << "  " << RegisterClasses[i]->getName() << "RegClassID";
69      OS << " = " << i;
70    }
71    OS << "\n  };\n";
72    if (!Namespace.empty())
73      OS << "}\n";
74  }
75
76  const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
77  // If the only definition is the default NoRegAltName, we don't need to
78  // emit anything.
79  if (RegAltNameIndices.size() > 1) {
80    OS << "\n// Register alternate name indices\n";
81    if (!Namespace.empty())
82      OS << "namespace " << Namespace << " {\n";
83    OS << "enum {\n";
84    for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
85      OS << "  " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
86    OS << "  NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
87    OS << "};\n";
88    if (!Namespace.empty())
89      OS << "}\n";
90  }
91
92
93  OS << "} // End llvm namespace \n";
94  OS << "#endif // GET_REGINFO_ENUM\n\n";
95}
96
97void
98RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
99                                    const std::vector<CodeGenRegister*> &Regs,
100                                    bool isCtor) {
101
102  // Collect all information about dwarf register numbers
103  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
104  DwarfRegNumsMapTy DwarfRegNums;
105
106  // First, just pull all provided information to the map
107  unsigned maxLength = 0;
108  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
109    Record *Reg = Regs[i]->TheDef;
110    std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
111    maxLength = std::max((size_t)maxLength, RegNums.size());
112    if (DwarfRegNums.count(Reg))
113      errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
114             << "specified multiple times\n";
115    DwarfRegNums[Reg] = RegNums;
116  }
117
118  if (!maxLength)
119    return;
120
121  // Now we know maximal length of number list. Append -1's, where needed
122  for (DwarfRegNumsMapTy::iterator
123       I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
124    for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
125      I->second.push_back(-1);
126
127  // Emit reverse information about the dwarf register numbers.
128  for (unsigned j = 0; j < 2; ++j) {
129    OS << "  switch (";
130    if (j == 0)
131      OS << "DwarfFlavour";
132    else
133      OS << "EHFlavour";
134    OS << ") {\n"
135     << "  default:\n"
136     << "    assert(0 && \"Unknown DWARF flavour\");\n"
137     << "    break;\n";
138
139    for (unsigned i = 0, e = maxLength; i != e; ++i) {
140      OS << "  case " << i << ":\n";
141      for (DwarfRegNumsMapTy::iterator
142             I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
143        int DwarfRegNo = I->second[i];
144        if (DwarfRegNo < 0)
145          continue;
146        OS << "    ";
147        if (!isCtor)
148          OS << "RI->";
149        OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
150           << getQualifiedName(I->first) << ", ";
151        if (j == 0)
152          OS << "false";
153        else
154          OS << "true";
155        OS << " );\n";
156      }
157      OS << "    break;\n";
158    }
159    OS << "  }\n";
160  }
161
162  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
163    Record *Reg = Regs[i]->TheDef;
164    const RecordVal *V = Reg->getValue("DwarfAlias");
165    if (!V || !V->getValue())
166      continue;
167
168    DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
169    Record *Alias = DI->getDef();
170    DwarfRegNums[Reg] = DwarfRegNums[Alias];
171  }
172
173  // Emit information about the dwarf register numbers.
174  for (unsigned j = 0; j < 2; ++j) {
175    OS << "  switch (";
176    if (j == 0)
177      OS << "DwarfFlavour";
178    else
179      OS << "EHFlavour";
180    OS << ") {\n"
181       << "  default:\n"
182       << "    assert(0 && \"Unknown DWARF flavour\");\n"
183       << "    break;\n";
184
185    for (unsigned i = 0, e = maxLength; i != e; ++i) {
186      OS << "  case " << i << ":\n";
187      // Sort by name to get a stable order.
188      for (DwarfRegNumsMapTy::iterator
189             I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
190        int RegNo = I->second[i];
191        OS << "    ";
192        if (!isCtor)
193          OS << "RI->";
194        OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
195           <<  RegNo << ", ";
196        if (j == 0)
197          OS << "false";
198        else
199          OS << "true";
200        OS << " );\n";
201      }
202      OS << "    break;\n";
203    }
204    OS << "  }\n";
205  }
206}
207
208// Helper to emit a set of bits into a constant byte array.
209class BitVectorEmitter {
210  BitVector Values;
211public:
212  void add(unsigned v) {
213    if (v >= Values.size())
214      Values.resize(((v/8)+1)*8); // Round up to the next byte.
215    Values[v] = true;
216  }
217
218  void print(raw_ostream &OS) {
219    for (unsigned i = 0, e = Values.size() / 8; i != e; ++i) {
220      unsigned char out = 0;
221      for (unsigned j = 0; j != 8; ++j)
222        if (Values[i * 8 + j])
223          out |= 1 << j;
224      OS << format("0x%02x, ", out);
225    }
226  }
227};
228
229//
230// runMCDesc - Print out MC register descriptions.
231//
232void
233RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
234                               CodeGenRegBank &RegBank) {
235  EmitSourceFileHeader("MC Register Information", OS);
236
237  OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
238  OS << "#undef GET_REGINFO_MC_DESC\n";
239
240  std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
241  RegBank.computeOverlaps(Overlaps);
242
243  OS << "namespace llvm {\n\n";
244
245  const std::string &TargetName = Target.getName();
246  std::string ClassName = TargetName + "GenMCRegisterInfo";
247  OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
248     << "  explicit " << ClassName << "(const MCRegisterDesc *D);\n";
249  OS << "};\n";
250
251  OS << "\nnamespace {\n";
252
253  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
254
255  // Emit an overlap list for all registers.
256  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
257    const CodeGenRegister *Reg = Regs[i];
258    const CodeGenRegister::Set &O = Overlaps[Reg];
259    // Move Reg to the front so TRI::getAliasSet can share the list.
260    OS << "  const unsigned " << Reg->getName() << "_Overlaps[] = { "
261       << getQualifiedName(Reg->TheDef) << ", ";
262    for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
263         I != E; ++I)
264      if (*I != Reg)
265        OS << getQualifiedName((*I)->TheDef) << ", ";
266    OS << "0 };\n";
267  }
268
269  // Emit the empty sub-registers list
270  OS << "  const unsigned Empty_SubRegsSet[] = { 0 };\n";
271  // Loop over all of the registers which have sub-registers, emitting the
272  // sub-registers list to memory.
273  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
274    const CodeGenRegister &Reg = *Regs[i];
275    if (Reg.getSubRegs().empty())
276     continue;
277    // getSubRegs() orders by SubRegIndex. We want a topological order.
278    SetVector<CodeGenRegister*> SR;
279    Reg.addSubRegsPreOrder(SR);
280    OS << "  const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
281    for (unsigned j = 0, je = SR.size(); j != je; ++j)
282      OS << getQualifiedName(SR[j]->TheDef) << ", ";
283    OS << "0 };\n";
284  }
285
286  // Emit the empty super-registers list
287  OS << "  const unsigned Empty_SuperRegsSet[] = { 0 };\n";
288  // Loop over all of the registers which have super-registers, emitting the
289  // super-registers list to memory.
290  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
291    const CodeGenRegister &Reg = *Regs[i];
292    const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
293    if (SR.empty())
294      continue;
295    OS << "  const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
296    for (unsigned j = 0, je = SR.size(); j != je; ++j)
297      OS << getQualifiedName(SR[j]->TheDef) << ", ";
298    OS << "0 };\n";
299  }
300  OS << "}\n";       // End of anonymous namespace...
301
302  OS << "\nMCRegisterDesc " << TargetName
303     << "RegDesc[] = { // Descriptors\n";
304  OS << "  { \"NOREG\",\t0,\t0,\t0 },\n";
305
306  // Now that register alias and sub-registers sets have been emitted, emit the
307  // register descriptors now.
308  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
309    const CodeGenRegister &Reg = *Regs[i];
310    OS << "  { \"";
311    OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
312    if (!Reg.getSubRegs().empty())
313      OS << Reg.getName() << "_SubRegsSet,\t";
314    else
315      OS << "Empty_SubRegsSet,\t";
316    if (!Reg.getSuperRegs().empty())
317      OS << Reg.getName() << "_SuperRegsSet";
318    else
319      OS << "Empty_SuperRegsSet";
320    OS << " },\n";
321  }
322  OS << "};\n\n";      // End of register descriptors...
323
324  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
325
326  // Loop over all of the register classes... emitting each one.
327  OS << "namespace {     // Register classes...\n";
328
329  // Emit the register enum value arrays for each RegisterClass
330  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
331    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
332    ArrayRef<Record*> Order = RC.getOrder();
333
334    // Give the register class a legal C name if it's anonymous.
335    std::string Name = RC.getName();
336
337    // Emit the register list now.
338    OS << "  // " << Name << " Register Class...\n"
339       << "  static const unsigned " << Name
340       << "[] = {\n    ";
341    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
342      Record *Reg = Order[i];
343      OS << getQualifiedName(Reg) << ", ";
344    }
345    OS << "\n  };\n\n";
346
347    OS << "  // " << Name << " Bit set.\n"
348       << "  static const unsigned char " << Name
349       << "Bits[] = {\n    ";
350    BitVectorEmitter BVE;
351    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
352      Record *Reg = Order[i];
353      BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
354    }
355    BVE.print(OS);
356    OS << "\n  };\n\n";
357
358  }
359  OS << "}\n\n";
360
361  OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n";
362
363  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
364    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
365    OS << "  MCRegisterClass(";
366    if (!RC.Namespace.empty())
367      OS << RC.Namespace << "::";
368    OS << RC.getName() + "RegClassID" << ", "
369       << '\"' << RC.getName() << "\", "
370       << RC.SpillSize/8 << ", "
371       << RC.SpillAlignment/8 << ", "
372       << RC.CopyCost << ", "
373       << RC.Allocatable << ", "
374       << RC.getName() << ", " << RC.getName() << " + "
375       << RC.getOrder().size() << ", "
376       << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)"
377       << "),\n";
378  }
379
380  OS << "};\n\n";
381
382  // MCRegisterInfo initialization routine.
383  OS << "static inline void Init" << TargetName
384     << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
385     << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
386  OS << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
387     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
388     << RegisterClasses.size() << ");\n\n";
389
390  EmitRegMapping(OS, Regs, false);
391
392  OS << "}\n\n";
393
394
395  OS << "} // End llvm namespace \n";
396  OS << "#endif // GET_REGINFO_MC_DESC\n\n";
397}
398
399void
400RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
401                                     CodeGenRegBank &RegBank) {
402  EmitSourceFileHeader("Register Information Header Fragment", OS);
403
404  OS << "\n#ifdef GET_REGINFO_HEADER\n";
405  OS << "#undef GET_REGINFO_HEADER\n";
406
407  const std::string &TargetName = Target.getName();
408  std::string ClassName = TargetName + "GenRegisterInfo";
409
410  OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
411  OS << "#include <string>\n\n";
412
413  OS << "namespace llvm {\n\n";
414
415  OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
416     << "  explicit " << ClassName
417     << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
418     << "  virtual bool needsStackRealignment(const MachineFunction &) const\n"
419     << "     { return false; }\n"
420     << "  unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
421     << "  unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
422     << "  unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
423     << "};\n\n";
424
425  const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
426  if (!SubRegIndices.empty()) {
427    OS << "\n// Subregister indices\n";
428    std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
429    if (!Namespace.empty())
430      OS << "namespace " << Namespace << " {\n";
431    OS << "enum {\n  NoSubRegister,\n";
432    for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
433      OS << "  " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
434    OS << "  NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
435    OS << "};\n";
436    if (!Namespace.empty())
437      OS << "}\n";
438  }
439
440  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
441
442  if (!RegisterClasses.empty()) {
443    OS << "namespace " << RegisterClasses[0]->Namespace
444       << " { // Register classes\n";
445
446    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
447      const CodeGenRegisterClass &RC = *RegisterClasses[i];
448      const std::string &Name = RC.getName();
449
450      // Output the register class definition.
451      OS << "  struct " << Name << "Class : public TargetRegisterClass {\n"
452         << "    " << Name << "Class();\n";
453      if (!RC.AltOrderSelect.empty())
454        OS << "    ArrayRef<unsigned> "
455              "getRawAllocationOrder(const MachineFunction&) const;\n";
456      OS << "  };\n";
457
458      // Output the extern for the instance.
459      OS << "  extern " << Name << "Class\t" << Name << "RegClass;\n";
460      // Output the extern for the pointer to the instance (should remove).
461      OS << "  static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
462         << Name << "RegClass;\n";
463    }
464    OS << "} // end of namespace " << TargetName << "\n\n";
465  }
466  OS << "} // End llvm namespace \n";
467  OS << "#endif // GET_REGINFO_HEADER\n\n";
468}
469
470//
471// runTargetDesc - Output the target register and register file descriptions.
472//
473void
474RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
475                                   CodeGenRegBank &RegBank){
476  EmitSourceFileHeader("Target Register and Register Classes Information", OS);
477
478  OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
479  OS << "#undef GET_REGINFO_TARGET_DESC\n";
480
481  OS << "namespace llvm {\n\n";
482
483  // Get access to MCRegisterClass data.
484  OS << "extern MCRegisterClass " << Target.getName()
485    << "MCRegisterClasses[];\n";
486
487  // Start out by emitting each of the register classes.
488  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
489
490  // Collect all registers belonging to any allocatable class.
491  std::set<Record*> AllocatableRegs;
492
493  // Collect allocatable registers.
494  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
495    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
496    ArrayRef<Record*> Order = RC.getOrder();
497
498    if (RC.Allocatable)
499      AllocatableRegs.insert(Order.begin(), Order.end());
500  }
501
502  OS << "namespace {     // Register classes...\n";
503
504  // Emit the ValueType arrays for each RegisterClass
505  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
506    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
507
508    // Give the register class a legal C name if it's anonymous.
509    std::string Name = RC.getName() + "VTs";
510
511    // Emit the register list now.
512    OS << "  // " << Name
513       << " Register Class Value Types...\n"
514       << "  static const EVT " << Name
515       << "[] = {\n    ";
516    for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
517      OS << getEnumName(RC.VTs[i]) << ", ";
518    OS << "MVT::Other\n  };\n\n";
519  }
520  OS << "}  // end anonymous namespace\n\n";
521
522  // Now that all of the structs have been emitted, emit the instances.
523  if (!RegisterClasses.empty()) {
524    OS << "namespace " << RegisterClasses[0]->Namespace
525       << " {   // Register class instances\n";
526    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
527      OS << "  " << RegisterClasses[i]->getName()  << "Class\t"
528         << RegisterClasses[i]->getName() << "RegClass;\n";
529
530    std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
531
532    OS << "\n  static const TargetRegisterClass* const "
533      << "NullRegClasses[] = { NULL };\n\n";
534
535    unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
536
537    if (NumSubRegIndices) {
538      // Emit the sub-register classes for each RegisterClass
539      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
540        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
541        std::vector<Record*> SRC(NumSubRegIndices);
542        for (DenseMap<Record*,Record*>::const_iterator
543             i = RC.SubRegClasses.begin(),
544             e = RC.SubRegClasses.end(); i != e; ++i) {
545          // Build SRC array.
546          unsigned idx = RegBank.getSubRegIndexNo(i->first);
547          SRC.at(idx-1) = i->second;
548
549          // Find the register class number of i->second for SuperRegClassMap.
550          for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
551            const CodeGenRegisterClass &RC2 = *RegisterClasses[rc2];
552            if (RC2.TheDef == i->second) {
553              SuperRegClassMap[rc2].insert(rc);
554              break;
555            }
556          }
557        }
558
559        // Give the register class a legal C name if it's anonymous.
560        std::string Name = RC.TheDef->getName();
561
562        OS << "  // " << Name
563           << " Sub-register Classes...\n"
564           << "  static const TargetRegisterClass* const "
565           << Name << "SubRegClasses[] = {\n    ";
566
567        for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
568          if (idx)
569            OS << ", ";
570          if (SRC[idx])
571            OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
572          else
573            OS << "0";
574        }
575        OS << "\n  };\n\n";
576      }
577
578      // Emit the super-register classes for each RegisterClass
579      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
580        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
581
582        // Give the register class a legal C name if it's anonymous.
583        std::string Name = RC.TheDef->getName();
584
585        OS << "  // " << Name
586           << " Super-register Classes...\n"
587           << "  static const TargetRegisterClass* const "
588           << Name << "SuperRegClasses[] = {\n    ";
589
590        bool Empty = true;
591        std::map<unsigned, std::set<unsigned> >::iterator I =
592          SuperRegClassMap.find(rc);
593        if (I != SuperRegClassMap.end()) {
594          for (std::set<unsigned>::iterator II = I->second.begin(),
595                 EE = I->second.end(); II != EE; ++II) {
596            const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
597            if (!Empty)
598              OS << ", ";
599            OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
600            Empty = false;
601          }
602        }
603
604        OS << (!Empty ? ", " : "") << "NULL";
605        OS << "\n  };\n\n";
606      }
607    }
608
609    // Emit the sub-classes array for each RegisterClass
610    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
611      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
612
613      // Give the register class a legal C name if it's anonymous.
614      std::string Name = RC.TheDef->getName();
615
616      OS << "  // " << Name
617         << " Register Class sub-classes...\n"
618         << "  static const TargetRegisterClass* const "
619         << Name << "Subclasses[] = {\n    ";
620
621      bool Empty = true;
622      for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
623        const CodeGenRegisterClass &RC2 = *RegisterClasses[rc2];
624
625        // Sub-classes are used to determine if a virtual register can be used
626        // as an instruction operand, or if it must be copied first.
627        if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
628
629        if (!Empty) OS << ", ";
630        OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
631        Empty = false;
632      }
633
634      OS << (!Empty ? ", " : "") << "NULL";
635      OS << "\n  };\n\n";
636    }
637
638    // Emit NULL terminated super-class lists.
639    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
640      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
641      ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
642
643      // Skip classes without supers.  We can reuse NullRegClasses.
644      if (Supers.empty())
645        continue;
646
647      OS << "  static const TargetRegisterClass* const "
648         << RC.getName() << "Superclasses[] = {\n";
649      for (unsigned i = 0; i != Supers.size(); ++i)
650        OS << "    &" << getQualifiedName(Supers[i]->TheDef) << "RegClass,\n";
651      OS << "    NULL\n  };\n\n";
652    }
653
654    // Emit methods.
655    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
656      const CodeGenRegisterClass &RC = *RegisterClasses[i];
657      OS << RC.getName() << "Class::" << RC.getName()
658         << "Class()  : TargetRegisterClass(&"
659         << Target.getName() << "MCRegisterClasses["
660         << RC.getName() + "RegClassID" << "], "
661         << RC.getName() + "VTs" << ", "
662         << RC.getName() + "Subclasses" << ", ";
663      if (RC.getSuperClasses().empty())
664        OS << "NullRegClasses, ";
665      else
666        OS << RC.getName() + "Superclasses, ";
667      OS << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
668         << "RegClasses, "
669         << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
670         << "RegClasses"
671         << ") {}\n";
672      if (!RC.AltOrderSelect.empty()) {
673        OS << "\nstatic inline unsigned " << RC.getName()
674           << "AltOrderSelect(const MachineFunction &MF) {"
675           << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
676           << RC.getName() << "Class::"
677           << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
678        for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
679          ArrayRef<Record*> Elems = RC.getOrder(oi);
680          OS << "  static const unsigned AltOrder" << oi << "[] = {";
681          for (unsigned elem = 0; elem != Elems.size(); ++elem)
682            OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
683          OS << " };\n";
684        }
685        OS << "  const MCRegisterClass &MCR = " << Target.getName()
686           << "MCRegisterClasses[";
687        if (!RC.Namespace.empty())
688          OS << RC.Namespace << "::";
689        OS << RC.getName() + "RegClassID];"
690           << "  static const ArrayRef<unsigned> Order[] = {\n"
691           << "    makeArrayRef(MCR.begin(), MCR.getNumRegs()";
692        for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
693          OS << "),\n    makeArrayRef(AltOrder" << oi;
694        OS << ")\n  };\n  const unsigned Select = " << RC.getName()
695           << "AltOrderSelect(MF);\n  assert(Select < " << RC.getNumOrders()
696           << ");\n  return Order[Select];\n}\n";
697        }
698    }
699
700    OS << "}\n";
701  }
702
703  OS << "\nnamespace {\n";
704  OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
705  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
706    OS << "    &" << getQualifiedName(RegisterClasses[i]->TheDef)
707       << "RegClass,\n";
708  OS << "  };\n";
709  OS << "}\n";       // End of anonymous namespace...
710
711  // Emit extra information about registers.
712  const std::string &TargetName = Target.getName();
713  OS << "\n  static const TargetRegisterInfoDesc "
714     << TargetName << "RegInfoDesc[] = "
715     << "{ // Extra Descriptors\n";
716  OS << "    { 0, 0 },\n";
717
718  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
719  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
720    const CodeGenRegister &Reg = *Regs[i];
721    OS << "    { ";
722    OS << Reg.CostPerUse << ", "
723       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
724  }
725  OS << "  };\n";      // End of register descriptors...
726
727
728  // Calculate the mapping of subregister+index pairs to physical registers.
729  // This will also create further anonymous indexes.
730  unsigned NamedIndices = RegBank.getNumNamedIndices();
731
732  // Emit SubRegIndex names, skipping 0
733  const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
734  OS << "\n  static const char *const " << TargetName
735     << "SubRegIndexTable[] = { \"";
736  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
737    OS << SubRegIndices[i]->getName();
738    if (i+1 != e)
739      OS << "\", \"";
740  }
741  OS << "\" };\n\n";
742
743  // Emit names of the anonymus subreg indexes.
744  if (SubRegIndices.size() > NamedIndices) {
745    OS << "  enum {";
746    for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
747      OS << "\n    " << SubRegIndices[i]->getName() << " = " << i+1;
748      if (i+1 != e)
749        OS << ',';
750    }
751    OS << "\n  };\n\n";
752  }
753  OS << "\n";
754
755  std::string ClassName = Target.getName() + "GenRegisterInfo";
756
757  // Emit the subregister + index mapping function based on the information
758  // calculated above.
759  OS << "unsigned " << ClassName
760     << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
761     << "  switch (RegNo) {\n"
762     << "  default:\n    return 0;\n";
763  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
764    const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
765    if (SRM.empty())
766      continue;
767    OS << "  case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
768    OS << "    switch (Index) {\n";
769    OS << "    default: return 0;\n";
770    for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
771         ie = SRM.end(); ii != ie; ++ii)
772      OS << "    case " << getQualifiedName(ii->first)
773         << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
774    OS << "    };\n" << "    break;\n";
775  }
776  OS << "  };\n";
777  OS << "  return 0;\n";
778  OS << "}\n\n";
779
780  OS << "unsigned " << ClassName
781     << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
782     << "  switch (RegNo) {\n"
783     << "  default:\n    return 0;\n";
784   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
785     const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
786     if (SRM.empty())
787       continue;
788    OS << "  case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
789    for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
790         ie = SRM.end(); ii != ie; ++ii)
791      OS << "    if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
792         << ")  return " << getQualifiedName(ii->first) << ";\n";
793    OS << "    return 0;\n";
794  }
795  OS << "  };\n";
796  OS << "  return 0;\n";
797  OS << "}\n\n";
798
799  // Emit composeSubRegIndices
800  OS << "unsigned " << ClassName
801     << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
802     << "  switch (IdxA) {\n"
803     << "  default:\n    return IdxB;\n";
804  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
805    bool Open = false;
806    for (unsigned j = 0; j != e; ++j) {
807      if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
808                                                         SubRegIndices[j])) {
809        if (!Open) {
810          OS << "  case " << getQualifiedName(SubRegIndices[i])
811             << ": switch(IdxB) {\n    default: return IdxB;\n";
812          Open = true;
813        }
814        OS << "    case " << getQualifiedName(SubRegIndices[j])
815           << ": return " << getQualifiedName(Comp) << ";\n";
816      }
817    }
818    if (Open)
819      OS << "    }\n";
820  }
821  OS << "  }\n}\n\n";
822
823  // Emit the constructor of the class...
824  OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
825
826  OS << ClassName << "::" << ClassName
827     << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
828     << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
829     << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
830     << "                 " << TargetName << "SubRegIndexTable) {\n"
831     << "  InitMCRegisterInfo(" << TargetName << "RegDesc, "
832     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
833     << RegisterClasses.size() << ");\n\n";
834
835  EmitRegMapping(OS, Regs, true);
836
837  OS << "}\n\n";
838
839  OS << "} // End llvm namespace \n";
840  OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
841}
842
843void RegisterInfoEmitter::run(raw_ostream &OS) {
844  CodeGenTarget Target(Records);
845  CodeGenRegBank &RegBank = Target.getRegBank();
846  RegBank.computeDerivedInfo();
847
848  runEnums(OS, Target, RegBank);
849  runMCDesc(OS, Target, RegBank);
850  runTargetHeader(OS, Target, RegBank);
851  runTargetDesc(OS, Target, RegBank);
852}
853