SubtargetEmitter.cpp revision 3881cb7a5d54c0011b40997adcd742e1c7b91abd
1//===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend emits subtarget enumerations. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SubtargetEmitter.h" 15#include "CodeGenTarget.h" 16#include "Record.h" 17#include "llvm/ADT/StringExtras.h" 18#include "llvm/Support/Debug.h" 19#include <algorithm> 20using namespace llvm; 21 22// 23// Enumeration - Emit the specified class as an enumeration. 24// 25void SubtargetEmitter::Enumeration(raw_ostream &OS, 26 const char *ClassName, 27 bool isBits) { 28 // Get all records of class and sort 29 std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName); 30 std::sort(DefList.begin(), DefList.end(), LessRecord()); 31 32 // Open enumeration 33 OS << "enum {\n"; 34 35 // For each record 36 for (unsigned i = 0, N = DefList.size(); i < N;) { 37 // Next record 38 Record *Def = DefList[i]; 39 40 // Get and emit name 41 OS << " " << Def->getName(); 42 43 // If bit flags then emit expression (1 << i) 44 if (isBits) OS << " = " << " 1 << " << i; 45 46 // Depending on 'if more in the list' emit comma 47 if (++i < N) OS << ","; 48 49 OS << "\n"; 50 } 51 52 // Close enumeration 53 OS << "};\n"; 54} 55 56// 57// FeatureKeyValues - Emit data of all the subtarget features. Used by the 58// command line. 59// 60void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { 61 // Gather and sort all the features 62 std::vector<Record*> FeatureList = 63 Records.getAllDerivedDefinitions("SubtargetFeature"); 64 std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName()); 65 66 // Begin feature table 67 OS << "// Sorted (by key) array of values for CPU features.\n" 68 << "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n"; 69 70 // For each feature 71 for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) { 72 // Next feature 73 Record *Feature = FeatureList[i]; 74 75 const std::string &Name = Feature->getName(); 76 const std::string &CommandLineName = Feature->getValueAsString("Name"); 77 const std::string &Desc = Feature->getValueAsString("Desc"); 78 79 if (CommandLineName.empty()) continue; 80 81 // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in } 82 OS << " { " 83 << "\"" << CommandLineName << "\", " 84 << "\"" << Desc << "\", " 85 << Name << ", "; 86 87 const std::vector<Record*> &ImpliesList = 88 Feature->getValueAsListOfDefs("Implies"); 89 90 if (ImpliesList.empty()) { 91 OS << "0"; 92 } else { 93 for (unsigned j = 0, M = ImpliesList.size(); j < M;) { 94 OS << ImpliesList[j]->getName(); 95 if (++j < M) OS << " | "; 96 } 97 } 98 99 OS << " }"; 100 101 // Depending on 'if more in the list' emit comma 102 if ((i + 1) < N) OS << ","; 103 104 OS << "\n"; 105 } 106 107 // End feature table 108 OS << "};\n"; 109 110 // Emit size of table 111 OS<<"\nenum {\n"; 112 OS<<" FeatureKVSize = sizeof(FeatureKV)/sizeof(llvm::SubtargetFeatureKV)\n"; 113 OS<<"};\n"; 114} 115 116// 117// CPUKeyValues - Emit data of all the subtarget processors. Used by command 118// line. 119// 120void SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { 121 // Gather and sort processor information 122 std::vector<Record*> ProcessorList = 123 Records.getAllDerivedDefinitions("Processor"); 124 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); 125 126 // Begin processor table 127 OS << "// Sorted (by key) array of values for CPU subtype.\n" 128 << "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n"; 129 130 // For each processor 131 for (unsigned i = 0, N = ProcessorList.size(); i < N;) { 132 // Next processor 133 Record *Processor = ProcessorList[i]; 134 135 const std::string &Name = Processor->getValueAsString("Name"); 136 const std::vector<Record*> &FeatureList = 137 Processor->getValueAsListOfDefs("Features"); 138 139 // Emit as { "cpu", "description", f1 | f2 | ... fn }, 140 OS << " { " 141 << "\"" << Name << "\", " 142 << "\"Select the " << Name << " processor\", "; 143 144 if (FeatureList.empty()) { 145 OS << "0"; 146 } else { 147 for (unsigned j = 0, M = FeatureList.size(); j < M;) { 148 OS << FeatureList[j]->getName(); 149 if (++j < M) OS << " | "; 150 } 151 } 152 153 // The "0" is for the "implies" section of this data structure. 154 OS << ", 0 }"; 155 156 // Depending on 'if more in the list' emit comma 157 if (++i < N) OS << ","; 158 159 OS << "\n"; 160 } 161 162 // End processor table 163 OS << "};\n"; 164 165 // Emit size of table 166 OS<<"\nenum {\n"; 167 OS<<" SubTypeKVSize = sizeof(SubTypeKV)/sizeof(llvm::SubtargetFeatureKV)\n"; 168 OS<<"};\n"; 169} 170 171// 172// CollectAllItinClasses - Gathers and enumerates all the itinerary classes. 173// Returns itinerary class count. 174// 175unsigned SubtargetEmitter:: 176CollectAllItinClasses(raw_ostream &OS, 177 std::map<std::string, unsigned> &ItinClassesMap, 178 std::vector<Record*> &ItinClassList) { 179 // For each itinerary class 180 unsigned N = ItinClassList.size(); 181 for (unsigned i = 0; i < N; i++) { 182 // Next itinerary class 183 const Record *ItinClass = ItinClassList[i]; 184 // Get name of itinerary class 185 // Assign itinerary class a unique number 186 ItinClassesMap[ItinClass->getName()] = i; 187 } 188 189 // Emit size of table 190 OS<<"\nenum {\n"; 191 OS<<" ItinClassesSize = " << N << "\n"; 192 OS<<"};\n"; 193 194 // Return itinerary class count 195 return N; 196} 197 198// 199// FormItineraryStageString - Compose a string containing the stage 200// data initialization for the specified itinerary. N is the number 201// of stages. 202// 203void SubtargetEmitter::FormItineraryStageString(const std::string &Name, 204 Record *ItinData, 205 std::string &ItinString, 206 unsigned &NStages) { 207 // Get states list 208 const std::vector<Record*> &StageList = 209 ItinData->getValueAsListOfDefs("Stages"); 210 211 // For each stage 212 unsigned N = NStages = StageList.size(); 213 for (unsigned i = 0; i < N;) { 214 // Next stage 215 const Record *Stage = StageList[i]; 216 217 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind } 218 int Cycles = Stage->getValueAsInt("Cycles"); 219 ItinString += " { " + itostr(Cycles) + ", "; 220 221 // Get unit list 222 const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units"); 223 224 // For each unit 225 for (unsigned j = 0, M = UnitList.size(); j < M;) { 226 // Add name and bitwise or 227 ItinString += Name + "FU::" + UnitList[j]->getName(); 228 if (++j < M) ItinString += " | "; 229 } 230 231 int TimeInc = Stage->getValueAsInt("TimeInc"); 232 ItinString += ", " + itostr(TimeInc); 233 234 int Kind = Stage->getValueAsInt("Kind"); 235 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind); 236 237 // Close off stage 238 ItinString += " }"; 239 if (++i < N) ItinString += ", "; 240 } 241} 242 243// 244// FormItineraryOperandCycleString - Compose a string containing the 245// operand cycle initialization for the specified itinerary. N is the 246// number of operands that has cycles specified. 247// 248void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, 249 std::string &ItinString, unsigned &NOperandCycles) { 250 // Get operand cycle list 251 const std::vector<int64_t> &OperandCycleList = 252 ItinData->getValueAsListOfInts("OperandCycles"); 253 254 // For each operand cycle 255 unsigned N = NOperandCycles = OperandCycleList.size(); 256 for (unsigned i = 0; i < N;) { 257 // Next operand cycle 258 const int OCycle = OperandCycleList[i]; 259 260 ItinString += " " + itostr(OCycle); 261 if (++i < N) ItinString += ", "; 262 } 263} 264 265void SubtargetEmitter::FormItineraryBypassString(const std::string &Name, 266 Record *ItinData, 267 std::string &ItinString, 268 unsigned NOperandCycles) { 269 const std::vector<Record*> &BypassList = 270 ItinData->getValueAsListOfDefs("Bypasses"); 271 unsigned N = BypassList.size(); 272 unsigned i = 0; 273 for (; i < N;) { 274 ItinString += Name + "Bypass::" + BypassList[i]->getName(); 275 if (++i < NOperandCycles) ItinString += ", "; 276 } 277 for (; i < NOperandCycles;) { 278 ItinString += " 0"; 279 if (++i < NOperandCycles) ItinString += ", "; 280 } 281} 282 283// 284// EmitStageAndOperandCycleData - Generate unique itinerary stages and 285// operand cycle tables. Record itineraries for processors. 286// 287void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, 288 unsigned NItinClasses, 289 std::map<std::string, unsigned> &ItinClassesMap, 290 std::vector<Record*> &ItinClassList, 291 std::vector<std::vector<InstrItinerary> > &ProcList) { 292 // Gather processor iteraries 293 std::vector<Record*> ProcItinList = 294 Records.getAllDerivedDefinitions("ProcessorItineraries"); 295 296 // If just no itinerary then don't bother 297 if (ProcItinList.size() < 2) return; 298 299 // Emit functional units for all the itineraries. 300 for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) { 301 // Next record 302 Record *Proc = ProcItinList[i]; 303 304 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU"); 305 if (FUs.empty()) 306 continue; 307 308 const std::string &Name = Proc->getName(); 309 OS << "\n// Functional units for itineraries \"" << Name << "\"\n" 310 << "namespace " << Name << "FU {\n"; 311 312 for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j) 313 OS << " const unsigned " << FUs[j]->getName() 314 << " = 1 << " << j << ";\n"; 315 316 OS << "}\n"; 317 318 std::vector<Record*> BPs = Proc->getValueAsListOfDefs("BP"); 319 if (BPs.size()) { 320 OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name 321 << "\"\n" << "namespace " << Name << "Bypass {\n"; 322 323 OS << " const unsigned NoBypass = 0;\n"; 324 for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j) 325 OS << " const unsigned " << BPs[j]->getName() 326 << " = 1 << " << j << ";\n"; 327 328 OS << "}\n"; 329 } 330 } 331 332 // Begin stages table 333 std::string StageTable = "\nstatic const llvm::InstrStage Stages[] = {\n"; 334 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n"; 335 336 // Begin operand cycle table 337 std::string OperandCycleTable = "static const unsigned OperandCycles[] = {\n"; 338 OperandCycleTable += " 0, // No itinerary\n"; 339 340 // Begin pipeline bypass table 341 std::string BypassTable = "static const unsigned ForwardingPathes[] = {\n"; 342 BypassTable += " 0, // No itinerary\n"; 343 344 unsigned StageCount = 1, OperandCycleCount = 1; 345 unsigned ItinStageEnum = 1, ItinOperandCycleEnum = 1; 346 std::map<std::string, unsigned> ItinStageMap, ItinOperandMap; 347 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) { 348 // Next record 349 Record *Proc = ProcItinList[i]; 350 351 // Get processor itinerary name 352 const std::string &Name = Proc->getName(); 353 354 // Skip default 355 if (Name == "NoItineraries") continue; 356 357 // Create and expand processor itinerary to cover all itinerary classes 358 std::vector<InstrItinerary> ItinList; 359 ItinList.resize(NItinClasses); 360 361 // Get itinerary data list 362 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID"); 363 364 // For each itinerary data 365 for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) { 366 // Next itinerary data 367 Record *ItinData = ItinDataList[j]; 368 369 // Get string and stage count 370 std::string ItinStageString; 371 unsigned NStages; 372 FormItineraryStageString(Name, ItinData, ItinStageString, NStages); 373 374 // Get string and operand cycle count 375 std::string ItinOperandCycleString; 376 unsigned NOperandCycles; 377 FormItineraryOperandCycleString(ItinData, ItinOperandCycleString, 378 NOperandCycles); 379 380 std::string ItinBypassString; 381 FormItineraryBypassString(Name, ItinData, ItinBypassString, 382 NOperandCycles); 383 384 // Check to see if stage already exists and create if it doesn't 385 unsigned FindStage = 0; 386 if (NStages > 0) { 387 FindStage = ItinStageMap[ItinStageString]; 388 if (FindStage == 0) { 389 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // index 390 StageTable += ItinStageString + ", // " + itostr(ItinStageEnum) + "\n"; 391 // Record Itin class number. 392 ItinStageMap[ItinStageString] = FindStage = StageCount; 393 StageCount += NStages; 394 ItinStageEnum++; 395 } 396 } 397 398 // Check to see if operand cycle already exists and create if it doesn't 399 unsigned FindOperandCycle = 0; 400 if (NOperandCycles > 0) { 401 std::string ItinOperandString = ItinOperandCycleString+ItinBypassString; 402 FindOperandCycle = ItinOperandMap[ItinOperandString]; 403 if (FindOperandCycle == 0) { 404 // Emit as cycle, // index 405 OperandCycleTable += ItinOperandCycleString + ", // " + 406 itostr(ItinOperandCycleEnum) + "\n"; 407 // Record Itin class number. 408 ItinOperandMap[ItinOperandCycleString] = 409 FindOperandCycle = OperandCycleCount; 410 411 // Emit as bypass, // index 412 BypassTable += ItinBypassString + ", // " + 413 itostr(ItinOperandCycleEnum) + "\n"; 414 415 OperandCycleCount += NOperandCycles; 416 ItinOperandCycleEnum++; 417 } 418 } 419 420 // Locate where to inject into processor itinerary table 421 const std::string &Name = ItinData->getValueAsDef("TheClass")->getName(); 422 unsigned Find = ItinClassesMap[Name]; 423 424 // Set up itinerary as location and location + stage count 425 unsigned NumUOps = ItinClassList[Find]->getValueAsInt("NumMicroOps"); 426 InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages, 427 FindOperandCycle, 428 FindOperandCycle + NOperandCycles}; 429 430 // Inject - empty slots will be 0, 0 431 ItinList[Find] = Intinerary; 432 } 433 434 // Add process itinerary to list 435 ProcList.push_back(ItinList); 436 } 437 438 // Closing stage 439 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End itinerary\n"; 440 StageTable += "};\n"; 441 442 // Closing operand cycles 443 OperandCycleTable += " 0 // End itinerary\n"; 444 OperandCycleTable += "};\n"; 445 446 BypassTable += " 0 // End itinerary\n"; 447 BypassTable += "};\n"; 448 449 // Emit tables. 450 OS << StageTable; 451 OS << OperandCycleTable; 452 OS << BypassTable; 453 454 // Emit size of tables 455 OS<<"\nenum {\n"; 456 OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),\n"; 457 OS<<" OperandCyclesSize = sizeof(OperandCycles)/sizeof(unsigned)\n"; 458 OS<<"};\n"; 459} 460 461// 462// EmitProcessorData - Generate data for processor itineraries. 463// 464void SubtargetEmitter::EmitProcessorData(raw_ostream &OS, 465 std::vector<std::vector<InstrItinerary> > &ProcList) { 466 // Get an iterator for processor itinerary stages 467 std::vector<std::vector<InstrItinerary> >::iterator 468 ProcListIter = ProcList.begin(); 469 470 // For each processor itinerary 471 std::vector<Record*> Itins = 472 Records.getAllDerivedDefinitions("ProcessorItineraries"); 473 for (unsigned i = 0, N = Itins.size(); i < N; i++) { 474 // Next record 475 Record *Itin = Itins[i]; 476 477 // Get processor itinerary name 478 const std::string &Name = Itin->getName(); 479 480 // Skip default 481 if (Name == "NoItineraries") continue; 482 483 // Begin processor itinerary table 484 OS << "\n"; 485 OS << "static const llvm::InstrItinerary " << Name << "[] = {\n"; 486 487 // For each itinerary class 488 std::vector<InstrItinerary> &ItinList = *ProcListIter++; 489 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { 490 InstrItinerary &Intinerary = ItinList[j]; 491 492 // Emit in the form of 493 // { firstStage, lastStage, firstCycle, lastCycle } // index 494 if (Intinerary.FirstStage == 0) { 495 OS << " { 1, 0, 0, 0, 0 }"; 496 } else { 497 OS << " { " << 498 Intinerary.NumMicroOps << ", " << 499 Intinerary.FirstStage << ", " << 500 Intinerary.LastStage << ", " << 501 Intinerary.FirstOperandCycle << ", " << 502 Intinerary.LastOperandCycle << " }"; 503 } 504 505 OS << ", // " << j << "\n"; 506 } 507 508 // End processor itinerary table 509 OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n"; 510 OS << "};\n"; 511 } 512} 513 514// 515// EmitProcessorLookup - generate cpu name to itinerary lookup table. 516// 517void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { 518 // Gather and sort processor information 519 std::vector<Record*> ProcessorList = 520 Records.getAllDerivedDefinitions("Processor"); 521 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); 522 523 // Begin processor table 524 OS << "\n"; 525 OS << "// Sorted (by key) array of itineraries for CPU subtype.\n" 526 << "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n"; 527 528 // For each processor 529 for (unsigned i = 0, N = ProcessorList.size(); i < N;) { 530 // Next processor 531 Record *Processor = ProcessorList[i]; 532 533 const std::string &Name = Processor->getValueAsString("Name"); 534 const std::string &ProcItin = 535 Processor->getValueAsDef("ProcItin")->getName(); 536 537 // Emit as { "cpu", procinit }, 538 OS << " { " 539 << "\"" << Name << "\", " 540 << "(void *)&" << ProcItin; 541 542 OS << " }"; 543 544 // Depending on ''if more in the list'' emit comma 545 if (++i < N) OS << ","; 546 547 OS << "\n"; 548 } 549 550 // End processor table 551 OS << "};\n"; 552 553 // Emit size of table 554 OS<<"\nenum {\n"; 555 OS<<" ProcItinKVSize = sizeof(ProcItinKV)/" 556 "sizeof(llvm::SubtargetInfoKV)\n"; 557 OS<<"};\n"; 558} 559 560// 561// EmitData - Emits all stages and itineries, folding common patterns. 562// 563void SubtargetEmitter::EmitData(raw_ostream &OS) { 564 std::map<std::string, unsigned> ItinClassesMap; 565 // Gather and sort all itinerary classes 566 std::vector<Record*> ItinClassList = 567 Records.getAllDerivedDefinitions("InstrItinClass"); 568 std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); 569 570 // Enumerate all the itinerary classes 571 unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap, 572 ItinClassList); 573 // Make sure the rest is worth the effort 574 HasItineraries = NItinClasses != 1; // Ignore NoItinerary. 575 576 if (HasItineraries) { 577 std::vector<std::vector<InstrItinerary> > ProcList; 578 // Emit the stage data 579 EmitStageAndOperandCycleData(OS, NItinClasses, ItinClassesMap, 580 ItinClassList, ProcList); 581 // Emit the processor itinerary data 582 EmitProcessorData(OS, ProcList); 583 // Emit the processor lookup data 584 EmitProcessorLookup(OS); 585 } 586} 587 588// 589// ParseFeaturesFunction - Produces a subtarget specific function for parsing 590// the subtarget features string. 591// 592void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { 593 std::vector<Record*> Features = 594 Records.getAllDerivedDefinitions("SubtargetFeature"); 595 std::sort(Features.begin(), Features.end(), LessRecord()); 596 597 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" 598 << "// subtarget options.\n" 599 << "std::string llvm::"; 600 OS << Target; 601 OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n" 602 << " const std::string &CPU) {\n" 603 << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n" 604 << " DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n" 605 << " SubtargetFeatures Features(FS);\n" 606 << " Features.setCPUIfNone(CPU);\n" 607 << " uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n" 608 << " FeatureKV, FeatureKVSize);\n"; 609 610 for (unsigned i = 0; i < Features.size(); i++) { 611 // Next record 612 Record *R = Features[i]; 613 const std::string &Instance = R->getName(); 614 const std::string &Value = R->getValueAsString("Value"); 615 const std::string &Attribute = R->getValueAsString("Attribute"); 616 617 if (Value=="true" || Value=="false") 618 OS << " if ((Bits & " << Instance << ") != 0) " 619 << Attribute << " = " << Value << ";\n"; 620 else 621 OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute << 622 " < " << Value << ") " << Attribute << " = " << Value << ";\n"; 623 } 624 625 if (HasItineraries) { 626 OS << "\n" 627 << " InstrItinerary *Itinerary = (InstrItinerary *)" 628 << "Features.getInfo(ProcItinKV, ProcItinKVSize);\n" 629 << " InstrItins = InstrItineraryData(Stages, OperandCycles, " 630 << "ForwardingPathes, Itinerary);\n"; 631 } 632 633 OS << " return Features.getCPU();\n" 634 << "}\n"; 635} 636 637// 638// SubtargetEmitter::run - Main subtarget enumeration emitter. 639// 640void SubtargetEmitter::run(raw_ostream &OS) { 641 Target = CodeGenTarget().getName(); 642 643 EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); 644 645 OS << "#include \"llvm/Support/Debug.h\"\n"; 646 OS << "#include \"llvm/Support/raw_ostream.h\"\n"; 647 OS << "#include \"llvm/Target/SubtargetFeature.h\"\n"; 648 OS << "#include \"llvm/Target/TargetInstrItineraries.h\"\n\n"; 649 650// Enumeration(OS, "FuncUnit", true); 651// OS<<"\n"; 652// Enumeration(OS, "InstrItinClass", false); 653// OS<<"\n"; 654 Enumeration(OS, "SubtargetFeature", true); 655 OS<<"\n"; 656 FeatureKeyValues(OS); 657 OS<<"\n"; 658 CPUKeyValues(OS); 659 OS<<"\n"; 660 EmitData(OS); 661 OS<<"\n"; 662 ParseFeaturesFunction(OS); 663} 664