r600.h revision 6d0a011acbea90537d142c86b8dd5aecd1e14390
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_H 27#define R600_H 28 29#include "../../winsys/radeon/drm/radeon_winsys.h" 30#include "util/u_double_list.h" 31#include "util/u_vbuf.h" 32 33#define R600_ERR(fmt, args...) \ 34 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) 35 36struct winsys_handle; 37 38enum radeon_family { 39 CHIP_UNKNOWN, 40 CHIP_R600, 41 CHIP_RV610, 42 CHIP_RV630, 43 CHIP_RV670, 44 CHIP_RV620, 45 CHIP_RV635, 46 CHIP_RS780, 47 CHIP_RS880, 48 CHIP_RV770, 49 CHIP_RV730, 50 CHIP_RV710, 51 CHIP_RV740, 52 CHIP_CEDAR, 53 CHIP_REDWOOD, 54 CHIP_JUNIPER, 55 CHIP_CYPRESS, 56 CHIP_HEMLOCK, 57 CHIP_PALM, 58 CHIP_SUMO, 59 CHIP_SUMO2, 60 CHIP_BARTS, 61 CHIP_TURKS, 62 CHIP_CAICOS, 63 CHIP_CAYMAN, 64 CHIP_LAST, 65}; 66 67enum chip_class { 68 R600, 69 R700, 70 EVERGREEN, 71 CAYMAN, 72}; 73 74struct r600_tiling_info { 75 unsigned num_channels; 76 unsigned num_banks; 77 unsigned group_bytes; 78}; 79 80struct r600_resource { 81 struct u_vbuf_resource b; 82 83 /* Winsys objects. */ 84 struct pb_buffer *buf; 85 struct radeon_winsys_cs_handle *cs_buf; 86 87 /* Resource state. */ 88 unsigned domains; 89}; 90 91/* R600/R700 STATES */ 92#define R600_GROUP_MAX 16 93#define R600_BLOCK_MAX_BO 32 94#define R600_BLOCK_MAX_REG 128 95 96/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ 97/* there is a block entry for each register so 512 blocks */ 98/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ 99/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ 100#define RANGE_OFFSET_START 0x8000 101#define HASH_SHIFT 9 102#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ 103 104#define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) 105#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) 106 107struct r600_pipe_reg { 108 uint32_t value; 109 struct r600_block *block; 110 struct r600_resource *bo; 111 enum radeon_bo_usage bo_usage; 112 uint32_t id; 113}; 114 115struct r600_pipe_state { 116 unsigned id; 117 unsigned nregs; 118 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG]; 119}; 120 121struct r600_pipe_resource_state { 122 unsigned id; 123 uint32_t val[8]; 124 struct r600_resource *bo[2]; 125 enum radeon_bo_usage bo_usage[2]; 126}; 127 128#define R600_BLOCK_STATUS_ENABLED (1 << 0) 129#define R600_BLOCK_STATUS_DIRTY (1 << 1) 130#define R600_BLOCK_STATUS_RESOURCE_DIRTY (1 << 2) 131 132#define R600_BLOCK_STATUS_RESOURCE_VERTEX (1 << 3) 133 134struct r600_block_reloc { 135 struct r600_resource *bo; 136 enum radeon_bo_usage bo_usage; 137 unsigned bo_pm4_index; 138}; 139 140struct r600_block { 141 struct list_head list; 142 struct list_head enable_list; 143 unsigned status; 144 unsigned flags; 145 unsigned start_offset; 146 unsigned pm4_ndwords; 147 unsigned nbo; 148 uint16_t nreg; 149 uint16_t nreg_dirty; 150 uint32_t *reg; 151 uint32_t pm4[R600_BLOCK_MAX_REG]; 152 unsigned pm4_bo_index[R600_BLOCK_MAX_REG]; 153 struct r600_block_reloc reloc[R600_BLOCK_MAX_BO]; 154}; 155 156struct r600_range { 157 struct r600_block **blocks; 158}; 159 160struct r600_query { 161 union { 162 uint64_t u64; 163 boolean b; 164 struct pipe_query_data_so_statistics so; 165 } result; 166 /* The kind of query */ 167 unsigned type; 168 /* Offset of the first result for current query */ 169 unsigned results_start; 170 /* Offset of the next free result after current query data */ 171 unsigned results_end; 172 /* Size of the result in memory for both begin_query and end_query, 173 * this can be one or two numbers, or it could even be a size of a structure. */ 174 unsigned result_size; 175 /* The buffer where query results are stored. It's used as a ring, 176 * data blocks for current query are stored sequentially from 177 * results_start to results_end, with wrapping on the buffer end */ 178 struct r600_resource *buffer; 179 /* The number of dwords for begin_query or end_query. */ 180 unsigned num_cs_dw; 181 /* linked list of queries */ 182 struct list_head list; 183}; 184 185struct r600_so_target { 186 struct pipe_stream_output_target b; 187 188 /* The buffer where BUFFER_FILLED_SIZE is stored. */ 189 struct r600_resource *filled_size; 190 unsigned stride_in_dw; 191 unsigned so_index; 192}; 193 194#define R600_CONTEXT_DRAW_PENDING (1 << 0) 195#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) 196#define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) 197 198struct r600_draw { 199 uint32_t vgt_num_indices; 200 uint32_t vgt_num_instances; 201 uint32_t vgt_index_type; 202 uint32_t vgt_draw_initiator; 203 uint32_t indices_bo_offset; 204 unsigned db_render_override; 205 unsigned db_render_control; 206 struct r600_resource *indices; 207}; 208 209struct r600_context; 210struct r600_screen; 211 212void r600_get_backend_mask(struct r600_context *ctx); 213int r600_context_init(struct r600_context *ctx); 214void r600_context_fini(struct r600_context *ctx); 215void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state); 216void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 217void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 218void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 219void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 220void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 221void r600_context_flush(struct r600_context *ctx, unsigned flags); 222void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 223 224struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type); 225void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query); 226boolean r600_context_query_result(struct r600_context *ctx, 227 struct r600_query *query, 228 boolean wait, void *vresult); 229void r600_query_begin(struct r600_context *ctx, struct r600_query *query); 230void r600_query_end(struct r600_context *ctx, struct r600_query *query); 231void r600_context_queries_suspend(struct r600_context *ctx); 232void r600_context_queries_resume(struct r600_context *ctx); 233void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, 234 int flag_wait); 235void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence, 236 unsigned offset, unsigned value); 237void r600_inval_shader_cache(struct r600_context *ctx); 238void r600_inval_texture_cache(struct r600_context *ctx); 239void r600_inval_vertex_cache(struct r600_context *ctx); 240void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now); 241 242void r600_context_streamout_begin(struct r600_context *ctx); 243void r600_context_streamout_end(struct r600_context *ctx); 244void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t); 245void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); 246void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block); 247void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block); 248 249int evergreen_context_init(struct r600_context *ctx); 250void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 251void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 252void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 253void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 254void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 255void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 256 257void _r600_pipe_state_add_reg(struct r600_context *ctx, 258 struct r600_pipe_state *state, 259 uint32_t offset, uint32_t value, 260 uint32_t range_id, uint32_t block_id, 261 struct r600_resource *bo, 262 enum radeon_bo_usage usage); 263 264void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, 265 uint32_t offset, uint32_t value, 266 struct r600_resource *bo, 267 enum radeon_bo_usage usage); 268 269#define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage) 270 271static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state, 272 uint32_t value) 273{ 274 state->regs[state->nregs].value = value; 275 state->nregs++; 276} 277 278static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state, 279 uint32_t value, struct r600_resource *bo, 280 enum radeon_bo_usage usage) 281{ 282 state->regs[state->nregs].value = value; 283 state->regs[state->nregs].bo = bo; 284 state->regs[state->nregs].bo_usage = usage; 285 state->nregs++; 286} 287 288#endif 289