r600.h revision eaae63b7155f1fd00fe36a3db4cb8b94aa5ad7b2
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_H 27#define R600_H 28 29#include <assert.h> 30#include <stdint.h> 31#include <stdio.h> 32#include <util/u_double_list.h> 33#include <pipe/p_compiler.h> 34 35#define RADEON_CTX_MAX_PM4 (64 * 1024 / 4) 36 37#define R600_ERR(fmt, args...) \ 38 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) 39 40typedef uint64_t u64; 41typedef uint32_t u32; 42typedef uint16_t u16; 43typedef uint8_t u8; 44 45struct radeon; 46struct winsys_handle; 47 48enum radeon_family { 49 CHIP_UNKNOWN, 50 CHIP_R100, 51 CHIP_RV100, 52 CHIP_RS100, 53 CHIP_RV200, 54 CHIP_RS200, 55 CHIP_R200, 56 CHIP_RV250, 57 CHIP_RS300, 58 CHIP_RV280, 59 CHIP_R300, 60 CHIP_R350, 61 CHIP_RV350, 62 CHIP_RV370, 63 CHIP_RV380, 64 CHIP_R420, 65 CHIP_R423, 66 CHIP_R430, 67 CHIP_R480, 68 CHIP_R481, 69 CHIP_RV410, 70 CHIP_RS400, 71 CHIP_RC410, 72 CHIP_RS480, 73 CHIP_RS600, 74 CHIP_RS690, 75 CHIP_RS740, 76 CHIP_RV515, 77 CHIP_R520, 78 CHIP_RV530, 79 CHIP_RV560, 80 CHIP_RV570, 81 CHIP_R580, 82 CHIP_R600, 83 CHIP_RV610, 84 CHIP_RV630, 85 CHIP_RV670, 86 CHIP_RV620, 87 CHIP_RV635, 88 CHIP_RS780, 89 CHIP_RS880, 90 CHIP_RV770, 91 CHIP_RV730, 92 CHIP_RV710, 93 CHIP_RV740, 94 CHIP_CEDAR, 95 CHIP_REDWOOD, 96 CHIP_JUNIPER, 97 CHIP_CYPRESS, 98 CHIP_HEMLOCK, 99 CHIP_PALM, 100 CHIP_SUMO, 101 CHIP_SUMO2, 102 CHIP_BARTS, 103 CHIP_TURKS, 104 CHIP_CAICOS, 105 CHIP_CAYMAN, 106 CHIP_LAST, 107}; 108 109enum chip_class { 110 R600, 111 R700, 112 EVERGREEN, 113 CAYMAN, 114}; 115 116struct r600_tiling_info { 117 unsigned num_channels; 118 unsigned num_banks; 119 unsigned group_bytes; 120}; 121 122enum radeon_family r600_get_family(struct radeon *rw); 123enum chip_class r600_get_family_class(struct radeon *radeon); 124struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon); 125unsigned r600_get_clock_crystal_freq(struct radeon *radeon); 126unsigned r600_get_minor_version(struct radeon *radeon); 127unsigned r600_get_num_backends(struct radeon *radeon); 128 129/* r600_bo.c */ 130struct r600_bo; 131struct r600_bo *r600_bo(struct radeon *radeon, 132 unsigned size, unsigned alignment, 133 unsigned binding, unsigned usage); 134struct r600_bo *r600_bo_handle(struct radeon *radeon, 135 unsigned handle, unsigned *array_mode); 136void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx); 137void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo); 138void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, 139 struct r600_bo *src); 140boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo, 141 unsigned stride, struct winsys_handle *whandle); 142static INLINE unsigned r600_bo_offset(struct r600_bo *bo) 143{ 144 return 0; 145} 146 147 148/* R600/R700 STATES */ 149#define R600_GROUP_MAX 16 150#define R600_BLOCK_MAX_BO 32 151#define R600_BLOCK_MAX_REG 128 152 153/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ 154/* there is a block entry for each register so 512 blocks */ 155/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ 156/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ 157#define RANGE_OFFSET_START 0x8000 158#define HASH_SHIFT 9 159#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ 160 161#define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) 162#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) 163 164struct r600_pipe_reg { 165 u32 value; 166 u32 mask; 167 struct r600_block *block; 168 struct r600_bo *bo; 169 u32 id; 170}; 171 172struct r600_pipe_state { 173 unsigned id; 174 unsigned nregs; 175 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG]; 176}; 177 178struct r600_pipe_resource_state { 179 unsigned id; 180 u32 val[8]; 181 struct r600_bo *bo[2]; 182}; 183 184#define R600_BLOCK_STATUS_ENABLED (1 << 0) 185#define R600_BLOCK_STATUS_DIRTY (1 << 1) 186 187struct r600_block_reloc { 188 struct r600_bo *bo; 189 unsigned flush_flags; 190 unsigned flush_mask; 191 unsigned bo_pm4_index; 192}; 193 194struct r600_block { 195 struct list_head list; 196 struct list_head enable_list; 197 unsigned status; 198 unsigned flags; 199 unsigned start_offset; 200 unsigned pm4_ndwords; 201 unsigned pm4_flush_ndwords; 202 unsigned nbo; 203 u16 nreg; 204 u16 nreg_dirty; 205 u32 *reg; 206 u32 pm4[R600_BLOCK_MAX_REG]; 207 unsigned pm4_bo_index[R600_BLOCK_MAX_REG]; 208 struct r600_block_reloc reloc[R600_BLOCK_MAX_BO]; 209}; 210 211struct r600_range { 212 struct r600_block **blocks; 213}; 214 215/* 216 * relocation 217 */ 218#pragma pack(1) 219struct r600_reloc { 220 uint32_t handle; 221 uint32_t read_domain; 222 uint32_t write_domain; 223 uint32_t flags; 224}; 225#pragma pack() 226 227/* 228 * query 229 */ 230struct r600_query { 231 u64 result; 232 /* The kind of query. Currently only OQ is supported. */ 233 unsigned type; 234 /* How many results have been written, in dwords. It's incremented 235 * after end_query and flush. */ 236 unsigned num_results; 237 /* if we've flushed the query */ 238 unsigned state; 239 /* The buffer where query results are stored. */ 240 struct r600_bo *buffer; 241 unsigned buffer_size; 242 /* linked list of queries */ 243 struct list_head list; 244}; 245 246#define R600_QUERY_STATE_STARTED (1 << 0) 247#define R600_QUERY_STATE_ENDED (1 << 1) 248#define R600_QUERY_STATE_SUSPENDED (1 << 2) 249 250#define R600_CONTEXT_DRAW_PENDING (1 << 0) 251#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) 252#define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) 253 254struct r600_context { 255 struct radeon *radeon; 256 struct r600_range *range; 257 unsigned nblocks; 258 struct r600_block **blocks; 259 struct list_head dirty; 260 struct list_head enable_list; 261 unsigned pm4_ndwords; 262 unsigned pm4_cdwords; 263 unsigned pm4_dirty_cdwords; 264 unsigned ctx_pm4_ndwords; 265 unsigned nreloc; 266 unsigned creloc; 267 struct r600_reloc *reloc; 268 struct radeon_bo **bo; 269 u32 *pm4; 270 struct list_head query_list; 271 unsigned num_query_running; 272 struct list_head fenced_bo; 273 unsigned max_db; /* for OQ */ 274 unsigned num_dest_buffers; 275 unsigned flags; 276 boolean predicate_drawing; 277 struct r600_range ps_resources; 278 struct r600_range vs_resources; 279 struct r600_range fs_resources; 280 int num_ps_resources, num_vs_resources, num_fs_resources; 281}; 282 283struct r600_draw { 284 u32 vgt_num_indices; 285 u32 vgt_num_instances; 286 u32 vgt_index_type; 287 u32 vgt_draw_initiator; 288 u32 indices_bo_offset; 289 struct r600_bo *indices; 290}; 291 292int r600_context_init(struct r600_context *ctx, struct radeon *radeon); 293void r600_context_fini(struct r600_context *ctx); 294void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state); 295void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 296void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 297void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 298void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 299void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 300void r600_context_flush(struct r600_context *ctx); 301void r600_context_dump_bof(struct r600_context *ctx, const char *file); 302void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 303 304struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type); 305void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query); 306boolean r600_context_query_result(struct r600_context *ctx, 307 struct r600_query *query, 308 boolean wait, void *vresult); 309void r600_query_begin(struct r600_context *ctx, struct r600_query *query); 310void r600_query_end(struct r600_context *ctx, struct r600_query *query); 311void r600_context_queries_suspend(struct r600_context *ctx); 312void r600_context_queries_resume(struct r600_context *ctx); 313void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, 314 int flag_wait); 315void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence, 316 unsigned offset, unsigned value); 317void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags); 318void r600_context_flush_dest_caches(struct r600_context *ctx); 319 320int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon); 321void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 322void evergreen_context_flush_dest_caches(struct r600_context *ctx); 323void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 324void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 325void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 326void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 327void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 328 329struct radeon *radeon_decref(struct radeon *radeon); 330 331void _r600_pipe_state_add_reg(struct r600_context *ctx, 332 struct r600_pipe_state *state, 333 u32 offset, u32 value, u32 mask, 334 u32 range_id, u32 block_id, 335 struct r600_bo *bo); 336 337void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, 338 u32 offset, u32 value, u32 mask, 339 struct r600_bo *bo); 340#define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo) 341 342static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state, 343 u32 value) 344{ 345 state->regs[state->nregs].value = value; 346 state->nregs++; 347} 348 349static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state, 350 u32 value, struct r600_bo *bo) 351{ 352 state->regs[state->nregs].value = value; 353 state->regs[state->nregs].bo = bo; 354 state->nregs++; 355} 356 357#endif 358