r600.h revision fba685a0995e76f86af5920163297e5c3b32fb4b
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_H 27#define R600_H 28 29#include "../../winsys/radeon/drm/radeon_winsys.h" 30#include "util/u_double_list.h" 31#include "util/u_vbuf.h" 32 33#define R600_ERR(fmt, args...) \ 34 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) 35 36typedef uint64_t u64; 37typedef uint32_t u32; 38typedef uint16_t u16; 39typedef uint8_t u8; 40 41struct winsys_handle; 42 43enum radeon_family { 44 CHIP_UNKNOWN, 45 CHIP_R600, 46 CHIP_RV610, 47 CHIP_RV630, 48 CHIP_RV670, 49 CHIP_RV620, 50 CHIP_RV635, 51 CHIP_RS780, 52 CHIP_RS880, 53 CHIP_RV770, 54 CHIP_RV730, 55 CHIP_RV710, 56 CHIP_RV740, 57 CHIP_CEDAR, 58 CHIP_REDWOOD, 59 CHIP_JUNIPER, 60 CHIP_CYPRESS, 61 CHIP_HEMLOCK, 62 CHIP_PALM, 63 CHIP_SUMO, 64 CHIP_SUMO2, 65 CHIP_BARTS, 66 CHIP_TURKS, 67 CHIP_CAICOS, 68 CHIP_CAYMAN, 69 CHIP_LAST, 70}; 71 72enum chip_class { 73 R600, 74 R700, 75 EVERGREEN, 76 CAYMAN, 77}; 78 79struct r600_tiling_info { 80 unsigned num_channels; 81 unsigned num_banks; 82 unsigned group_bytes; 83}; 84 85struct r600_resource { 86 struct u_vbuf_resource b; 87 88 /* Winsys objects. */ 89 struct pb_buffer *buf; 90 struct radeon_winsys_cs_handle *cs_buf; 91}; 92 93/* R600/R700 STATES */ 94#define R600_GROUP_MAX 16 95#define R600_BLOCK_MAX_BO 32 96#define R600_BLOCK_MAX_REG 128 97 98/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ 99/* there is a block entry for each register so 512 blocks */ 100/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ 101/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ 102#define RANGE_OFFSET_START 0x8000 103#define HASH_SHIFT 9 104#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ 105 106#define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) 107#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) 108 109struct r600_pipe_reg { 110 u32 value; 111 u32 mask; 112 struct r600_block *block; 113 struct r600_resource *bo; 114 enum radeon_bo_usage bo_usage; 115 u32 id; 116}; 117 118struct r600_pipe_state { 119 unsigned id; 120 unsigned nregs; 121 struct r600_pipe_reg regs[R600_BLOCK_MAX_REG]; 122}; 123 124struct r600_pipe_resource_state { 125 unsigned id; 126 u32 val[8]; 127 struct r600_resource *bo[2]; 128 enum radeon_bo_usage bo_usage[2]; 129}; 130 131#define R600_BLOCK_STATUS_ENABLED (1 << 0) 132#define R600_BLOCK_STATUS_DIRTY (1 << 1) 133#define R600_BLOCK_STATUS_RESOURCE_DIRTY (1 << 2) 134 135#define R600_BLOCK_STATUS_RESOURCE_VERTEX (1 << 3) 136 137struct r600_block_reloc { 138 struct r600_resource *bo; 139 enum radeon_bo_usage bo_usage; 140 unsigned flush_flags; 141 unsigned flush_mask; 142 unsigned bo_pm4_index; 143}; 144 145struct r600_block { 146 struct list_head list; 147 struct list_head enable_list; 148 unsigned status; 149 unsigned flags; 150 unsigned start_offset; 151 unsigned pm4_ndwords; 152 unsigned pm4_flush_ndwords; 153 unsigned nbo; 154 u16 nreg; 155 u16 nreg_dirty; 156 u32 *reg; 157 u32 pm4[R600_BLOCK_MAX_REG]; 158 unsigned pm4_bo_index[R600_BLOCK_MAX_REG]; 159 struct r600_block_reloc reloc[R600_BLOCK_MAX_BO]; 160}; 161 162struct r600_range { 163 struct r600_block **blocks; 164}; 165 166struct r600_query { 167 union { 168 uint64_t u64; 169 boolean b; 170 } result; 171 /* The kind of query */ 172 unsigned type; 173 /* Offset of the first result for current query */ 174 unsigned results_start; 175 /* Offset of the next free result after current query data */ 176 unsigned results_end; 177 /* Size of the result in memory for both begin_query and end_query, 178 * this can be one or two numbers, or it could even be a size of a structure. */ 179 unsigned result_size; 180 /* The buffer where query results are stored. It's used as a ring, 181 * data blocks for current query are stored sequentially from 182 * results_start to results_end, with wrapping on the buffer end */ 183 struct r600_resource *buffer; 184 /* The number of dwords for begin_query or end_query. */ 185 unsigned num_cs_dw; 186 /* linked list of queries */ 187 struct list_head list; 188}; 189 190#define R600_CONTEXT_DRAW_PENDING (1 << 0) 191#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) 192#define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) 193 194struct r600_context { 195 struct r600_screen *screen; 196 struct radeon_winsys *ws; 197 struct radeon_winsys_cs *cs; 198 struct pipe_context *pipe; 199 200 void (*flush)(void *pipe, unsigned flags); 201 202 struct r600_range *range; 203 unsigned nblocks; 204 struct r600_block **blocks; 205 struct list_head dirty; 206 struct list_head resource_dirty; 207 struct list_head enable_list; 208 unsigned pm4_dirty_cdwords; 209 unsigned ctx_pm4_ndwords; 210 unsigned init_dwords; 211 212 unsigned creloc; 213 struct r600_resource **bo; 214 215 u32 *pm4; 216 unsigned pm4_cdwords; 217 218 /* The list of active queries. Only one query of each type can be active. */ 219 struct list_head active_query_list; 220 unsigned num_cs_dw_queries_suspend; 221 222 unsigned backend_mask; 223 unsigned max_db; /* for OQ */ 224 unsigned num_dest_buffers; 225 unsigned flags; 226 boolean predicate_drawing; 227 struct r600_range ps_resources; 228 struct r600_range vs_resources; 229 struct r600_range fs_resources; 230 int num_ps_resources, num_vs_resources, num_fs_resources; 231 boolean have_depth_texture, have_depth_fb; 232}; 233 234struct r600_draw { 235 u32 vgt_num_indices; 236 u32 vgt_num_instances; 237 u32 vgt_index_type; 238 u32 vgt_draw_initiator; 239 u32 indices_bo_offset; 240 struct r600_resource *indices; 241}; 242 243void r600_get_backend_mask(struct r600_context *ctx); 244int r600_context_init(struct r600_context *ctx, struct r600_screen *screen); 245void r600_context_fini(struct r600_context *ctx); 246void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state); 247void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 248void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 249void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 250void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 251void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 252void r600_context_flush(struct r600_context *ctx, unsigned flags); 253void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 254 255struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type); 256void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query); 257boolean r600_context_query_result(struct r600_context *ctx, 258 struct r600_query *query, 259 boolean wait, void *vresult); 260void r600_query_begin(struct r600_context *ctx, struct r600_query *query); 261void r600_query_end(struct r600_context *ctx, struct r600_query *query); 262void r600_context_queries_suspend(struct r600_context *ctx); 263void r600_context_queries_resume(struct r600_context *ctx); 264void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, 265 int flag_wait); 266void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence, 267 unsigned offset, unsigned value); 268void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags); 269void r600_context_flush_dest_caches(struct r600_context *ctx); 270 271int evergreen_context_init(struct r600_context *ctx, struct r600_screen *screen); 272void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw); 273void evergreen_context_flush_dest_caches(struct r600_context *ctx); 274void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 275void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 276void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); 277void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 278void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); 279 280void _r600_pipe_state_add_reg(struct r600_context *ctx, 281 struct r600_pipe_state *state, 282 u32 offset, u32 value, u32 mask, 283 u32 range_id, u32 block_id, 284 struct r600_resource *bo, 285 enum radeon_bo_usage usage); 286 287void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, 288 u32 offset, u32 value, u32 mask, 289 struct r600_resource *bo, 290 enum radeon_bo_usage usage); 291 292#define r600_pipe_state_add_reg(state, offset, value, mask, bo, usage) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage) 293 294static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state, 295 u32 value) 296{ 297 state->regs[state->nregs].value = value; 298 state->nregs++; 299} 300 301static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state, 302 u32 value, struct r600_resource *bo, 303 enum radeon_bo_usage usage) 304{ 305 state->regs[state->nregs].value = value; 306 state->regs[state->nregs].bo = bo; 307 state->regs[state->nregs].bo_usage = usage; 308 state->nregs++; 309} 310 311#endif 312