r600_pipe.h revision 05ea705c7c6212d16fcc9bcf04619ffd4311bb03
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_shader.h" 32#include "r600_resource.h" 33 34#define R600_MAX_CONST_BUFFERS 2 35#define R600_MAX_CONST_BUFFER_SIZE 4096 36 37#ifdef PIPE_ARCH_BIG_ENDIAN 38#define R600_BIG_ENDIAN 1 39#else 40#define R600_BIG_ENDIAN 0 41#endif 42 43enum r600_atom_flags { 44 /* When set, atoms are added at the beginning of the dirty list 45 * instead of the end. */ 46 EMIT_EARLY = (1 << 0) 47}; 48 49/* This encapsulates a state or an operation which can emitted into the GPU 50 * command stream. It's not limited to states only, it can be used for anything 51 * that wants to write commands into the CS (e.g. cache flushes). */ 52struct r600_atom { 53 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 54 55 unsigned num_dw; 56 enum r600_atom_flags flags; 57 bool dirty; 58 59 struct list_head head; 60}; 61 62/* This is an atom containing GPU commands that never change. 63 * This is supposed to be copied directly into the CS. */ 64struct r600_command_buffer { 65 struct r600_atom atom; 66 uint32_t *buf; 67 unsigned max_num_dw; 68}; 69 70struct r600_surface_sync_cmd { 71 struct r600_atom atom; 72 unsigned flush_flags; /* CP_COHER_CNTL */ 73}; 74 75struct r600_db_misc_state { 76 struct r600_atom atom; 77 bool occlusion_query_enabled; 78 bool flush_depthstencil_enabled; 79}; 80 81enum r600_pipe_state_id { 82 R600_PIPE_STATE_BLEND = 0, 83 R600_PIPE_STATE_BLEND_COLOR, 84 R600_PIPE_STATE_CONFIG, 85 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 86 R600_PIPE_STATE_CLIP, 87 R600_PIPE_STATE_SCISSOR, 88 R600_PIPE_STATE_VIEWPORT, 89 R600_PIPE_STATE_RASTERIZER, 90 R600_PIPE_STATE_VGT, 91 R600_PIPE_STATE_FRAMEBUFFER, 92 R600_PIPE_STATE_DSA, 93 R600_PIPE_STATE_STENCIL_REF, 94 R600_PIPE_STATE_PS_SHADER, 95 R600_PIPE_STATE_VS_SHADER, 96 R600_PIPE_STATE_CONSTANT, 97 R600_PIPE_STATE_SAMPLER, 98 R600_PIPE_STATE_RESOURCE, 99 R600_PIPE_STATE_POLYGON_OFFSET, 100 R600_PIPE_STATE_FETCH_SHADER, 101 R600_PIPE_NSTATES 102}; 103 104struct r600_pipe_fences { 105 struct r600_resource *bo; 106 unsigned *data; 107 unsigned next_index; 108 /* linked list of preallocated blocks */ 109 struct list_head blocks; 110 /* linked list of freed fences */ 111 struct list_head pool; 112 pipe_mutex mutex; 113}; 114 115struct r600_screen { 116 struct pipe_screen screen; 117 struct radeon_winsys *ws; 118 unsigned family; 119 enum chip_class chip_class; 120 struct radeon_info info; 121 struct r600_tiling_info tiling_info; 122 struct r600_pipe_fences fences; 123 124 bool use_surface_alloc; 125 int glsl_feature_level; 126}; 127 128struct r600_pipe_sampler_view { 129 struct pipe_sampler_view base; 130 struct r600_pipe_resource_state state; 131}; 132 133struct r600_pipe_rasterizer { 134 struct r600_pipe_state rstate; 135 boolean flatshade; 136 boolean two_side; 137 unsigned sprite_coord_enable; 138 unsigned clip_plane_enable; 139 unsigned pa_sc_line_stipple; 140 unsigned pa_cl_clip_cntl; 141 float offset_units; 142 float offset_scale; 143 bool scissor_enable; 144}; 145 146struct r600_pipe_blend { 147 struct r600_pipe_state rstate; 148 unsigned cb_target_mask; 149 unsigned cb_color_control; 150 bool dual_src_blend; 151}; 152 153struct r600_pipe_dsa { 154 struct r600_pipe_state rstate; 155 unsigned alpha_ref; 156 ubyte valuemask[2]; 157 ubyte writemask[2]; 158 bool is_flush; 159 unsigned sx_alpha_test_control; 160}; 161 162struct r600_vertex_element 163{ 164 unsigned count; 165 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 166 struct r600_resource *fetch_shader; 167 unsigned fs_size; 168 struct r600_pipe_state rstate; 169}; 170 171struct r600_pipe_shader { 172 struct r600_shader shader; 173 struct r600_pipe_state rstate; 174 struct r600_resource *bo; 175 struct r600_resource *bo_fetch; 176 struct r600_vertex_element vertex_elements; 177 struct tgsi_token *tokens; 178 unsigned sprite_coord_enable; 179 unsigned flatshade; 180 unsigned pa_cl_vs_out_cntl; 181 unsigned ps_cb_shader_mask; 182 struct pipe_stream_output_info so; 183}; 184 185struct r600_pipe_sampler_state { 186 struct r600_pipe_state rstate; 187 boolean seamless_cube_map; 188}; 189 190/* needed for blitter save */ 191#define NUM_TEX_UNITS 16 192 193struct r600_textures_info { 194 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 195 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 196 unsigned n_views; 197 unsigned n_samplers; 198 bool samplers_dirty; 199 bool is_array_sampler[NUM_TEX_UNITS]; 200}; 201 202struct r600_fence { 203 struct pipe_reference reference; 204 unsigned index; /* in the shared bo */ 205 struct r600_resource *sleep_bo; 206 struct list_head head; 207}; 208 209#define FENCE_BLOCK_SIZE 16 210 211struct r600_fence_block { 212 struct r600_fence fences[FENCE_BLOCK_SIZE]; 213 struct list_head head; 214}; 215 216#define R600_CONSTANT_ARRAY_SIZE 256 217#define R600_RESOURCE_ARRAY_SIZE 160 218 219struct r600_stencil_ref 220{ 221 ubyte ref_value[2]; 222 ubyte valuemask[2]; 223 ubyte writemask[2]; 224}; 225 226struct r600_constbuf_state 227{ 228 struct r600_atom atom; 229 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 230 uint32_t enabled_mask; 231 uint32_t dirty_mask; 232}; 233 234struct r600_context { 235 struct pipe_context context; 236 struct blitter_context *blitter; 237 enum radeon_family family; 238 enum chip_class chip_class; 239 boolean has_vertex_cache; 240 unsigned r6xx_num_clause_temp_gprs; 241 void *custom_dsa_flush; 242 struct r600_screen *screen; 243 struct radeon_winsys *ws; 244 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 245 struct r600_vertex_element *vertex_elements; 246 struct pipe_framebuffer_state framebuffer; 247 unsigned cb_target_mask; 248 unsigned fb_cb_shader_mask; 249 unsigned sx_alpha_test_control; 250 unsigned cb_shader_mask; 251 unsigned cb_color_control; 252 unsigned pa_sc_line_stipple; 253 unsigned pa_cl_clip_cntl; 254 /* for saving when using blitter */ 255 struct pipe_stencil_ref stencil_ref; 256 struct pipe_viewport_state viewport; 257 struct pipe_clip_state clip; 258 struct r600_pipe_shader *ps_shader; 259 struct r600_pipe_shader *vs_shader; 260 struct r600_pipe_rasterizer *rasterizer; 261 struct r600_pipe_state vgt; 262 struct r600_pipe_state spi; 263 struct pipe_query *current_render_cond; 264 unsigned current_render_cond_mode; 265 struct pipe_query *saved_render_cond; 266 unsigned saved_render_cond_mode; 267 /* shader information */ 268 boolean two_side; 269 unsigned sprite_coord_enable; 270 boolean export_16bpc; 271 unsigned alpha_ref; 272 boolean alpha_ref_dirty; 273 unsigned nr_cbufs; 274 struct r600_textures_info vs_samplers; 275 struct r600_textures_info ps_samplers; 276 277 struct u_upload_mgr *uploader; 278 struct util_slab_mempool pool_transfers; 279 boolean have_depth_texture, have_depth_fb; 280 281 unsigned default_ps_gprs, default_vs_gprs; 282 283 /* States based on r600_atom. */ 284 struct list_head dirty_states; 285 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 286 struct r600_surface_sync_cmd surface_sync_cmd; 287 struct r600_atom r6xx_flush_and_inv_cmd; 288 struct r600_db_misc_state db_misc_state; 289 struct r600_atom vertex_buffer_state; 290 struct r600_constbuf_state vs_constbuf_state; 291 struct r600_constbuf_state ps_constbuf_state; 292 293 struct radeon_winsys_cs *cs; 294 295 struct r600_range *range; 296 unsigned nblocks; 297 struct r600_block **blocks; 298 struct list_head dirty; 299 struct list_head resource_dirty; 300 struct list_head enable_list; 301 unsigned pm4_dirty_cdwords; 302 unsigned ctx_pm4_ndwords; 303 304 /* The list of active queries. Only one query of each type can be active. */ 305 int num_occlusion_queries; 306 307 /* Manage queries in two separate groups: 308 * The timer ones and the others (streamout, occlusion). 309 * 310 * We do this because we should only suspend non-timer queries for u_blitter, 311 * and later if the non-timer queries are suspended, the context flush should 312 * only suspend and resume the timer queries. */ 313 struct list_head active_timer_queries; 314 unsigned num_cs_dw_timer_queries_suspend; 315 struct list_head active_nontimer_queries; 316 unsigned num_cs_dw_nontimer_queries_suspend; 317 318 unsigned num_cs_dw_streamout_end; 319 320 unsigned backend_mask; 321 unsigned max_db; /* for OQ */ 322 unsigned flags; 323 boolean predicate_drawing; 324 struct r600_range ps_resources; 325 struct r600_range vs_resources; 326 int num_ps_resources, num_vs_resources; 327 328 unsigned num_so_targets; 329 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 330 boolean streamout_start; 331 unsigned streamout_append_bitmask; 332 333 /* There is no scissor enable bit on r6xx, so we must use a workaround. 334 * These track the current scissor state. */ 335 bool scissor_enable; 336 struct pipe_scissor_state scissor_state; 337 338 /* With rasterizer discard, there doesn't have to be a pixel shader. 339 * In that case, we bind this one: */ 340 void *dummy_pixel_shader; 341 342 boolean dual_src_blend; 343 344 /* Vertex and index buffers. */ 345 bool vertex_buffers_dirty; 346 struct pipe_index_buffer index_buffer; 347 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; 348 unsigned nr_vertex_buffers; 349}; 350 351static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 352{ 353 atom->emit(rctx, atom); 354 atom->dirty = false; 355 if (atom->head.next && atom->head.prev) 356 LIST_DELINIT(&atom->head); 357} 358 359static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 360{ 361 if (!state->dirty) { 362 if (state->flags & EMIT_EARLY) { 363 LIST_ADD(&state->head, &rctx->dirty_states); 364 } else { 365 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 366 } 367 state->dirty = true; 368 } 369} 370 371/* evergreen_state.c */ 372void evergreen_init_state_functions(struct r600_context *rctx); 373void evergreen_init_atom_start_cs(struct r600_context *rctx); 374void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 375void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 376void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 377void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 378void evergreen_polygon_offset_update(struct r600_context *rctx); 379boolean evergreen_is_format_supported(struct pipe_screen *screen, 380 enum pipe_format format, 381 enum pipe_texture_target target, 382 unsigned sample_count, 383 unsigned usage); 384 385/* r600_blit.c */ 386void r600_init_blit_functions(struct r600_context *rctx); 387void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 388void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 389void r600_flush_depth_textures(struct r600_context *rctx); 390 391/* r600_buffer.c */ 392bool r600_init_resource(struct r600_screen *rscreen, 393 struct r600_resource *res, 394 unsigned size, unsigned alignment, 395 unsigned bind, unsigned usage); 396struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 397 const struct pipe_resource *templ); 398 399/* r600_pipe.c */ 400void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 401 unsigned flags); 402 403/* r600_query.c */ 404void r600_init_query_functions(struct r600_context *rctx); 405void r600_suspend_nontimer_queries(struct r600_context *ctx); 406void r600_resume_nontimer_queries(struct r600_context *ctx); 407void r600_suspend_timer_queries(struct r600_context *ctx); 408void r600_resume_timer_queries(struct r600_context *ctx); 409 410/* r600_resource.c */ 411void r600_init_context_resource_functions(struct r600_context *r600); 412 413/* r600_shader.c */ 414int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 415void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 416int r600_find_vs_semantic_index(struct r600_shader *vs, 417 struct r600_shader *ps, int id); 418 419/* r600_state.c */ 420void r600_set_scissor_state(struct r600_context *rctx, 421 const struct pipe_scissor_state *state); 422void r600_update_sampler_states(struct r600_context *rctx); 423void r600_init_state_functions(struct r600_context *rctx); 424void r600_init_atom_start_cs(struct r600_context *rctx); 425void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 426void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 427void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 428void *r600_create_db_flush_dsa(struct r600_context *rctx); 429void r600_polygon_offset_update(struct r600_context *rctx); 430void r600_adjust_gprs(struct r600_context *rctx); 431boolean r600_is_format_supported(struct pipe_screen *screen, 432 enum pipe_format format, 433 enum pipe_texture_target target, 434 unsigned sample_count, 435 unsigned usage); 436 437/* r600_texture.c */ 438void r600_init_screen_texture_functions(struct pipe_screen *screen); 439void r600_init_surface_functions(struct r600_context *r600); 440uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 441 const unsigned char *swizzle_view, 442 uint32_t *word4_p, uint32_t *yuv_format_p); 443unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 444 unsigned level, unsigned layer); 445 446/* r600_translate.c */ 447void r600_translate_index_buffer(struct r600_context *r600, 448 struct pipe_index_buffer *ib, 449 unsigned count); 450 451/* r600_state_common.c */ 452void r600_init_atom(struct r600_atom *atom, 453 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 454 unsigned num_dw, enum r600_atom_flags flags); 455void r600_init_common_atoms(struct r600_context *rctx); 456unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 457void r600_texture_barrier(struct pipe_context *ctx); 458void r600_set_index_buffer(struct pipe_context *ctx, 459 const struct pipe_index_buffer *ib); 460void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 461 const struct pipe_vertex_buffer *buffers); 462void *r600_create_vertex_elements(struct pipe_context *ctx, 463 unsigned count, 464 const struct pipe_vertex_element *elements); 465void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 466void r600_bind_blend_state(struct pipe_context *ctx, void *state); 467void r600_set_blend_color(struct pipe_context *ctx, 468 const struct pipe_blend_color *state); 469void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 470void r600_set_max_scissor(struct r600_context *rctx); 471void r600_bind_rs_state(struct pipe_context *ctx, void *state); 472void r600_delete_rs_state(struct pipe_context *ctx, void *state); 473void r600_sampler_view_destroy(struct pipe_context *ctx, 474 struct pipe_sampler_view *state); 475void r600_delete_state(struct pipe_context *ctx, void *state); 476void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 477void *r600_create_shader_state(struct pipe_context *ctx, 478 const struct pipe_shader_state *state); 479void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 480void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 481void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 482void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 483void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 484void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 485 struct pipe_constant_buffer *cb); 486struct pipe_stream_output_target * 487r600_create_so_target(struct pipe_context *ctx, 488 struct pipe_resource *buffer, 489 unsigned buffer_offset, 490 unsigned buffer_size); 491void r600_so_target_destroy(struct pipe_context *ctx, 492 struct pipe_stream_output_target *target); 493void r600_set_so_targets(struct pipe_context *ctx, 494 unsigned num_targets, 495 struct pipe_stream_output_target **targets, 496 unsigned append_bitmask); 497void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 498 const struct pipe_stencil_ref *state); 499void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 500uint32_t r600_translate_stencil_op(int s_op); 501uint32_t r600_translate_fill(uint32_t func); 502unsigned r600_tex_wrap(unsigned wrap); 503unsigned r600_tex_filter(unsigned filter); 504unsigned r600_tex_mipfilter(unsigned filter); 505unsigned r600_tex_compare(unsigned compare); 506 507/* 508 * Helpers for building command buffers 509 */ 510 511#define PKT3_SET_CONFIG_REG 0x68 512#define PKT3_SET_CONTEXT_REG 0x69 513#define PKT3_SET_CTL_CONST 0x6F 514#define PKT3_SET_LOOP_CONST 0x6C 515 516#define R600_CONFIG_REG_OFFSET 0x08000 517#define R600_CONTEXT_REG_OFFSET 0x28000 518#define R600_CTL_CONST_OFFSET 0x3CFF0 519#define R600_LOOP_CONST_OFFSET 0X0003E200 520#define EG_LOOP_CONST_OFFSET 0x0003A200 521 522#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 523#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 524#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 525#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 526#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 527 528static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 529{ 530 cb->buf[cb->atom.num_dw++] = value; 531} 532 533static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 534{ 535 assert(reg < R600_CONTEXT_REG_OFFSET); 536 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 537 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 538 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 539} 540 541static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 542{ 543 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 544 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 545 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 546 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 547} 548 549static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 550{ 551 assert(reg >= R600_CTL_CONST_OFFSET); 552 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 553 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 554 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 555} 556 557static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 558{ 559 assert(reg >= R600_LOOP_CONST_OFFSET); 560 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 561 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 562 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 563} 564 565static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 566{ 567 assert(reg >= EG_LOOP_CONST_OFFSET); 568 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 569 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 570 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 571} 572 573static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 574{ 575 r600_store_config_reg_seq(cb, reg, 1); 576 r600_store_value(cb, value); 577} 578 579static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 580{ 581 r600_store_context_reg_seq(cb, reg, 1); 582 r600_store_value(cb, value); 583} 584 585static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 586{ 587 r600_store_ctl_const_seq(cb, reg, 1); 588 r600_store_value(cb, value); 589} 590 591static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 592{ 593 r600_store_loop_const_seq(cb, reg, 1); 594 r600_store_value(cb, value); 595} 596 597static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 598{ 599 eg_store_loop_const_seq(cb, reg, 1); 600 r600_store_value(cb, value); 601} 602 603void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 604void r600_release_command_buffer(struct r600_command_buffer *cb); 605 606/* 607 * Helpers for emitting state into a command stream directly. 608 */ 609 610static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 611 enum radeon_bo_usage usage) 612{ 613 assert(usage); 614 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 615} 616 617static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 618{ 619 cs->buf[cs->cdw++] = value; 620} 621 622static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 623{ 624 assert(reg < R600_CONTEXT_REG_OFFSET); 625 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 626 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 627 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 628} 629 630static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 631{ 632 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 633 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 634 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 635 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 636} 637 638static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 639{ 640 assert(reg >= R600_CTL_CONST_OFFSET); 641 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 642 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 643 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 644} 645 646static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 647{ 648 r600_write_config_reg_seq(cs, reg, 1); 649 r600_write_value(cs, value); 650} 651 652static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 653{ 654 r600_write_context_reg_seq(cs, reg, 1); 655 r600_write_value(cs, value); 656} 657 658static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 659{ 660 r600_write_ctl_const_seq(cs, reg, 1); 661 r600_write_value(cs, value); 662} 663 664/* 665 * common helpers 666 */ 667static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 668{ 669 return value * (1 << frac_bits); 670} 671#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 672 673static inline unsigned r600_tex_aniso_filter(unsigned filter) 674{ 675 if (filter <= 1) return 0; 676 if (filter <= 2) return 1; 677 if (filter <= 4) return 2; 678 if (filter <= 8) return 3; 679 /* else */ return 4; 680} 681 682/* 12.4 fixed-point */ 683static INLINE unsigned r600_pack_float_12p4(float x) 684{ 685 return x <= 0 ? 0 : 686 x >= 4096 ? 0xffff : x * 16; 687} 688 689static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 690{ 691 struct r600_screen *rscreen = (struct r600_screen*)screen; 692 struct r600_resource *rresource = (struct r600_resource*)resource; 693 694 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 695} 696 697#endif 698