r600_pipe.h revision 09ec30f02830b3cbf9d6ac04d9497634dca86846
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "../../winsys/radeon/drm/radeon_winsys.h" 30 31#include "pipe/p_state.h" 32#include "pipe/p_screen.h" 33#include "pipe/p_context.h" 34#include "util/u_math.h" 35#include "util/u_slab.h" 36#include "util/u_vbuf.h" 37#include "r600.h" 38#include "r600_public.h" 39#include "r600_shader.h" 40#include "r600_resource.h" 41 42#define R600_MAX_CONST_BUFFERS 2 43#define R600_MAX_CONST_BUFFER_SIZE 4096 44 45#ifdef PIPE_ARCH_BIG_ENDIAN 46#define R600_BIG_ENDIAN 1 47#else 48#define R600_BIG_ENDIAN 0 49#endif 50 51enum r600_atom_flags { 52 /* When set, atoms are added at the beginning of the dirty list 53 * instead of the end. */ 54 EMIT_EARLY = (1 << 0) 55}; 56 57/* This encapsulates a state or an operation which can emitted into the GPU 58 * command stream. It's not limited to states only, it can be used for anything 59 * that wants to write commands into the CS (e.g. cache flushes). */ 60struct r600_atom { 61 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 62 63 unsigned num_dw; 64 enum r600_atom_flags flags; 65 bool dirty; 66 67 struct list_head head; 68}; 69 70/* This is an atom containing GPU commands that never change. 71 * This is supposed to be copied directly into the CS. */ 72struct r600_command_buffer { 73 struct r600_atom atom; 74 uint32_t *buf; 75 unsigned max_num_dw; 76}; 77 78struct r600_atom_surface_sync { 79 struct r600_atom atom; 80 unsigned flush_flags; /* CP_COHER_CNTL */ 81}; 82 83struct r600_atom_db_misc_state { 84 struct r600_atom atom; 85 bool occlusion_query_enabled; 86 bool flush_depthstencil_enabled; 87}; 88 89enum r600_pipe_state_id { 90 R600_PIPE_STATE_BLEND = 0, 91 R600_PIPE_STATE_BLEND_COLOR, 92 R600_PIPE_STATE_CONFIG, 93 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 94 R600_PIPE_STATE_CLIP, 95 R600_PIPE_STATE_SCISSOR, 96 R600_PIPE_STATE_VIEWPORT, 97 R600_PIPE_STATE_RASTERIZER, 98 R600_PIPE_STATE_VGT, 99 R600_PIPE_STATE_FRAMEBUFFER, 100 R600_PIPE_STATE_DSA, 101 R600_PIPE_STATE_STENCIL_REF, 102 R600_PIPE_STATE_PS_SHADER, 103 R600_PIPE_STATE_VS_SHADER, 104 R600_PIPE_STATE_CONSTANT, 105 R600_PIPE_STATE_SAMPLER, 106 R600_PIPE_STATE_RESOURCE, 107 R600_PIPE_STATE_POLYGON_OFFSET, 108 R600_PIPE_STATE_FETCH_SHADER, 109 R600_PIPE_NSTATES 110}; 111 112struct r600_pipe_fences { 113 struct r600_resource *bo; 114 unsigned *data; 115 unsigned next_index; 116 /* linked list of preallocated blocks */ 117 struct list_head blocks; 118 /* linked list of freed fences */ 119 struct list_head pool; 120 pipe_mutex mutex; 121}; 122 123struct r600_screen { 124 struct pipe_screen screen; 125 struct radeon_winsys *ws; 126 unsigned family; 127 enum chip_class chip_class; 128 struct radeon_info info; 129 struct r600_tiling_info tiling_info; 130 struct util_slab_mempool pool_buffers; 131 struct r600_pipe_fences fences; 132 133 unsigned num_contexts; 134 bool use_surface_alloc; 135 136 /* for thread-safe write accessing to num_contexts */ 137 pipe_mutex mutex_num_contexts; 138}; 139 140struct r600_pipe_sampler_view { 141 struct pipe_sampler_view base; 142 struct r600_pipe_resource_state state; 143}; 144 145struct r600_pipe_rasterizer { 146 struct r600_pipe_state rstate; 147 boolean flatshade; 148 boolean two_side; 149 unsigned sprite_coord_enable; 150 unsigned clip_plane_enable; 151 unsigned pa_sc_line_stipple; 152 unsigned pa_cl_clip_cntl; 153 float offset_units; 154 float offset_scale; 155}; 156 157struct r600_pipe_blend { 158 struct r600_pipe_state rstate; 159 unsigned cb_target_mask; 160 unsigned cb_color_control; 161}; 162 163struct r600_pipe_dsa { 164 struct r600_pipe_state rstate; 165 unsigned alpha_ref; 166 ubyte valuemask[2]; 167 ubyte writemask[2]; 168 bool is_flush; 169}; 170 171struct r600_vertex_element 172{ 173 unsigned count; 174 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 175 struct u_vbuf_elements *vmgr_elements; 176 struct r600_resource *fetch_shader; 177 unsigned fs_size; 178 struct r600_pipe_state rstate; 179 /* if offset is to big for fetch instructio we need to alterate 180 * offset of vertex buffer, record here the offset need to add 181 */ 182 unsigned vbuffer_need_offset; 183 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS]; 184}; 185 186struct r600_pipe_shader { 187 struct r600_shader shader; 188 struct r600_pipe_state rstate; 189 struct r600_resource *bo; 190 struct r600_resource *bo_fetch; 191 struct r600_vertex_element vertex_elements; 192 struct tgsi_token *tokens; 193 unsigned sprite_coord_enable; 194 unsigned flatshade; 195 unsigned pa_cl_vs_out_cntl; 196 struct pipe_stream_output_info so; 197}; 198 199struct r600_pipe_sampler_state { 200 struct r600_pipe_state rstate; 201 boolean seamless_cube_map; 202}; 203 204/* needed for blitter save */ 205#define NUM_TEX_UNITS 16 206 207struct r600_textures_info { 208 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 209 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 210 unsigned n_views; 211 unsigned n_samplers; 212 bool samplers_dirty; 213 bool is_array_sampler[NUM_TEX_UNITS]; 214}; 215 216struct r600_fence { 217 struct pipe_reference reference; 218 unsigned index; /* in the shared bo */ 219 struct r600_resource *sleep_bo; 220 struct list_head head; 221}; 222 223#define FENCE_BLOCK_SIZE 16 224 225struct r600_fence_block { 226 struct r600_fence fences[FENCE_BLOCK_SIZE]; 227 struct list_head head; 228}; 229 230#define R600_CONSTANT_ARRAY_SIZE 256 231#define R600_RESOURCE_ARRAY_SIZE 160 232 233struct r600_stencil_ref 234{ 235 ubyte ref_value[2]; 236 ubyte valuemask[2]; 237 ubyte writemask[2]; 238}; 239 240struct r600_context { 241 struct pipe_context context; 242 struct blitter_context *blitter; 243 enum radeon_family family; 244 enum chip_class chip_class; 245 unsigned r6xx_num_clause_temp_gprs; 246 void *custom_dsa_flush; 247 struct r600_screen *screen; 248 struct radeon_winsys *ws; 249 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 250 struct r600_vertex_element *vertex_elements; 251 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS]; 252 struct pipe_framebuffer_state framebuffer; 253 unsigned cb_target_mask; 254 unsigned cb_color_control; 255 unsigned pa_sc_line_stipple; 256 unsigned pa_cl_clip_cntl; 257 /* for saving when using blitter */ 258 struct pipe_stencil_ref stencil_ref; 259 struct pipe_viewport_state viewport; 260 struct pipe_clip_state clip; 261 struct r600_pipe_shader *ps_shader; 262 struct r600_pipe_shader *vs_shader; 263 struct r600_pipe_state vs_const_buffer; 264 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 265 struct r600_pipe_state ps_const_buffer; 266 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 267 struct r600_pipe_rasterizer *rasterizer; 268 struct r600_pipe_state vgt; 269 struct r600_pipe_state spi; 270 struct pipe_query *current_render_cond; 271 unsigned current_render_cond_mode; 272 struct pipe_query *saved_render_cond; 273 unsigned saved_render_cond_mode; 274 /* shader information */ 275 boolean two_side; 276 unsigned sprite_coord_enable; 277 boolean export_16bpc; 278 unsigned alpha_ref; 279 boolean alpha_ref_dirty; 280 unsigned nr_cbufs; 281 struct r600_textures_info vs_samplers; 282 struct r600_textures_info ps_samplers; 283 284 struct u_vbuf *vbuf_mgr; 285 struct util_slab_mempool pool_transfers; 286 boolean have_depth_texture, have_depth_fb; 287 288 unsigned default_ps_gprs, default_vs_gprs; 289 290 /* States based on r600_state. */ 291 struct list_head dirty_states; 292 struct r600_command_buffer atom_start_cs; /* invariant state mostly */ 293 struct r600_atom_surface_sync atom_surface_sync; 294 struct r600_atom atom_r6xx_flush_and_inv; 295 struct r600_atom_db_misc_state atom_db_misc_state; 296 297 /* Below are variables from the old r600_context. 298 */ 299 struct radeon_winsys_cs *cs; 300 301 struct r600_range *range; 302 unsigned nblocks; 303 struct r600_block **blocks; 304 struct list_head dirty; 305 struct list_head resource_dirty; 306 struct list_head enable_list; 307 unsigned pm4_dirty_cdwords; 308 unsigned ctx_pm4_ndwords; 309 310 /* The list of active queries. Only one query of each type can be active. */ 311 int num_occlusion_queries; 312 313 /* Manage queries in two separate groups: 314 * The timer ones and the others (streamout, occlusion). 315 * 316 * We do this because we should only suspend non-timer queries for u_blitter, 317 * and later if the non-timer queries are suspended, the context flush should 318 * only suspend and resume the timer queries. */ 319 struct list_head active_timer_queries; 320 unsigned num_cs_dw_timer_queries_suspend; 321 struct list_head active_nontimer_queries; 322 unsigned num_cs_dw_nontimer_queries_suspend; 323 324 unsigned num_cs_dw_streamout_end; 325 326 unsigned backend_mask; 327 unsigned max_db; /* for OQ */ 328 unsigned flags; 329 boolean predicate_drawing; 330 struct r600_range ps_resources; 331 struct r600_range vs_resources; 332 struct r600_range fs_resources; 333 int num_ps_resources, num_vs_resources, num_fs_resources; 334 335 unsigned num_so_targets; 336 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 337 boolean streamout_start; 338 unsigned streamout_append_bitmask; 339}; 340 341static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 342{ 343 atom->emit(rctx, atom); 344 atom->dirty = false; 345 if (atom->head.next && atom->head.prev) 346 LIST_DELINIT(&atom->head); 347} 348 349static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 350{ 351 if (!state->dirty) { 352 if (state->flags & EMIT_EARLY) { 353 LIST_ADD(&state->head, &rctx->dirty_states); 354 } else { 355 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 356 } 357 state->dirty = true; 358 } 359} 360 361/* evergreen_state.c */ 362void evergreen_init_state_functions(struct r600_context *rctx); 363void evergreen_init_atom_start_cs(struct r600_context *rctx); 364void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 365void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 366void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 367void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 368void evergreen_polygon_offset_update(struct r600_context *rctx); 369void evergreen_pipe_init_buffer_resource(struct r600_context *rctx, 370 struct r600_pipe_resource_state *rstate); 371void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx, 372 struct r600_pipe_resource_state *rstate, 373 struct r600_resource *rbuffer, 374 unsigned offset, unsigned stride, 375 enum radeon_bo_usage usage); 376boolean evergreen_is_format_supported(struct pipe_screen *screen, 377 enum pipe_format format, 378 enum pipe_texture_target target, 379 unsigned sample_count, 380 unsigned usage); 381 382/* r600_blit.c */ 383void r600_init_blit_functions(struct r600_context *rctx); 384void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 385void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 386void r600_flush_depth_textures(struct r600_context *rctx); 387 388/* r600_buffer.c */ 389bool r600_init_resource(struct r600_screen *rscreen, 390 struct r600_resource *res, 391 unsigned size, unsigned alignment, 392 unsigned bind, unsigned usage); 393struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 394 const struct pipe_resource *templ); 395struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 396 void *ptr, unsigned bytes, 397 unsigned bind); 398void r600_upload_index_buffer(struct r600_context *rctx, 399 struct pipe_index_buffer *ib, unsigned count); 400 401 402/* r600_pipe.c */ 403void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 404 unsigned flags); 405 406/* r600_query.c */ 407void r600_init_query_functions(struct r600_context *rctx); 408void r600_suspend_nontimer_queries(struct r600_context *ctx); 409void r600_resume_nontimer_queries(struct r600_context *ctx); 410void r600_suspend_timer_queries(struct r600_context *ctx); 411void r600_resume_timer_queries(struct r600_context *ctx); 412 413/* r600_resource.c */ 414void r600_init_context_resource_functions(struct r600_context *r600); 415 416/* r600_shader.c */ 417int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 418void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 419int r600_find_vs_semantic_index(struct r600_shader *vs, 420 struct r600_shader *ps, int id); 421 422/* r600_state.c */ 423void r600_update_sampler_states(struct r600_context *rctx); 424void r600_init_state_functions(struct r600_context *rctx); 425void r600_init_atom_start_cs(struct r600_context *rctx); 426void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 427void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 428void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 429void *r600_create_db_flush_dsa(struct r600_context *rctx); 430void r600_polygon_offset_update(struct r600_context *rctx); 431void r600_pipe_init_buffer_resource(struct r600_context *rctx, 432 struct r600_pipe_resource_state *rstate); 433void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 434 struct r600_resource *rbuffer, 435 unsigned offset, unsigned stride, 436 enum radeon_bo_usage usage); 437void r600_adjust_gprs(struct r600_context *rctx); 438boolean r600_is_format_supported(struct pipe_screen *screen, 439 enum pipe_format format, 440 enum pipe_texture_target target, 441 unsigned sample_count, 442 unsigned usage); 443 444/* r600_texture.c */ 445void r600_init_screen_texture_functions(struct pipe_screen *screen); 446void r600_init_surface_functions(struct r600_context *r600); 447uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 448 const unsigned char *swizzle_view, 449 uint32_t *word4_p, uint32_t *yuv_format_p); 450unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 451 unsigned level, unsigned layer); 452 453/* r600_translate.c */ 454void r600_translate_index_buffer(struct r600_context *r600, 455 struct pipe_index_buffer *ib, 456 unsigned count); 457 458/* r600_state_common.c */ 459void r600_init_atom(struct r600_atom *atom, 460 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 461 unsigned num_dw, enum r600_atom_flags flags); 462void r600_init_common_atoms(struct r600_context *rctx); 463unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 464void r600_texture_barrier(struct pipe_context *ctx); 465void r600_set_index_buffer(struct pipe_context *ctx, 466 const struct pipe_index_buffer *ib); 467void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 468 const struct pipe_vertex_buffer *buffers); 469void *r600_create_vertex_elements(struct pipe_context *ctx, 470 unsigned count, 471 const struct pipe_vertex_element *elements); 472void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 473void r600_bind_blend_state(struct pipe_context *ctx, void *state); 474void r600_set_blend_color(struct pipe_context *ctx, 475 const struct pipe_blend_color *state); 476void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 477void r600_bind_rs_state(struct pipe_context *ctx, void *state); 478void r600_delete_rs_state(struct pipe_context *ctx, void *state); 479void r600_sampler_view_destroy(struct pipe_context *ctx, 480 struct pipe_sampler_view *state); 481void r600_delete_state(struct pipe_context *ctx, void *state); 482void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 483void *r600_create_shader_state(struct pipe_context *ctx, 484 const struct pipe_shader_state *state); 485void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 486void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 487void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 488void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 489void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 490 struct pipe_resource *buffer); 491struct pipe_stream_output_target * 492r600_create_so_target(struct pipe_context *ctx, 493 struct pipe_resource *buffer, 494 unsigned buffer_offset, 495 unsigned buffer_size); 496void r600_so_target_destroy(struct pipe_context *ctx, 497 struct pipe_stream_output_target *target); 498void r600_set_so_targets(struct pipe_context *ctx, 499 unsigned num_targets, 500 struct pipe_stream_output_target **targets, 501 unsigned append_bitmask); 502void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 503 const struct pipe_stencil_ref *state); 504void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 505uint32_t r600_translate_stencil_op(int s_op); 506uint32_t r600_translate_fill(uint32_t func); 507unsigned r600_tex_wrap(unsigned wrap); 508unsigned r600_tex_filter(unsigned filter); 509unsigned r600_tex_mipfilter(unsigned filter); 510unsigned r600_tex_compare(unsigned compare); 511 512/* 513 * Helpers for building command buffers 514 */ 515 516#define PKT3_SET_CONFIG_REG 0x68 517#define PKT3_SET_CONTEXT_REG 0x69 518#define PKT3_SET_CTL_CONST 0x6F 519#define PKT3_SET_LOOP_CONST 0x6C 520 521#define R600_CONFIG_REG_OFFSET 0x08000 522#define R600_CONTEXT_REG_OFFSET 0x28000 523#define R600_CTL_CONST_OFFSET 0x3CFF0 524#define R600_LOOP_CONST_OFFSET 0X0003E200 525#define EG_LOOP_CONST_OFFSET 0x0003A200 526 527#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 528#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 529#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 530#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 531#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 532 533static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 534{ 535 cb->buf[cb->atom.num_dw++] = value; 536} 537 538static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 539{ 540 assert(reg < R600_CONTEXT_REG_OFFSET); 541 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 542 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 543 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 544} 545 546static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 547{ 548 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 549 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 550 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 551 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 552} 553 554static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 555{ 556 assert(reg >= R600_CTL_CONST_OFFSET); 557 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 558 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 559 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 560} 561 562static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 563{ 564 assert(reg >= R600_LOOP_CONST_OFFSET); 565 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 566 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 567 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 568} 569 570static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 571{ 572 assert(reg >= EG_LOOP_CONST_OFFSET); 573 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 574 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 575 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 576} 577 578static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 579{ 580 r600_store_config_reg_seq(cb, reg, 1); 581 r600_store_value(cb, value); 582} 583 584static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 585{ 586 r600_store_context_reg_seq(cb, reg, 1); 587 r600_store_value(cb, value); 588} 589 590static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 591{ 592 r600_store_ctl_const_seq(cb, reg, 1); 593 r600_store_value(cb, value); 594} 595 596static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 597{ 598 r600_store_loop_const_seq(cb, reg, 1); 599 r600_store_value(cb, value); 600} 601 602static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 603{ 604 eg_store_loop_const_seq(cb, reg, 1); 605 r600_store_value(cb, value); 606} 607 608void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 609void r600_release_command_buffer(struct r600_command_buffer *cb); 610 611/* 612 * Helpers for emitting state into a command stream directly. 613 */ 614 615static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 616{ 617 cs->buf[cs->cdw++] = value; 618} 619 620static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 621{ 622 assert(reg < R600_CONTEXT_REG_OFFSET); 623 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 624 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 625 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 626} 627 628static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 629{ 630 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 631 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 632 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 633 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 634} 635 636static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 637{ 638 assert(reg >= R600_CTL_CONST_OFFSET); 639 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 640 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 641 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 642} 643 644static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 645{ 646 r600_write_config_reg_seq(cs, reg, 1); 647 r600_write_value(cs, value); 648} 649 650static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 651{ 652 r600_write_context_reg_seq(cs, reg, 1); 653 r600_write_value(cs, value); 654} 655 656static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 657{ 658 r600_write_ctl_const_seq(cs, reg, 1); 659 r600_write_value(cs, value); 660} 661 662/* 663 * common helpers 664 */ 665static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 666{ 667 return value * (1 << frac_bits); 668} 669#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 670 671static inline unsigned r600_tex_aniso_filter(unsigned filter) 672{ 673 if (filter <= 1) return 0; 674 if (filter <= 2) return 1; 675 if (filter <= 4) return 2; 676 if (filter <= 8) return 3; 677 /* else */ return 4; 678} 679 680/* 12.4 fixed-point */ 681static INLINE unsigned r600_pack_float_12p4(float x) 682{ 683 return x <= 0 ? 0 : 684 x >= 4096 ? 0xffff : x * 16; 685} 686 687#endif 688