r600_pipe.h revision 0ea76916e63f8fc556f5e8f5a46c196d317cd5ad
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71 unsigned pkt_flags; 72}; 73 74struct r600_surface_sync_cmd { 75 struct r600_atom atom; 76 unsigned flush_flags; /* CP_COHER_CNTL */ 77}; 78 79struct r600_db_misc_state { 80 struct r600_atom atom; 81 bool occlusion_query_enabled; 82 bool flush_depthstencil_enabled; 83}; 84 85struct r600_cb_misc_state { 86 struct r600_atom atom; 87 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 88 unsigned nr_cbufs; 89}; 90 91enum r600_pipe_state_id { 92 R600_PIPE_STATE_BLEND = 0, 93 R600_PIPE_STATE_BLEND_COLOR, 94 R600_PIPE_STATE_CONFIG, 95 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 96 R600_PIPE_STATE_CLIP, 97 R600_PIPE_STATE_SCISSOR, 98 R600_PIPE_STATE_VIEWPORT, 99 R600_PIPE_STATE_RASTERIZER, 100 R600_PIPE_STATE_VGT, 101 R600_PIPE_STATE_FRAMEBUFFER, 102 R600_PIPE_STATE_DSA, 103 R600_PIPE_STATE_STENCIL_REF, 104 R600_PIPE_STATE_PS_SHADER, 105 R600_PIPE_STATE_VS_SHADER, 106 R600_PIPE_STATE_CONSTANT, 107 R600_PIPE_STATE_SAMPLER, 108 R600_PIPE_STATE_RESOURCE, 109 R600_PIPE_STATE_POLYGON_OFFSET, 110 R600_PIPE_STATE_FETCH_SHADER, 111 R600_PIPE_STATE_SPI, 112 R600_PIPE_NSTATES 113}; 114 115struct compute_memory_pool; 116void compute_memory_pool_delete(struct compute_memory_pool* pool); 117struct compute_memory_pool* compute_memory_pool_new( 118 struct r600_screen *rscreen); 119 120struct r600_pipe_fences { 121 struct r600_resource *bo; 122 unsigned *data; 123 unsigned next_index; 124 /* linked list of preallocated blocks */ 125 struct list_head blocks; 126 /* linked list of freed fences */ 127 struct list_head pool; 128 pipe_mutex mutex; 129}; 130 131struct r600_screen { 132 struct pipe_screen screen; 133 struct radeon_winsys *ws; 134 unsigned family; 135 enum chip_class chip_class; 136 struct radeon_info info; 137 bool has_streamout; 138 struct r600_tiling_info tiling_info; 139 struct r600_pipe_fences fences; 140 141 bool use_surface_alloc; 142 int glsl_feature_level; 143 144 /*for compute global memory binding, we allocate stuff here, instead of 145 * buffers. 146 * XXX: Not sure if this is the best place for global_pool. Also, 147 * it's not thread safe, so it won't work with multiple contexts. */ 148 struct compute_memory_pool *global_pool; 149}; 150 151struct r600_pipe_sampler_view { 152 struct pipe_sampler_view base; 153 struct r600_pipe_resource_state state; 154}; 155 156struct r600_pipe_rasterizer { 157 struct r600_pipe_state rstate; 158 boolean flatshade; 159 boolean two_side; 160 unsigned sprite_coord_enable; 161 unsigned clip_plane_enable; 162 unsigned pa_sc_line_stipple; 163 unsigned pa_cl_clip_cntl; 164 float offset_units; 165 float offset_scale; 166 bool scissor_enable; 167}; 168 169struct r600_pipe_blend { 170 struct r600_pipe_state rstate; 171 unsigned cb_target_mask; 172 unsigned cb_color_control; 173 bool dual_src_blend; 174}; 175 176struct r600_pipe_dsa { 177 struct r600_pipe_state rstate; 178 unsigned alpha_ref; 179 ubyte valuemask[2]; 180 ubyte writemask[2]; 181 bool is_flush; 182 unsigned sx_alpha_test_control; 183}; 184 185struct r600_vertex_element 186{ 187 unsigned count; 188 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 189 struct r600_resource *fetch_shader; 190 unsigned fs_size; 191 struct r600_pipe_state rstate; 192}; 193 194struct r600_pipe_shader; 195 196struct r600_pipe_shader_selector { 197 struct r600_pipe_shader *current; 198 199 struct tgsi_token *tokens; 200 struct pipe_stream_output_info so; 201 202 unsigned num_shaders; 203 204 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 205 unsigned type; 206 207 unsigned nr_ps_max_color_exports; 208}; 209 210struct r600_pipe_shader { 211 struct r600_pipe_shader_selector *selector; 212 struct r600_pipe_shader *next_variant; 213 struct r600_shader shader; 214 struct r600_pipe_state rstate; 215 struct r600_resource *bo; 216 struct r600_resource *bo_fetch; 217 struct r600_vertex_element vertex_elements; 218 unsigned sprite_coord_enable; 219 unsigned flatshade; 220 unsigned pa_cl_vs_out_cntl; 221 unsigned ps_cb_shader_mask; 222 unsigned key; 223 unsigned db_shader_control; 224 unsigned ps_depth_export; 225}; 226 227struct r600_pipe_sampler_state { 228 struct r600_pipe_state rstate; 229 boolean seamless_cube_map; 230}; 231 232/* needed for blitter save */ 233#define NUM_TEX_UNITS 16 234 235struct r600_textures_info { 236 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 237 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 238 unsigned n_views; 239 unsigned n_samplers; 240 bool samplers_dirty; 241 bool is_array_sampler[NUM_TEX_UNITS]; 242}; 243 244struct r600_fence { 245 struct pipe_reference reference; 246 unsigned index; /* in the shared bo */ 247 struct r600_resource *sleep_bo; 248 struct list_head head; 249}; 250 251#define FENCE_BLOCK_SIZE 16 252 253struct r600_fence_block { 254 struct r600_fence fences[FENCE_BLOCK_SIZE]; 255 struct list_head head; 256}; 257 258#define R600_CONSTANT_ARRAY_SIZE 256 259#define R600_RESOURCE_ARRAY_SIZE 160 260 261struct r600_stencil_ref 262{ 263 ubyte ref_value[2]; 264 ubyte valuemask[2]; 265 ubyte writemask[2]; 266}; 267 268struct r600_constbuf_state 269{ 270 struct r600_atom atom; 271 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 272 uint32_t enabled_mask; 273 uint32_t dirty_mask; 274}; 275 276struct r600_context { 277 struct pipe_context context; 278 struct blitter_context *blitter; 279 enum radeon_family family; 280 enum chip_class chip_class; 281 boolean has_vertex_cache; 282 unsigned r6xx_num_clause_temp_gprs; 283 void *custom_dsa_flush; 284 struct r600_screen *screen; 285 struct radeon_winsys *ws; 286 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 287 struct r600_vertex_element *vertex_elements; 288 struct pipe_framebuffer_state framebuffer; 289 unsigned fb_cb_shader_mask; 290 unsigned compute_cb_target_mask; 291 unsigned sx_alpha_test_control; 292 unsigned cb_shader_mask; 293 unsigned db_shader_control; 294 unsigned cb_color_control; 295 unsigned pa_sc_line_stipple; 296 unsigned pa_cl_clip_cntl; 297 /* for saving when using blitter */ 298 struct pipe_stencil_ref stencil_ref; 299 struct pipe_viewport_state viewport; 300 struct pipe_clip_state clip; 301 struct r600_pipe_shader_selector *ps_shader; 302 struct r600_pipe_shader_selector *vs_shader; 303 struct r600_pipe_compute *cs_shader; 304 struct r600_pipe_rasterizer *rasterizer; 305 struct r600_pipe_state vgt; 306 struct r600_pipe_state spi; 307 struct pipe_query *current_render_cond; 308 unsigned current_render_cond_mode; 309 struct pipe_query *saved_render_cond; 310 unsigned saved_render_cond_mode; 311 /* shader information */ 312 boolean two_side; 313 boolean spi_dirty; 314 unsigned sprite_coord_enable; 315 boolean flatshade; 316 boolean export_16bpc; 317 unsigned alpha_ref; 318 boolean alpha_ref_dirty; 319 unsigned nr_cbufs; 320 struct r600_textures_info vs_samplers; 321 struct r600_textures_info ps_samplers; 322 323 struct u_upload_mgr *uploader; 324 struct util_slab_mempool pool_transfers; 325 boolean have_depth_texture, have_depth_fb; 326 327 unsigned default_ps_gprs, default_vs_gprs; 328 329 /* States based on r600_atom. */ 330 struct list_head dirty_states; 331 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 332 /** Compute specific registers initializations. The start_cs_cmd atom 333 * must be emitted before start_compute_cs_cmd. */ 334 struct r600_command_buffer start_compute_cs_cmd; 335 struct r600_surface_sync_cmd surface_sync_cmd; 336 struct r600_atom r6xx_flush_and_inv_cmd; 337 struct r600_cb_misc_state cb_misc_state; 338 struct r600_db_misc_state db_misc_state; 339 struct r600_atom vertex_buffer_state; 340 struct r600_constbuf_state vs_constbuf_state; 341 struct r600_constbuf_state ps_constbuf_state; 342 343 struct radeon_winsys_cs *cs; 344 345 struct r600_range *range; 346 unsigned nblocks; 347 struct r600_block **blocks; 348 struct list_head dirty; 349 struct list_head resource_dirty; 350 struct list_head enable_list; 351 unsigned pm4_dirty_cdwords; 352 unsigned ctx_pm4_ndwords; 353 354 /* The list of active queries. Only one query of each type can be active. */ 355 int num_occlusion_queries; 356 357 /* Manage queries in two separate groups: 358 * The timer ones and the others (streamout, occlusion). 359 * 360 * We do this because we should only suspend non-timer queries for u_blitter, 361 * and later if the non-timer queries are suspended, the context flush should 362 * only suspend and resume the timer queries. */ 363 struct list_head active_timer_queries; 364 unsigned num_cs_dw_timer_queries_suspend; 365 struct list_head active_nontimer_queries; 366 unsigned num_cs_dw_nontimer_queries_suspend; 367 368 unsigned num_cs_dw_streamout_end; 369 370 unsigned backend_mask; 371 unsigned max_db; /* for OQ */ 372 unsigned flags; 373 boolean predicate_drawing; 374 struct r600_range ps_resources; 375 struct r600_range vs_resources; 376 int num_ps_resources, num_vs_resources; 377 378 unsigned num_so_targets; 379 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 380 boolean streamout_start; 381 unsigned streamout_append_bitmask; 382 383 /* There is no scissor enable bit on r6xx, so we must use a workaround. 384 * These track the current scissor state. */ 385 bool scissor_enable; 386 struct pipe_scissor_state scissor_state; 387 388 /* With rasterizer discard, there doesn't have to be a pixel shader. 389 * In that case, we bind this one: */ 390 void *dummy_pixel_shader; 391 392 boolean dual_src_blend; 393 394 /* Vertex and index buffers. */ 395 bool vertex_buffers_dirty; 396 struct pipe_index_buffer index_buffer; 397 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; 398 unsigned nr_vertex_buffers; 399}; 400 401static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 402{ 403 atom->emit(rctx, atom); 404 atom->dirty = false; 405 if (atom->head.next && atom->head.prev) 406 LIST_DELINIT(&atom->head); 407} 408 409static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 410{ 411 if (!state->dirty) { 412 if (state->flags & EMIT_EARLY) { 413 LIST_ADD(&state->head, &rctx->dirty_states); 414 } else { 415 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 416 } 417 state->dirty = true; 418 } 419} 420 421/* evergreen_state.c */ 422void evergreen_init_state_functions(struct r600_context *rctx); 423void evergreen_init_atom_start_cs(struct r600_context *rctx); 424void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 425void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 426void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 427void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 428void evergreen_polygon_offset_update(struct r600_context *rctx); 429boolean evergreen_is_format_supported(struct pipe_screen *screen, 430 enum pipe_format format, 431 enum pipe_texture_target target, 432 unsigned sample_count, 433 unsigned usage); 434void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, 435 const struct pipe_framebuffer_state *state, int cb); 436 437 438void evergreen_update_dual_export_state(struct r600_context * rctx); 439 440/* r600_blit.c */ 441void r600_init_blit_functions(struct r600_context *rctx); 442void r600_blit_uncompress_depth(struct pipe_context *ctx, 443 struct r600_resource_texture *texture, 444 struct r600_resource_texture *staging); 445void r600_flush_depth_textures(struct r600_context *rctx); 446 447/* r600_buffer.c */ 448bool r600_init_resource(struct r600_screen *rscreen, 449 struct r600_resource *res, 450 unsigned size, unsigned alignment, 451 unsigned bind, unsigned usage); 452struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 453 const struct pipe_resource *templ); 454 455/* r600_pipe.c */ 456void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 457 unsigned flags); 458 459/* r600_query.c */ 460void r600_init_query_functions(struct r600_context *rctx); 461void r600_suspend_nontimer_queries(struct r600_context *ctx); 462void r600_resume_nontimer_queries(struct r600_context *ctx); 463void r600_suspend_timer_queries(struct r600_context *ctx); 464void r600_resume_timer_queries(struct r600_context *ctx); 465 466/* r600_resource.c */ 467void r600_init_context_resource_functions(struct r600_context *r600); 468 469/* r600_shader.c */ 470int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 471#ifdef HAVE_OPENCL 472int r600_compute_shader_create(struct pipe_context * ctx, 473 LLVMModuleRef mod, struct r600_bytecode * bytecode); 474#endif 475void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 476 477/* r600_state.c */ 478void r600_set_scissor_state(struct r600_context *rctx, 479 const struct pipe_scissor_state *state); 480void r600_update_sampler_states(struct r600_context *rctx); 481void r600_init_state_functions(struct r600_context *rctx); 482void r600_init_atom_start_cs(struct r600_context *rctx); 483void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 484void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 485void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 486void *r600_create_db_flush_dsa(struct r600_context *rctx); 487void r600_polygon_offset_update(struct r600_context *rctx); 488void r600_adjust_gprs(struct r600_context *rctx); 489boolean r600_is_format_supported(struct pipe_screen *screen, 490 enum pipe_format format, 491 enum pipe_texture_target target, 492 unsigned sample_count, 493 unsigned usage); 494void r600_update_dual_export_state(struct r600_context * rctx); 495 496/* r600_texture.c */ 497void r600_init_screen_texture_functions(struct pipe_screen *screen); 498void r600_init_surface_functions(struct r600_context *r600); 499uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 500 const unsigned char *swizzle_view, 501 uint32_t *word4_p, uint32_t *yuv_format_p); 502unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 503 unsigned level, unsigned layer); 504 505/* r600_translate.c */ 506void r600_translate_index_buffer(struct r600_context *r600, 507 struct pipe_index_buffer *ib, 508 unsigned count); 509 510/* r600_state_common.c */ 511void r600_init_atom(struct r600_atom *atom, 512 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 513 unsigned num_dw, enum r600_atom_flags flags); 514void r600_init_common_atoms(struct r600_context *rctx); 515unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 516void r600_texture_barrier(struct pipe_context *ctx); 517void r600_set_index_buffer(struct pipe_context *ctx, 518 const struct pipe_index_buffer *ib); 519void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 520 const struct pipe_vertex_buffer *buffers); 521void *r600_create_vertex_elements(struct pipe_context *ctx, 522 unsigned count, 523 const struct pipe_vertex_element *elements); 524void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 525void r600_bind_blend_state(struct pipe_context *ctx, void *state); 526void r600_set_blend_color(struct pipe_context *ctx, 527 const struct pipe_blend_color *state); 528void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 529void r600_set_max_scissor(struct r600_context *rctx); 530void r600_bind_rs_state(struct pipe_context *ctx, void *state); 531void r600_delete_rs_state(struct pipe_context *ctx, void *state); 532void r600_sampler_view_destroy(struct pipe_context *ctx, 533 struct pipe_sampler_view *state); 534void r600_delete_state(struct pipe_context *ctx, void *state); 535void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 536void *r600_create_shader_state_ps(struct pipe_context *ctx, 537 const struct pipe_shader_state *state); 538void *r600_create_shader_state_vs(struct pipe_context *ctx, 539 const struct pipe_shader_state *state); 540void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 541void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 542void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 543void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 544void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 545void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 546 struct pipe_constant_buffer *cb); 547struct pipe_stream_output_target * 548r600_create_so_target(struct pipe_context *ctx, 549 struct pipe_resource *buffer, 550 unsigned buffer_offset, 551 unsigned buffer_size); 552void r600_so_target_destroy(struct pipe_context *ctx, 553 struct pipe_stream_output_target *target); 554void r600_set_so_targets(struct pipe_context *ctx, 555 unsigned num_targets, 556 struct pipe_stream_output_target **targets, 557 unsigned append_bitmask); 558void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 559 const struct pipe_stencil_ref *state); 560void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 561uint32_t r600_translate_stencil_op(int s_op); 562uint32_t r600_translate_fill(uint32_t func); 563unsigned r600_tex_wrap(unsigned wrap); 564unsigned r600_tex_filter(unsigned filter); 565unsigned r600_tex_mipfilter(unsigned filter); 566unsigned r600_tex_compare(unsigned compare); 567 568/* 569 * Helpers for building command buffers 570 */ 571 572#define PKT3_SET_CONFIG_REG 0x68 573#define PKT3_SET_CONTEXT_REG 0x69 574#define PKT3_SET_CTL_CONST 0x6F 575#define PKT3_SET_LOOP_CONST 0x6C 576 577#define R600_CONFIG_REG_OFFSET 0x08000 578#define R600_CONTEXT_REG_OFFSET 0x28000 579#define R600_CTL_CONST_OFFSET 0x3CFF0 580#define R600_LOOP_CONST_OFFSET 0X0003E200 581#define EG_LOOP_CONST_OFFSET 0x0003A200 582 583#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 584#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 585#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 586#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 587#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 588 589static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 590{ 591 cb->buf[cb->atom.num_dw++] = value; 592} 593 594static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 595{ 596 assert(reg < R600_CONTEXT_REG_OFFSET); 597 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 598 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 599 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 600} 601 602/** 603 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 604 * shaders. 605 */ 606static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 607{ 608 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 609 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 610 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 611 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 612} 613 614/** 615 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 616 * shaders. 617 */ 618static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 619{ 620 assert(reg >= R600_CTL_CONST_OFFSET); 621 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 622 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 623 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 624} 625 626static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 627{ 628 assert(reg >= R600_LOOP_CONST_OFFSET); 629 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 630 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 631 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 632} 633 634/** 635 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 636 * shaders. 637 */ 638static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 639{ 640 assert(reg >= EG_LOOP_CONST_OFFSET); 641 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 642 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 643 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 644} 645 646static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 647{ 648 r600_store_config_reg_seq(cb, reg, 1); 649 r600_store_value(cb, value); 650} 651 652static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 653{ 654 r600_store_context_reg_seq(cb, reg, 1); 655 r600_store_value(cb, value); 656} 657 658static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 659{ 660 r600_store_ctl_const_seq(cb, reg, 1); 661 r600_store_value(cb, value); 662} 663 664static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 665{ 666 r600_store_loop_const_seq(cb, reg, 1); 667 r600_store_value(cb, value); 668} 669 670static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 671{ 672 eg_store_loop_const_seq(cb, reg, 1); 673 r600_store_value(cb, value); 674} 675 676void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 677void r600_release_command_buffer(struct r600_command_buffer *cb); 678 679/* 680 * Helpers for emitting state into a command stream directly. 681 */ 682 683static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 684 enum radeon_bo_usage usage) 685{ 686 assert(usage); 687 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 688} 689 690static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 691{ 692 cs->buf[cs->cdw++] = value; 693} 694 695static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 696{ 697 assert(reg < R600_CONTEXT_REG_OFFSET); 698 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 699 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 700 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 701} 702 703static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 704{ 705 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 706 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 707 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 708 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 709} 710 711static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 712{ 713 assert(reg >= R600_CTL_CONST_OFFSET); 714 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 715 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 716 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 717} 718 719static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 720{ 721 r600_write_config_reg_seq(cs, reg, 1); 722 r600_write_value(cs, value); 723} 724 725static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 726{ 727 r600_write_context_reg_seq(cs, reg, 1); 728 r600_write_value(cs, value); 729} 730 731static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 732{ 733 r600_write_ctl_const_seq(cs, reg, 1); 734 r600_write_value(cs, value); 735} 736 737/* 738 * common helpers 739 */ 740static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 741{ 742 return value * (1 << frac_bits); 743} 744#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 745 746static inline unsigned r600_tex_aniso_filter(unsigned filter) 747{ 748 if (filter <= 1) return 0; 749 if (filter <= 2) return 1; 750 if (filter <= 4) return 2; 751 if (filter <= 8) return 3; 752 /* else */ return 4; 753} 754 755/* 12.4 fixed-point */ 756static INLINE unsigned r600_pack_float_12p4(float x) 757{ 758 return x <= 0 ? 0 : 759 x >= 4096 ? 0xffff : x * 16; 760} 761 762static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 763{ 764 struct r600_screen *rscreen = (struct r600_screen*)screen; 765 struct r600_resource *rresource = (struct r600_resource*)resource; 766 767 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 768} 769 770#endif 771