r600_pipe.h revision 15ca9d159e50815b0bfe60df8873f48c32a59ca5
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71 unsigned pkt_flags; 72}; 73 74struct r600_surface_sync_cmd { 75 struct r600_atom atom; 76 unsigned flush_flags; /* CP_COHER_CNTL */ 77}; 78 79struct r600_db_misc_state { 80 struct r600_atom atom; 81 bool occlusion_query_enabled; 82 bool flush_depthstencil_through_cb; 83}; 84 85struct r600_cb_misc_state { 86 struct r600_atom atom; 87 unsigned cb_color_control; /* this comes from blend state */ 88 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 89 unsigned nr_cbufs; 90 unsigned nr_ps_color_outputs; 91 bool multiwrite; 92 bool dual_src_blend; 93}; 94 95enum r600_pipe_state_id { 96 R600_PIPE_STATE_BLEND = 0, 97 R600_PIPE_STATE_BLEND_COLOR, 98 R600_PIPE_STATE_CONFIG, 99 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 100 R600_PIPE_STATE_CLIP, 101 R600_PIPE_STATE_SCISSOR, 102 R600_PIPE_STATE_VIEWPORT, 103 R600_PIPE_STATE_RASTERIZER, 104 R600_PIPE_STATE_VGT, 105 R600_PIPE_STATE_FRAMEBUFFER, 106 R600_PIPE_STATE_DSA, 107 R600_PIPE_STATE_STENCIL_REF, 108 R600_PIPE_STATE_PS_SHADER, 109 R600_PIPE_STATE_VS_SHADER, 110 R600_PIPE_STATE_CONSTANT, 111 R600_PIPE_STATE_SAMPLER, 112 R600_PIPE_STATE_RESOURCE, 113 R600_PIPE_STATE_POLYGON_OFFSET, 114 R600_PIPE_STATE_FETCH_SHADER, 115 R600_PIPE_STATE_SPI, 116 R600_PIPE_NSTATES 117}; 118 119struct compute_memory_pool; 120void compute_memory_pool_delete(struct compute_memory_pool* pool); 121struct compute_memory_pool* compute_memory_pool_new( 122 struct r600_screen *rscreen); 123 124struct r600_pipe_fences { 125 struct r600_resource *bo; 126 unsigned *data; 127 unsigned next_index; 128 /* linked list of preallocated blocks */ 129 struct list_head blocks; 130 /* linked list of freed fences */ 131 struct list_head pool; 132 pipe_mutex mutex; 133}; 134 135struct r600_screen { 136 struct pipe_screen screen; 137 struct radeon_winsys *ws; 138 unsigned family; 139 enum chip_class chip_class; 140 struct radeon_info info; 141 bool has_streamout; 142 struct r600_tiling_info tiling_info; 143 struct r600_pipe_fences fences; 144 145 bool use_surface_alloc; 146 147 /*for compute global memory binding, we allocate stuff here, instead of 148 * buffers. 149 * XXX: Not sure if this is the best place for global_pool. Also, 150 * it's not thread safe, so it won't work with multiple contexts. */ 151 struct compute_memory_pool *global_pool; 152}; 153 154struct r600_pipe_sampler_view { 155 struct pipe_sampler_view base; 156 struct r600_pipe_resource_state state; 157}; 158 159struct r600_pipe_rasterizer { 160 struct r600_pipe_state rstate; 161 boolean flatshade; 162 boolean two_side; 163 unsigned sprite_coord_enable; 164 unsigned clip_plane_enable; 165 unsigned pa_sc_line_stipple; 166 unsigned pa_cl_clip_cntl; 167 float offset_units; 168 float offset_scale; 169 bool scissor_enable; 170}; 171 172struct r600_pipe_blend { 173 struct r600_pipe_state rstate; 174 unsigned cb_target_mask; 175 unsigned cb_color_control; 176 bool dual_src_blend; 177}; 178 179struct r600_pipe_dsa { 180 struct r600_pipe_state rstate; 181 unsigned alpha_ref; 182 ubyte valuemask[2]; 183 ubyte writemask[2]; 184 unsigned sx_alpha_test_control; 185}; 186 187struct r600_vertex_element 188{ 189 unsigned count; 190 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 191 struct r600_resource *fetch_shader; 192 unsigned fs_size; 193 struct r600_pipe_state rstate; 194}; 195 196struct r600_pipe_shader; 197 198struct r600_pipe_shader_selector { 199 struct r600_pipe_shader *current; 200 201 struct tgsi_token *tokens; 202 struct pipe_stream_output_info so; 203 204 unsigned num_shaders; 205 206 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 207 unsigned type; 208 209 unsigned nr_ps_max_color_exports; 210}; 211 212struct r600_pipe_shader { 213 struct r600_pipe_shader_selector *selector; 214 struct r600_pipe_shader *next_variant; 215 struct r600_shader shader; 216 struct r600_pipe_state rstate; 217 struct r600_resource *bo; 218 struct r600_resource *bo_fetch; 219 struct r600_vertex_element vertex_elements; 220 unsigned sprite_coord_enable; 221 unsigned flatshade; 222 unsigned pa_cl_vs_out_cntl; 223 unsigned nr_ps_color_outputs; 224 unsigned key; 225 unsigned db_shader_control; 226 unsigned ps_depth_export; 227}; 228 229struct r600_pipe_sampler_state { 230 struct r600_pipe_state rstate; 231 boolean seamless_cube_map; 232}; 233 234/* needed for blitter save */ 235#define NUM_TEX_UNITS 16 236 237struct r600_textures_info { 238 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 239 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 240 unsigned n_views; 241 unsigned n_samplers; 242 bool samplers_dirty; 243 bool is_array_sampler[NUM_TEX_UNITS]; 244}; 245 246struct r600_fence { 247 struct pipe_reference reference; 248 unsigned index; /* in the shared bo */ 249 struct r600_resource *sleep_bo; 250 struct list_head head; 251}; 252 253#define FENCE_BLOCK_SIZE 16 254 255struct r600_fence_block { 256 struct r600_fence fences[FENCE_BLOCK_SIZE]; 257 struct list_head head; 258}; 259 260#define R600_CONSTANT_ARRAY_SIZE 256 261#define R600_RESOURCE_ARRAY_SIZE 160 262 263struct r600_stencil_ref 264{ 265 ubyte ref_value[2]; 266 ubyte valuemask[2]; 267 ubyte writemask[2]; 268}; 269 270struct r600_constbuf_state 271{ 272 struct r600_atom atom; 273 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 274 uint32_t enabled_mask; 275 uint32_t dirty_mask; 276}; 277 278struct r600_vertexbuf_state 279{ 280 struct r600_atom atom; 281 uint32_t dirty_mask; 282}; 283 284struct r600_context { 285 struct pipe_context context; 286 struct blitter_context *blitter; 287 enum radeon_family family; 288 enum chip_class chip_class; 289 boolean has_vertex_cache; 290 unsigned r6xx_num_clause_temp_gprs; 291 void *custom_dsa_flush; 292 struct r600_screen *screen; 293 struct radeon_winsys *ws; 294 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 295 struct r600_vertex_element *vertex_elements; 296 struct pipe_framebuffer_state framebuffer; 297 unsigned compute_cb_target_mask; 298 unsigned sx_alpha_test_control; 299 unsigned db_shader_control; 300 unsigned pa_sc_line_stipple; 301 unsigned pa_cl_clip_cntl; 302 /* for saving when using blitter */ 303 struct pipe_stencil_ref stencil_ref; 304 struct pipe_viewport_state viewport; 305 struct pipe_clip_state clip; 306 struct r600_pipe_shader_selector *ps_shader; 307 struct r600_pipe_shader_selector *vs_shader; 308 struct r600_pipe_compute *cs_shader; 309 struct r600_pipe_rasterizer *rasterizer; 310 struct r600_pipe_state vgt; 311 struct r600_pipe_state spi; 312 struct pipe_query *current_render_cond; 313 unsigned current_render_cond_mode; 314 struct pipe_query *saved_render_cond; 315 unsigned saved_render_cond_mode; 316 /* shader information */ 317 boolean two_side; 318 boolean spi_dirty; 319 unsigned sprite_coord_enable; 320 boolean flatshade; 321 boolean export_16bpc; 322 unsigned alpha_ref; 323 boolean alpha_ref_dirty; 324 unsigned nr_cbufs; 325 struct r600_textures_info vs_samplers; 326 struct r600_textures_info ps_samplers; 327 328 struct u_upload_mgr *uploader; 329 struct util_slab_mempool pool_transfers; 330 boolean have_depth_texture, have_depth_fb; 331 332 unsigned default_ps_gprs, default_vs_gprs; 333 334 /* States based on r600_atom. */ 335 struct list_head dirty_states; 336 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 337 /** Compute specific registers initializations. The start_cs_cmd atom 338 * must be emitted before start_compute_cs_cmd. */ 339 struct r600_command_buffer start_compute_cs_cmd; 340 struct r600_surface_sync_cmd surface_sync_cmd; 341 struct r600_atom r6xx_flush_and_inv_cmd; 342 struct r600_cb_misc_state cb_misc_state; 343 struct r600_db_misc_state db_misc_state; 344 /** Vertex buffers for fetch shaders */ 345 struct r600_vertexbuf_state vertex_buffer_state; 346 /** Vertex buffers for compute shaders */ 347 struct r600_vertexbuf_state cs_vertex_buffer_state; 348 struct r600_constbuf_state vs_constbuf_state; 349 struct r600_constbuf_state ps_constbuf_state; 350 351 struct radeon_winsys_cs *cs; 352 353 struct r600_range *range; 354 unsigned nblocks; 355 struct r600_block **blocks; 356 struct list_head dirty; 357 struct list_head resource_dirty; 358 struct list_head enable_list; 359 unsigned pm4_dirty_cdwords; 360 unsigned ctx_pm4_ndwords; 361 362 /* The list of active queries. Only one query of each type can be active. */ 363 int num_occlusion_queries; 364 365 /* Manage queries in two separate groups: 366 * The timer ones and the others (streamout, occlusion). 367 * 368 * We do this because we should only suspend non-timer queries for u_blitter, 369 * and later if the non-timer queries are suspended, the context flush should 370 * only suspend and resume the timer queries. */ 371 struct list_head active_timer_queries; 372 unsigned num_cs_dw_timer_queries_suspend; 373 struct list_head active_nontimer_queries; 374 unsigned num_cs_dw_nontimer_queries_suspend; 375 376 unsigned num_cs_dw_streamout_end; 377 378 unsigned backend_mask; 379 unsigned max_db; /* for OQ */ 380 unsigned flags; 381 boolean predicate_drawing; 382 struct r600_range ps_resources; 383 struct r600_range vs_resources; 384 int num_ps_resources, num_vs_resources; 385 386 unsigned num_so_targets; 387 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 388 boolean streamout_start; 389 unsigned streamout_append_bitmask; 390 391 /* There is no scissor enable bit on r6xx, so we must use a workaround. 392 * These track the current scissor state. */ 393 bool scissor_enable; 394 struct pipe_scissor_state scissor_state; 395 396 /* With rasterizer discard, there doesn't have to be a pixel shader. 397 * In that case, we bind this one: */ 398 void *dummy_pixel_shader; 399 400 boolean dual_src_blend; 401 402 /* Vertex and index buffers. */ 403 bool vertex_buffers_dirty; 404 struct pipe_index_buffer index_buffer; 405 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; 406 unsigned nr_vertex_buffers; 407 struct pipe_vertex_buffer cs_vertex_buffer[PIPE_MAX_ATTRIBS]; 408 unsigned nr_cs_vertex_buffers; 409}; 410 411static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 412{ 413 atom->emit(rctx, atom); 414 atom->dirty = false; 415 if (atom->head.next && atom->head.prev) 416 LIST_DELINIT(&atom->head); 417} 418 419static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 420{ 421 if (!state->dirty) { 422 if (state->flags & EMIT_EARLY) { 423 LIST_ADD(&state->head, &rctx->dirty_states); 424 } else { 425 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 426 } 427 state->dirty = true; 428 } 429} 430 431/* evergreen_state.c */ 432void evergreen_init_state_functions(struct r600_context *rctx); 433void evergreen_init_atom_start_cs(struct r600_context *rctx); 434void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 435void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 436void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 437void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 438void evergreen_polygon_offset_update(struct r600_context *rctx); 439boolean evergreen_is_format_supported(struct pipe_screen *screen, 440 enum pipe_format format, 441 enum pipe_texture_target target, 442 unsigned sample_count, 443 unsigned usage); 444void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, 445 const struct pipe_framebuffer_state *state, int cb); 446 447 448void evergreen_update_dual_export_state(struct r600_context * rctx); 449 450/* r600_blit.c */ 451void r600_init_blit_functions(struct r600_context *rctx); 452void r600_blit_uncompress_depth(struct pipe_context *ctx, 453 struct r600_resource_texture *texture, 454 struct r600_resource_texture *staging, 455 unsigned first_level, unsigned last_level, 456 unsigned first_layer, unsigned last_layer); 457void r600_flush_all_depth_textures(struct r600_context *rctx); 458 459/* r600_buffer.c */ 460bool r600_init_resource(struct r600_screen *rscreen, 461 struct r600_resource *res, 462 unsigned size, unsigned alignment, 463 unsigned bind, unsigned usage); 464struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 465 const struct pipe_resource *templ); 466 467/* r600_pipe.c */ 468void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 469 unsigned flags); 470 471/* r600_query.c */ 472void r600_init_query_functions(struct r600_context *rctx); 473void r600_suspend_nontimer_queries(struct r600_context *ctx); 474void r600_resume_nontimer_queries(struct r600_context *ctx); 475void r600_suspend_timer_queries(struct r600_context *ctx); 476void r600_resume_timer_queries(struct r600_context *ctx); 477 478/* r600_resource.c */ 479void r600_init_context_resource_functions(struct r600_context *r600); 480 481/* r600_shader.c */ 482int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 483#ifdef HAVE_OPENCL 484int r600_compute_shader_create(struct pipe_context * ctx, 485 LLVMModuleRef mod, struct r600_bytecode * bytecode); 486#endif 487void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 488 489/* r600_state.c */ 490void r600_set_scissor_state(struct r600_context *rctx, 491 const struct pipe_scissor_state *state); 492void r600_update_sampler_states(struct r600_context *rctx); 493void r600_init_state_functions(struct r600_context *rctx); 494void r600_init_atom_start_cs(struct r600_context *rctx); 495void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 496void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 497void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 498void *r600_create_db_flush_dsa(struct r600_context *rctx); 499void r600_polygon_offset_update(struct r600_context *rctx); 500void r600_adjust_gprs(struct r600_context *rctx); 501boolean r600_is_format_supported(struct pipe_screen *screen, 502 enum pipe_format format, 503 enum pipe_texture_target target, 504 unsigned sample_count, 505 unsigned usage); 506void r600_update_dual_export_state(struct r600_context * rctx); 507 508/* r600_texture.c */ 509void r600_init_screen_texture_functions(struct pipe_screen *screen); 510void r600_init_surface_functions(struct r600_context *r600); 511uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 512 const unsigned char *swizzle_view, 513 uint32_t *word4_p, uint32_t *yuv_format_p); 514unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 515 unsigned level, unsigned layer); 516 517/* r600_translate.c */ 518void r600_translate_index_buffer(struct r600_context *r600, 519 struct pipe_index_buffer *ib, 520 unsigned count); 521 522/* r600_state_common.c */ 523void r600_init_atom(struct r600_atom *atom, 524 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 525 unsigned num_dw, enum r600_atom_flags flags); 526void r600_init_common_atoms(struct r600_context *rctx); 527unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 528void r600_texture_barrier(struct pipe_context *ctx); 529void r600_set_index_buffer(struct pipe_context *ctx, 530 const struct pipe_index_buffer *ib); 531void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 532 const struct pipe_vertex_buffer *buffers); 533void *r600_create_vertex_elements(struct pipe_context *ctx, 534 unsigned count, 535 const struct pipe_vertex_element *elements); 536void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 537void r600_bind_blend_state(struct pipe_context *ctx, void *state); 538void r600_set_blend_color(struct pipe_context *ctx, 539 const struct pipe_blend_color *state); 540void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 541void r600_set_max_scissor(struct r600_context *rctx); 542void r600_bind_rs_state(struct pipe_context *ctx, void *state); 543void r600_delete_rs_state(struct pipe_context *ctx, void *state); 544void r600_sampler_view_destroy(struct pipe_context *ctx, 545 struct pipe_sampler_view *state); 546void r600_delete_state(struct pipe_context *ctx, void *state); 547void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 548void *r600_create_shader_state_ps(struct pipe_context *ctx, 549 const struct pipe_shader_state *state); 550void *r600_create_shader_state_vs(struct pipe_context *ctx, 551 const struct pipe_shader_state *state); 552void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 553void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 554void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 555void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 556void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 557void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 558 struct pipe_constant_buffer *cb); 559struct pipe_stream_output_target * 560r600_create_so_target(struct pipe_context *ctx, 561 struct pipe_resource *buffer, 562 unsigned buffer_offset, 563 unsigned buffer_size); 564void r600_so_target_destroy(struct pipe_context *ctx, 565 struct pipe_stream_output_target *target); 566void r600_set_so_targets(struct pipe_context *ctx, 567 unsigned num_targets, 568 struct pipe_stream_output_target **targets, 569 unsigned append_bitmask); 570void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 571 const struct pipe_stencil_ref *state); 572void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 573uint32_t r600_translate_stencil_op(int s_op); 574uint32_t r600_translate_fill(uint32_t func); 575unsigned r600_tex_wrap(unsigned wrap); 576unsigned r600_tex_filter(unsigned filter); 577unsigned r600_tex_mipfilter(unsigned filter); 578unsigned r600_tex_compare(unsigned compare); 579 580/* 581 * Helpers for building command buffers 582 */ 583 584#define PKT3_SET_CONFIG_REG 0x68 585#define PKT3_SET_CONTEXT_REG 0x69 586#define PKT3_SET_CTL_CONST 0x6F 587#define PKT3_SET_LOOP_CONST 0x6C 588 589#define R600_CONFIG_REG_OFFSET 0x08000 590#define R600_CONTEXT_REG_OFFSET 0x28000 591#define R600_CTL_CONST_OFFSET 0x3CFF0 592#define R600_LOOP_CONST_OFFSET 0X0003E200 593#define EG_LOOP_CONST_OFFSET 0x0003A200 594 595#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 596#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 597#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 598#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 599#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 600 601static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 602{ 603 cb->buf[cb->atom.num_dw++] = value; 604} 605 606static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 607{ 608 assert(reg < R600_CONTEXT_REG_OFFSET); 609 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 610 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 611 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 612} 613 614/** 615 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 616 * shaders. 617 */ 618static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 619{ 620 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 621 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 622 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 623 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 624} 625 626/** 627 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 628 * shaders. 629 */ 630static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 631{ 632 assert(reg >= R600_CTL_CONST_OFFSET); 633 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 634 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 635 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 636} 637 638static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 639{ 640 assert(reg >= R600_LOOP_CONST_OFFSET); 641 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 642 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 643 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 644} 645 646/** 647 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 648 * shaders. 649 */ 650static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 651{ 652 assert(reg >= EG_LOOP_CONST_OFFSET); 653 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 654 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 655 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 656} 657 658static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 659{ 660 r600_store_config_reg_seq(cb, reg, 1); 661 r600_store_value(cb, value); 662} 663 664static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 665{ 666 r600_store_context_reg_seq(cb, reg, 1); 667 r600_store_value(cb, value); 668} 669 670static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 671{ 672 r600_store_ctl_const_seq(cb, reg, 1); 673 r600_store_value(cb, value); 674} 675 676static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 677{ 678 r600_store_loop_const_seq(cb, reg, 1); 679 r600_store_value(cb, value); 680} 681 682static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 683{ 684 eg_store_loop_const_seq(cb, reg, 1); 685 r600_store_value(cb, value); 686} 687 688void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 689void r600_release_command_buffer(struct r600_command_buffer *cb); 690 691/* 692 * Helpers for emitting state into a command stream directly. 693 */ 694 695static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 696 enum radeon_bo_usage usage) 697{ 698 assert(usage); 699 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 700} 701 702static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 703{ 704 cs->buf[cs->cdw++] = value; 705} 706 707static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 708{ 709 assert(reg < R600_CONTEXT_REG_OFFSET); 710 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 711 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 712 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 713} 714 715static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 716{ 717 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 718 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 719 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 720 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 721} 722 723static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 724{ 725 assert(reg >= R600_CTL_CONST_OFFSET); 726 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 727 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 728 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 729} 730 731static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 732{ 733 r600_write_config_reg_seq(cs, reg, 1); 734 r600_write_value(cs, value); 735} 736 737static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 738{ 739 r600_write_context_reg_seq(cs, reg, 1); 740 r600_write_value(cs, value); 741} 742 743static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 744{ 745 r600_write_ctl_const_seq(cs, reg, 1); 746 r600_write_value(cs, value); 747} 748 749/* 750 * common helpers 751 */ 752static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 753{ 754 return value * (1 << frac_bits); 755} 756#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 757 758static inline unsigned r600_tex_aniso_filter(unsigned filter) 759{ 760 if (filter <= 1) return 0; 761 if (filter <= 2) return 1; 762 if (filter <= 4) return 2; 763 if (filter <= 8) return 3; 764 /* else */ return 4; 765} 766 767/* 12.4 fixed-point */ 768static INLINE unsigned r600_pack_float_12p4(float x) 769{ 770 return x <= 0 ? 0 : 771 x >= 4096 ? 0xffff : x * 16; 772} 773 774static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 775{ 776 struct r600_screen *rscreen = (struct r600_screen*)screen; 777 struct r600_resource *rresource = (struct r600_resource*)resource; 778 779 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 780} 781 782#endif 783