r600_pipe.h revision 26cb887ea213be2445e0fd64364d9264ed4fbfd2
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71 unsigned pkt_flags; 72}; 73 74struct r600_surface_sync_cmd { 75 struct r600_atom atom; 76 unsigned flush_flags; /* CP_COHER_CNTL */ 77}; 78 79struct r600_db_misc_state { 80 struct r600_atom atom; 81 bool occlusion_query_enabled; 82 bool flush_depthstencil_through_cb; 83 bool copy_depth, copy_stencil; 84}; 85 86struct r600_cb_misc_state { 87 struct r600_atom atom; 88 unsigned cb_color_control; /* this comes from blend state */ 89 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 90 unsigned nr_cbufs; 91 unsigned nr_ps_color_outputs; 92 bool multiwrite; 93 bool dual_src_blend; 94}; 95 96struct r600_alphatest_state { 97 struct r600_atom atom; 98 unsigned sx_alpha_test_control; /* this comes from dsa state */ 99 unsigned sx_alpha_ref; /* this comes from dsa state */ 100 bool bypass; 101 bool cb0_export_16bpc; /* from set_framebuffer_state */ 102}; 103 104struct r600_cs_shader_state { 105 struct r600_atom atom; 106 struct r600_pipe_compute *shader; 107}; 108 109enum r600_pipe_state_id { 110 R600_PIPE_STATE_BLEND = 0, 111 R600_PIPE_STATE_BLEND_COLOR, 112 R600_PIPE_STATE_CONFIG, 113 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 114 R600_PIPE_STATE_CLIP, 115 R600_PIPE_STATE_SCISSOR, 116 R600_PIPE_STATE_VIEWPORT, 117 R600_PIPE_STATE_RASTERIZER, 118 R600_PIPE_STATE_VGT, 119 R600_PIPE_STATE_FRAMEBUFFER, 120 R600_PIPE_STATE_DSA, 121 R600_PIPE_STATE_STENCIL_REF, 122 R600_PIPE_STATE_PS_SHADER, 123 R600_PIPE_STATE_VS_SHADER, 124 R600_PIPE_STATE_CONSTANT, 125 R600_PIPE_STATE_SAMPLER, 126 R600_PIPE_STATE_RESOURCE, 127 R600_PIPE_STATE_POLYGON_OFFSET, 128 R600_PIPE_STATE_FETCH_SHADER, 129 R600_PIPE_STATE_SPI, 130 R600_PIPE_NSTATES 131}; 132 133struct compute_memory_pool; 134void compute_memory_pool_delete(struct compute_memory_pool* pool); 135struct compute_memory_pool* compute_memory_pool_new( 136 struct r600_screen *rscreen); 137 138struct r600_pipe_fences { 139 struct r600_resource *bo; 140 unsigned *data; 141 unsigned next_index; 142 /* linked list of preallocated blocks */ 143 struct list_head blocks; 144 /* linked list of freed fences */ 145 struct list_head pool; 146 pipe_mutex mutex; 147}; 148 149struct r600_screen { 150 struct pipe_screen screen; 151 struct radeon_winsys *ws; 152 unsigned family; 153 enum chip_class chip_class; 154 struct radeon_info info; 155 bool has_streamout; 156 struct r600_tiling_info tiling_info; 157 struct r600_pipe_fences fences; 158 159 /*for compute global memory binding, we allocate stuff here, instead of 160 * buffers. 161 * XXX: Not sure if this is the best place for global_pool. Also, 162 * it's not thread safe, so it won't work with multiple contexts. */ 163 struct compute_memory_pool *global_pool; 164}; 165 166struct r600_pipe_sampler_view { 167 struct pipe_sampler_view base; 168 struct r600_resource *tex_resource; 169 uint32_t tex_resource_words[8]; 170}; 171 172struct r600_pipe_rasterizer { 173 struct r600_pipe_state rstate; 174 boolean flatshade; 175 boolean two_side; 176 unsigned sprite_coord_enable; 177 unsigned clip_plane_enable; 178 unsigned pa_sc_line_stipple; 179 unsigned pa_cl_clip_cntl; 180 float offset_units; 181 float offset_scale; 182 bool scissor_enable; 183 bool multisample_enable; 184}; 185 186struct r600_pipe_blend { 187 struct r600_pipe_state rstate; 188 unsigned cb_target_mask; 189 unsigned cb_color_control; 190 bool dual_src_blend; 191 bool alpha_to_one; 192}; 193 194struct r600_pipe_dsa { 195 struct r600_pipe_state rstate; 196 unsigned alpha_ref; 197 ubyte valuemask[2]; 198 ubyte writemask[2]; 199 unsigned sx_alpha_test_control; 200}; 201 202struct r600_vertex_element 203{ 204 unsigned count; 205 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 206 struct r600_resource *fetch_shader; 207 unsigned fs_size; 208 struct r600_pipe_state rstate; 209}; 210 211struct r600_pipe_shader; 212 213struct r600_pipe_shader_selector { 214 struct r600_pipe_shader *current; 215 216 struct tgsi_token *tokens; 217 struct pipe_stream_output_info so; 218 219 unsigned num_shaders; 220 221 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 222 unsigned type; 223 224 unsigned nr_ps_max_color_exports; 225}; 226 227struct r600_pipe_shader { 228 struct r600_pipe_shader_selector *selector; 229 struct r600_pipe_shader *next_variant; 230 struct r600_shader shader; 231 struct r600_pipe_state rstate; 232 struct r600_resource *bo; 233 struct r600_resource *bo_fetch; 234 struct r600_vertex_element vertex_elements; 235 unsigned sprite_coord_enable; 236 unsigned flatshade; 237 unsigned pa_cl_vs_out_cntl; 238 unsigned nr_ps_color_outputs; 239 unsigned key; 240 unsigned db_shader_control; 241 unsigned ps_depth_export; 242}; 243 244struct r600_pipe_sampler_state { 245 uint32_t tex_sampler_words[3]; 246 uint32_t border_color[4]; 247 bool border_color_use; 248 bool seamless_cube_map; 249}; 250 251/* needed for blitter save */ 252#define NUM_TEX_UNITS 16 253 254struct r600_seamless_cube_map { 255 struct r600_atom atom; 256 bool enabled; 257}; 258 259struct r600_samplerview_state { 260 struct r600_atom atom; 261 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 262 uint32_t enabled_mask; 263 uint32_t dirty_mask; 264 uint32_t depth_texture_mask; /* which textures are depth */ 265}; 266 267struct r600_textures_info { 268 struct r600_samplerview_state views; 269 struct r600_atom atom_sampler; 270 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 271 unsigned n_samplers; 272 bool is_array_sampler[NUM_TEX_UNITS]; 273}; 274 275struct r600_fence { 276 struct pipe_reference reference; 277 unsigned index; /* in the shared bo */ 278 struct r600_resource *sleep_bo; 279 struct list_head head; 280}; 281 282#define FENCE_BLOCK_SIZE 16 283 284struct r600_fence_block { 285 struct r600_fence fences[FENCE_BLOCK_SIZE]; 286 struct list_head head; 287}; 288 289#define R600_CONSTANT_ARRAY_SIZE 256 290#define R600_RESOURCE_ARRAY_SIZE 160 291 292struct r600_stencil_ref 293{ 294 ubyte ref_value[2]; 295 ubyte valuemask[2]; 296 ubyte writemask[2]; 297}; 298 299struct r600_constbuf_state 300{ 301 struct r600_atom atom; 302 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 303 uint32_t enabled_mask; 304 uint32_t dirty_mask; 305}; 306 307struct r600_vertexbuf_state 308{ 309 struct r600_atom atom; 310 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 311 uint32_t enabled_mask; /* non-NULL buffers */ 312 uint32_t dirty_mask; 313}; 314 315struct r600_context { 316 struct pipe_context context; 317 struct blitter_context *blitter; 318 enum radeon_family family; 319 enum chip_class chip_class; 320 boolean has_vertex_cache; 321 unsigned r6xx_num_clause_temp_gprs; 322 void *custom_dsa_flush; 323 struct r600_screen *screen; 324 struct radeon_winsys *ws; 325 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 326 struct r600_vertex_element *vertex_elements; 327 struct pipe_framebuffer_state framebuffer; 328 unsigned compute_cb_target_mask; 329 unsigned db_shader_control; 330 unsigned pa_sc_line_stipple; 331 unsigned pa_cl_clip_cntl; 332 /* for saving when using blitter */ 333 struct pipe_stencil_ref stencil_ref; 334 struct pipe_viewport_state viewport; 335 struct pipe_clip_state clip; 336 struct r600_pipe_shader_selector *ps_shader; 337 struct r600_pipe_shader_selector *vs_shader; 338 struct r600_pipe_rasterizer *rasterizer; 339 struct r600_pipe_state vgt; 340 struct r600_pipe_state spi; 341 struct pipe_query *current_render_cond; 342 unsigned current_render_cond_mode; 343 struct pipe_query *saved_render_cond; 344 unsigned saved_render_cond_mode; 345 /* shader information */ 346 boolean two_side; 347 boolean spi_dirty; 348 unsigned sprite_coord_enable; 349 boolean flatshade; 350 boolean export_16bpc; 351 unsigned nr_cbufs; 352 bool alpha_to_one; 353 bool multisample_enable; 354 bool cb0_is_integer; 355 356 struct u_upload_mgr *uploader; 357 struct util_slab_mempool pool_transfers; 358 359 unsigned default_ps_gprs, default_vs_gprs; 360 361 /* States based on r600_atom. */ 362 struct list_head dirty_states; 363 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 364 /** Compute specific registers initializations. The start_cs_cmd atom 365 * must be emitted before start_compute_cs_cmd. */ 366 struct r600_command_buffer start_compute_cs_cmd; 367 struct r600_surface_sync_cmd surface_sync_cmd; 368 struct r600_atom r6xx_flush_and_inv_cmd; 369 struct r600_alphatest_state alphatest_state; 370 struct r600_cb_misc_state cb_misc_state; 371 struct r600_db_misc_state db_misc_state; 372 /** Vertex buffers for fetch shaders */ 373 struct r600_vertexbuf_state vertex_buffer_state; 374 /** Vertex buffers for compute shaders */ 375 struct r600_vertexbuf_state cs_vertex_buffer_state; 376 struct r600_constbuf_state vs_constbuf_state; 377 struct r600_constbuf_state ps_constbuf_state; 378 struct r600_textures_info vs_samplers; 379 struct r600_textures_info ps_samplers; 380 struct r600_seamless_cube_map seamless_cube_map; 381 struct r600_cs_shader_state cs_shader_state; 382 383 struct radeon_winsys_cs *cs; 384 385 struct r600_range *range; 386 unsigned nblocks; 387 struct r600_block **blocks; 388 struct list_head dirty; 389 struct list_head enable_list; 390 unsigned pm4_dirty_cdwords; 391 unsigned ctx_pm4_ndwords; 392 393 /* The list of active queries. Only one query of each type can be active. */ 394 int num_occlusion_queries; 395 396 /* Manage queries in two separate groups: 397 * The timer ones and the others (streamout, occlusion). 398 * 399 * We do this because we should only suspend non-timer queries for u_blitter, 400 * and later if the non-timer queries are suspended, the context flush should 401 * only suspend and resume the timer queries. */ 402 struct list_head active_timer_queries; 403 unsigned num_cs_dw_timer_queries_suspend; 404 struct list_head active_nontimer_queries; 405 unsigned num_cs_dw_nontimer_queries_suspend; 406 407 unsigned num_cs_dw_streamout_end; 408 409 unsigned backend_mask; 410 unsigned max_db; /* for OQ */ 411 unsigned flags; 412 boolean predicate_drawing; 413 414 unsigned num_so_targets; 415 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 416 boolean streamout_start; 417 unsigned streamout_append_bitmask; 418 419 /* There is no scissor enable bit on r6xx, so we must use a workaround. 420 * These track the current scissor state. */ 421 bool scissor_enable; 422 struct pipe_scissor_state scissor_state; 423 424 /* With rasterizer discard, there doesn't have to be a pixel shader. 425 * In that case, we bind this one: */ 426 void *dummy_pixel_shader; 427 428 boolean dual_src_blend; 429 430 /* Index buffer. */ 431 struct pipe_index_buffer index_buffer; 432}; 433 434static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 435{ 436 atom->emit(rctx, atom); 437 atom->dirty = false; 438 if (atom->head.next && atom->head.prev) 439 LIST_DELINIT(&atom->head); 440} 441 442static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 443{ 444 if (!state->dirty) { 445 if (state->flags & EMIT_EARLY) { 446 LIST_ADD(&state->head, &rctx->dirty_states); 447 } else { 448 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 449 } 450 state->dirty = true; 451 } 452} 453 454/* evergreen_state.c */ 455void evergreen_init_state_functions(struct r600_context *rctx); 456void evergreen_init_atom_start_cs(struct r600_context *rctx); 457void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 458void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 459void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 460void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 461void evergreen_polygon_offset_update(struct r600_context *rctx); 462boolean evergreen_is_format_supported(struct pipe_screen *screen, 463 enum pipe_format format, 464 enum pipe_texture_target target, 465 unsigned sample_count, 466 unsigned usage); 467void evergreen_init_color_surface(struct r600_context *rctx, 468 struct r600_surface *surf); 469void evergreen_update_dual_export_state(struct r600_context * rctx); 470 471/* r600_blit.c */ 472void r600_copy_buffer(struct pipe_context *ctx, struct 473 pipe_resource *dst, unsigned dstx, 474 struct pipe_resource *src, const struct pipe_box *src_box); 475void r600_init_blit_functions(struct r600_context *rctx); 476void r600_blit_uncompress_depth(struct pipe_context *ctx, 477 struct r600_resource_texture *texture, 478 struct r600_resource_texture *staging, 479 unsigned first_level, unsigned last_level, 480 unsigned first_layer, unsigned last_layer); 481void r600_flush_depth_textures(struct r600_context *rctx, 482 struct r600_samplerview_state *textures); 483/* r600_buffer.c */ 484bool r600_init_resource(struct r600_screen *rscreen, 485 struct r600_resource *res, 486 unsigned size, unsigned alignment, 487 unsigned bind, unsigned usage); 488struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 489 const struct pipe_resource *templ); 490 491/* r600_pipe.c */ 492void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 493 unsigned flags); 494 495/* r600_query.c */ 496void r600_init_query_functions(struct r600_context *rctx); 497void r600_suspend_nontimer_queries(struct r600_context *ctx); 498void r600_resume_nontimer_queries(struct r600_context *ctx); 499void r600_suspend_timer_queries(struct r600_context *ctx); 500void r600_resume_timer_queries(struct r600_context *ctx); 501 502/* r600_resource.c */ 503void r600_init_context_resource_functions(struct r600_context *r600); 504 505/* r600_shader.c */ 506int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 507#ifdef HAVE_OPENCL 508int r600_compute_shader_create(struct pipe_context * ctx, 509 LLVMModuleRef mod, struct r600_bytecode * bytecode); 510#endif 511void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 512 513/* r600_state.c */ 514void r600_set_scissor_state(struct r600_context *rctx, 515 const struct pipe_scissor_state *state); 516void r600_init_state_functions(struct r600_context *rctx); 517void r600_init_atom_start_cs(struct r600_context *rctx); 518void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 519void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 520void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 521void *r600_create_db_flush_dsa(struct r600_context *rctx); 522void r600_polygon_offset_update(struct r600_context *rctx); 523void r600_adjust_gprs(struct r600_context *rctx); 524boolean r600_is_format_supported(struct pipe_screen *screen, 525 enum pipe_format format, 526 enum pipe_texture_target target, 527 unsigned sample_count, 528 unsigned usage); 529void r600_update_dual_export_state(struct r600_context * rctx); 530 531/* r600_texture.c */ 532void r600_init_screen_texture_functions(struct pipe_screen *screen); 533void r600_init_surface_functions(struct r600_context *r600); 534uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 535 const unsigned char *swizzle_view, 536 uint32_t *word4_p, uint32_t *yuv_format_p); 537unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 538 unsigned level, unsigned layer); 539 540/* r600_translate.c */ 541void r600_translate_index_buffer(struct r600_context *r600, 542 struct pipe_index_buffer *ib, 543 unsigned count); 544 545/* r600_state_common.c */ 546void r600_init_atom(struct r600_atom *atom, 547 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 548 unsigned num_dw, enum r600_atom_flags flags); 549void r600_init_common_atoms(struct r600_context *rctx); 550unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 551void r600_texture_barrier(struct pipe_context *ctx); 552void r600_set_index_buffer(struct pipe_context *ctx, 553 const struct pipe_index_buffer *ib); 554void r600_vertex_buffers_dirty(struct r600_context *rctx); 555void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 556 const struct pipe_vertex_buffer *input); 557void r600_sampler_views_dirty(struct r600_context *rctx, 558 struct r600_samplerview_state *state); 559void r600_set_sampler_views(struct r600_context *rctx, 560 struct r600_textures_info *dst, 561 unsigned count, 562 struct pipe_sampler_view **views); 563void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states); 564void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states); 565void *r600_create_vertex_elements(struct pipe_context *ctx, 566 unsigned count, 567 const struct pipe_vertex_element *elements); 568void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 569void r600_bind_blend_state(struct pipe_context *ctx, void *state); 570void r600_set_blend_color(struct pipe_context *ctx, 571 const struct pipe_blend_color *state); 572void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 573void r600_set_max_scissor(struct r600_context *rctx); 574void r600_bind_rs_state(struct pipe_context *ctx, void *state); 575void r600_delete_rs_state(struct pipe_context *ctx, void *state); 576void r600_sampler_view_destroy(struct pipe_context *ctx, 577 struct pipe_sampler_view *state); 578void r600_delete_sampler(struct pipe_context *ctx, void *state); 579void r600_delete_state(struct pipe_context *ctx, void *state); 580void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 581void *r600_create_shader_state_ps(struct pipe_context *ctx, 582 const struct pipe_shader_state *state); 583void *r600_create_shader_state_vs(struct pipe_context *ctx, 584 const struct pipe_shader_state *state); 585void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 586void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 587void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 588void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 589void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 590void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 591 struct pipe_constant_buffer *cb); 592struct pipe_stream_output_target * 593r600_create_so_target(struct pipe_context *ctx, 594 struct pipe_resource *buffer, 595 unsigned buffer_offset, 596 unsigned buffer_size); 597void r600_so_target_destroy(struct pipe_context *ctx, 598 struct pipe_stream_output_target *target); 599void r600_set_so_targets(struct pipe_context *ctx, 600 unsigned num_targets, 601 struct pipe_stream_output_target **targets, 602 unsigned append_bitmask); 603void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 604 const struct pipe_stencil_ref *state); 605void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 606uint32_t r600_translate_stencil_op(int s_op); 607uint32_t r600_translate_fill(uint32_t func); 608unsigned r600_tex_wrap(unsigned wrap); 609unsigned r600_tex_filter(unsigned filter); 610unsigned r600_tex_mipfilter(unsigned filter); 611unsigned r600_tex_compare(unsigned compare); 612 613/* 614 * Helpers for building command buffers 615 */ 616 617#define PKT3_SET_CONFIG_REG 0x68 618#define PKT3_SET_CONTEXT_REG 0x69 619#define PKT3_SET_CTL_CONST 0x6F 620#define PKT3_SET_LOOP_CONST 0x6C 621 622#define R600_CONFIG_REG_OFFSET 0x08000 623#define R600_CONTEXT_REG_OFFSET 0x28000 624#define R600_CTL_CONST_OFFSET 0x3CFF0 625#define R600_LOOP_CONST_OFFSET 0X0003E200 626#define EG_LOOP_CONST_OFFSET 0x0003A200 627 628#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 629#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 630#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 631#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 632#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 633 634#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 635 636/*Evergreen Compute packet3*/ 637#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) 638 639static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 640{ 641 cb->buf[cb->atom.num_dw++] = value; 642} 643 644static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 645{ 646 assert(reg < R600_CONTEXT_REG_OFFSET); 647 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 648 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 649 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 650} 651 652/** 653 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 654 * shaders. 655 */ 656static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 657{ 658 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 659 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 660 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 661 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 662} 663 664/** 665 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 666 * shaders. 667 */ 668static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 669{ 670 assert(reg >= R600_CTL_CONST_OFFSET); 671 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 672 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 673 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 674} 675 676static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 677{ 678 assert(reg >= R600_LOOP_CONST_OFFSET); 679 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 680 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 681 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 682} 683 684/** 685 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 686 * shaders. 687 */ 688static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 689{ 690 assert(reg >= EG_LOOP_CONST_OFFSET); 691 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 692 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 693 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 694} 695 696static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 697{ 698 r600_store_config_reg_seq(cb, reg, 1); 699 r600_store_value(cb, value); 700} 701 702static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 703{ 704 r600_store_context_reg_seq(cb, reg, 1); 705 r600_store_value(cb, value); 706} 707 708static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 709{ 710 r600_store_ctl_const_seq(cb, reg, 1); 711 r600_store_value(cb, value); 712} 713 714static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 715{ 716 r600_store_loop_const_seq(cb, reg, 1); 717 r600_store_value(cb, value); 718} 719 720static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 721{ 722 eg_store_loop_const_seq(cb, reg, 1); 723 r600_store_value(cb, value); 724} 725 726void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 727void r600_release_command_buffer(struct r600_command_buffer *cb); 728 729/* 730 * Helpers for emitting state into a command stream directly. 731 */ 732 733static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 734 enum radeon_bo_usage usage) 735{ 736 assert(usage); 737 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 738} 739 740static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 741{ 742 cs->buf[cs->cdw++] = value; 743} 744 745static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr) 746{ 747 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS); 748 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0])); 749 cs->cdw += num; 750} 751 752static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 753{ 754 assert(reg < R600_CONTEXT_REG_OFFSET); 755 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 756 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 757 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 758} 759 760static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 761{ 762 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 763 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 764 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 765 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 766} 767 768static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 769{ 770 r600_write_context_reg_seq(cs, reg, num); 771 /* Set the compute bit on the packet header */ 772 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; 773} 774 775static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 776{ 777 assert(reg >= R600_CTL_CONST_OFFSET); 778 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 779 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 780 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 781} 782 783static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 784{ 785 r600_write_config_reg_seq(cs, reg, 1); 786 r600_write_value(cs, value); 787} 788 789static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 790{ 791 r600_write_context_reg_seq(cs, reg, 1); 792 r600_write_value(cs, value); 793} 794 795static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 796{ 797 r600_write_compute_context_reg_seq(cs, reg, 1); 798 r600_write_value(cs, value); 799} 800 801static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 802{ 803 r600_write_ctl_const_seq(cs, reg, 1); 804 r600_write_value(cs, value); 805} 806 807/* 808 * common helpers 809 */ 810static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 811{ 812 return value * (1 << frac_bits); 813} 814#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 815 816static inline unsigned r600_tex_aniso_filter(unsigned filter) 817{ 818 if (filter <= 1) return 0; 819 if (filter <= 2) return 1; 820 if (filter <= 4) return 2; 821 if (filter <= 8) return 3; 822 /* else */ return 4; 823} 824 825/* 12.4 fixed-point */ 826static INLINE unsigned r600_pack_float_12p4(float x) 827{ 828 return x <= 0 ? 0 : 829 x >= 4096 ? 0xffff : x * 16; 830} 831 832static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 833{ 834 struct r600_screen *rscreen = (struct r600_screen*)screen; 835 struct r600_resource *rresource = (struct r600_resource*)resource; 836 837 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 838} 839 840#endif 841