r600_pipe.h revision 2df399c34bb39122a45bdd5b430b48346542e1cb
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71 unsigned pkt_flags; 72}; 73 74struct r600_surface_sync_cmd { 75 struct r600_atom atom; 76 unsigned flush_flags; /* CP_COHER_CNTL */ 77}; 78 79struct r600_db_misc_state { 80 struct r600_atom atom; 81 bool occlusion_query_enabled; 82 bool flush_depthstencil_through_cb; 83 bool copy_depth, copy_stencil; 84}; 85 86struct r600_cb_misc_state { 87 struct r600_atom atom; 88 unsigned cb_color_control; /* this comes from blend state */ 89 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 90 unsigned nr_cbufs; 91 unsigned nr_ps_color_outputs; 92 bool multiwrite; 93 bool dual_src_blend; 94}; 95 96struct r600_alphatest_state { 97 struct r600_atom atom; 98 unsigned sx_alpha_test_control; /* this comes from dsa state */ 99 unsigned sx_alpha_ref; /* this comes from dsa state */ 100 bool bypass; 101 bool cb0_export_16bpc; /* from set_framebuffer_state */ 102}; 103 104struct r600_cs_shader_state { 105 struct r600_atom atom; 106 struct r600_pipe_compute *shader; 107}; 108 109enum r600_pipe_state_id { 110 R600_PIPE_STATE_BLEND = 0, 111 R600_PIPE_STATE_BLEND_COLOR, 112 R600_PIPE_STATE_CONFIG, 113 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 114 R600_PIPE_STATE_CLIP, 115 R600_PIPE_STATE_SCISSOR, 116 R600_PIPE_STATE_VIEWPORT, 117 R600_PIPE_STATE_RASTERIZER, 118 R600_PIPE_STATE_VGT, 119 R600_PIPE_STATE_FRAMEBUFFER, 120 R600_PIPE_STATE_DSA, 121 R600_PIPE_STATE_STENCIL_REF, 122 R600_PIPE_STATE_PS_SHADER, 123 R600_PIPE_STATE_VS_SHADER, 124 R600_PIPE_STATE_CONSTANT, 125 R600_PIPE_STATE_SAMPLER, 126 R600_PIPE_STATE_RESOURCE, 127 R600_PIPE_STATE_POLYGON_OFFSET, 128 R600_PIPE_STATE_FETCH_SHADER, 129 R600_PIPE_STATE_SPI, 130 R600_PIPE_NSTATES 131}; 132 133struct compute_memory_pool; 134void compute_memory_pool_delete(struct compute_memory_pool* pool); 135struct compute_memory_pool* compute_memory_pool_new( 136 struct r600_screen *rscreen); 137 138struct r600_pipe_fences { 139 struct r600_resource *bo; 140 unsigned *data; 141 unsigned next_index; 142 /* linked list of preallocated blocks */ 143 struct list_head blocks; 144 /* linked list of freed fences */ 145 struct list_head pool; 146 pipe_mutex mutex; 147}; 148 149struct r600_screen { 150 struct pipe_screen screen; 151 struct radeon_winsys *ws; 152 unsigned family; 153 enum chip_class chip_class; 154 struct radeon_info info; 155 bool has_streamout; 156 struct r600_tiling_info tiling_info; 157 struct r600_pipe_fences fences; 158 159 /*for compute global memory binding, we allocate stuff here, instead of 160 * buffers. 161 * XXX: Not sure if this is the best place for global_pool. Also, 162 * it's not thread safe, so it won't work with multiple contexts. */ 163 struct compute_memory_pool *global_pool; 164}; 165 166struct r600_pipe_sampler_view { 167 struct pipe_sampler_view base; 168 struct r600_resource *tex_resource; 169 uint32_t tex_resource_words[8]; 170}; 171 172struct r600_pipe_rasterizer { 173 struct r600_pipe_state rstate; 174 boolean flatshade; 175 boolean two_side; 176 unsigned sprite_coord_enable; 177 unsigned clip_plane_enable; 178 unsigned pa_sc_line_stipple; 179 unsigned pa_cl_clip_cntl; 180 float offset_units; 181 float offset_scale; 182 bool scissor_enable; 183}; 184 185struct r600_pipe_blend { 186 struct r600_pipe_state rstate; 187 unsigned cb_target_mask; 188 unsigned cb_color_control; 189 bool dual_src_blend; 190}; 191 192struct r600_pipe_dsa { 193 struct r600_pipe_state rstate; 194 unsigned alpha_ref; 195 ubyte valuemask[2]; 196 ubyte writemask[2]; 197 unsigned sx_alpha_test_control; 198}; 199 200struct r600_vertex_element 201{ 202 unsigned count; 203 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 204 struct r600_resource *fetch_shader; 205 unsigned fs_size; 206 struct r600_pipe_state rstate; 207}; 208 209struct r600_pipe_shader; 210 211struct r600_pipe_shader_selector { 212 struct r600_pipe_shader *current; 213 214 struct tgsi_token *tokens; 215 struct pipe_stream_output_info so; 216 217 unsigned num_shaders; 218 219 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 220 unsigned type; 221 222 unsigned nr_ps_max_color_exports; 223}; 224 225struct r600_pipe_shader { 226 struct r600_pipe_shader_selector *selector; 227 struct r600_pipe_shader *next_variant; 228 struct r600_shader shader; 229 struct r600_pipe_state rstate; 230 struct r600_resource *bo; 231 struct r600_resource *bo_fetch; 232 struct r600_vertex_element vertex_elements; 233 unsigned sprite_coord_enable; 234 unsigned flatshade; 235 unsigned pa_cl_vs_out_cntl; 236 unsigned nr_ps_color_outputs; 237 unsigned key; 238 unsigned db_shader_control; 239 unsigned ps_depth_export; 240}; 241 242struct r600_pipe_sampler_state { 243 uint32_t tex_sampler_words[3]; 244 uint32_t border_color[4]; 245 bool border_color_use; 246 bool seamless_cube_map; 247}; 248 249/* needed for blitter save */ 250#define NUM_TEX_UNITS 16 251 252struct r600_seamless_cube_map { 253 struct r600_atom atom; 254 bool enabled; 255}; 256 257struct r600_samplerview_state { 258 struct r600_atom atom; 259 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 260 uint32_t enabled_mask; 261 uint32_t dirty_mask; 262 uint32_t depth_texture_mask; /* which textures are depth */ 263}; 264 265struct r600_textures_info { 266 struct r600_samplerview_state views; 267 struct r600_atom atom_sampler; 268 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 269 unsigned n_samplers; 270 bool is_array_sampler[NUM_TEX_UNITS]; 271}; 272 273struct r600_fence { 274 struct pipe_reference reference; 275 unsigned index; /* in the shared bo */ 276 struct r600_resource *sleep_bo; 277 struct list_head head; 278}; 279 280#define FENCE_BLOCK_SIZE 16 281 282struct r600_fence_block { 283 struct r600_fence fences[FENCE_BLOCK_SIZE]; 284 struct list_head head; 285}; 286 287#define R600_CONSTANT_ARRAY_SIZE 256 288#define R600_RESOURCE_ARRAY_SIZE 160 289 290struct r600_stencil_ref 291{ 292 ubyte ref_value[2]; 293 ubyte valuemask[2]; 294 ubyte writemask[2]; 295}; 296 297struct r600_constbuf_state 298{ 299 struct r600_atom atom; 300 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 301 uint32_t enabled_mask; 302 uint32_t dirty_mask; 303}; 304 305struct r600_vertexbuf_state 306{ 307 struct r600_atom atom; 308 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 309 uint32_t enabled_mask; /* non-NULL buffers */ 310 uint32_t dirty_mask; 311}; 312 313struct r600_context { 314 struct pipe_context context; 315 struct blitter_context *blitter; 316 enum radeon_family family; 317 enum chip_class chip_class; 318 boolean has_vertex_cache; 319 unsigned r6xx_num_clause_temp_gprs; 320 void *custom_dsa_flush; 321 struct r600_screen *screen; 322 struct radeon_winsys *ws; 323 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 324 struct r600_vertex_element *vertex_elements; 325 struct pipe_framebuffer_state framebuffer; 326 unsigned compute_cb_target_mask; 327 unsigned db_shader_control; 328 unsigned pa_sc_line_stipple; 329 unsigned pa_cl_clip_cntl; 330 /* for saving when using blitter */ 331 struct pipe_stencil_ref stencil_ref; 332 struct pipe_viewport_state viewport; 333 struct pipe_clip_state clip; 334 struct r600_pipe_shader_selector *ps_shader; 335 struct r600_pipe_shader_selector *vs_shader; 336 struct r600_pipe_rasterizer *rasterizer; 337 struct r600_pipe_state vgt; 338 struct r600_pipe_state spi; 339 struct pipe_query *current_render_cond; 340 unsigned current_render_cond_mode; 341 struct pipe_query *saved_render_cond; 342 unsigned saved_render_cond_mode; 343 /* shader information */ 344 boolean two_side; 345 boolean spi_dirty; 346 unsigned sprite_coord_enable; 347 boolean flatshade; 348 boolean export_16bpc; 349 unsigned nr_cbufs; 350 351 struct u_upload_mgr *uploader; 352 struct util_slab_mempool pool_transfers; 353 354 unsigned default_ps_gprs, default_vs_gprs; 355 356 /* States based on r600_atom. */ 357 struct list_head dirty_states; 358 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 359 /** Compute specific registers initializations. The start_cs_cmd atom 360 * must be emitted before start_compute_cs_cmd. */ 361 struct r600_command_buffer start_compute_cs_cmd; 362 struct r600_surface_sync_cmd surface_sync_cmd; 363 struct r600_atom r6xx_flush_and_inv_cmd; 364 struct r600_alphatest_state alphatest_state; 365 struct r600_cb_misc_state cb_misc_state; 366 struct r600_db_misc_state db_misc_state; 367 /** Vertex buffers for fetch shaders */ 368 struct r600_vertexbuf_state vertex_buffer_state; 369 /** Vertex buffers for compute shaders */ 370 struct r600_vertexbuf_state cs_vertex_buffer_state; 371 struct r600_constbuf_state vs_constbuf_state; 372 struct r600_constbuf_state ps_constbuf_state; 373 struct r600_textures_info vs_samplers; 374 struct r600_textures_info ps_samplers; 375 struct r600_seamless_cube_map seamless_cube_map; 376 struct r600_cs_shader_state cs_shader_state; 377 378 struct radeon_winsys_cs *cs; 379 380 struct r600_range *range; 381 unsigned nblocks; 382 struct r600_block **blocks; 383 struct list_head dirty; 384 struct list_head enable_list; 385 unsigned pm4_dirty_cdwords; 386 unsigned ctx_pm4_ndwords; 387 388 /* The list of active queries. Only one query of each type can be active. */ 389 int num_occlusion_queries; 390 391 /* Manage queries in two separate groups: 392 * The timer ones and the others (streamout, occlusion). 393 * 394 * We do this because we should only suspend non-timer queries for u_blitter, 395 * and later if the non-timer queries are suspended, the context flush should 396 * only suspend and resume the timer queries. */ 397 struct list_head active_timer_queries; 398 unsigned num_cs_dw_timer_queries_suspend; 399 struct list_head active_nontimer_queries; 400 unsigned num_cs_dw_nontimer_queries_suspend; 401 402 unsigned num_cs_dw_streamout_end; 403 404 unsigned backend_mask; 405 unsigned max_db; /* for OQ */ 406 unsigned flags; 407 boolean predicate_drawing; 408 409 unsigned num_so_targets; 410 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 411 boolean streamout_start; 412 unsigned streamout_append_bitmask; 413 414 /* There is no scissor enable bit on r6xx, so we must use a workaround. 415 * These track the current scissor state. */ 416 bool scissor_enable; 417 struct pipe_scissor_state scissor_state; 418 419 /* With rasterizer discard, there doesn't have to be a pixel shader. 420 * In that case, we bind this one: */ 421 void *dummy_pixel_shader; 422 423 boolean dual_src_blend; 424 425 /* Index buffer. */ 426 struct pipe_index_buffer index_buffer; 427}; 428 429static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 430{ 431 atom->emit(rctx, atom); 432 atom->dirty = false; 433 if (atom->head.next && atom->head.prev) 434 LIST_DELINIT(&atom->head); 435} 436 437static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 438{ 439 if (!state->dirty) { 440 if (state->flags & EMIT_EARLY) { 441 LIST_ADD(&state->head, &rctx->dirty_states); 442 } else { 443 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 444 } 445 state->dirty = true; 446 } 447} 448 449/* evergreen_state.c */ 450void evergreen_init_state_functions(struct r600_context *rctx); 451void evergreen_init_atom_start_cs(struct r600_context *rctx); 452void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 453void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 454void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 455void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 456void evergreen_polygon_offset_update(struct r600_context *rctx); 457boolean evergreen_is_format_supported(struct pipe_screen *screen, 458 enum pipe_format format, 459 enum pipe_texture_target target, 460 unsigned sample_count, 461 unsigned usage); 462void evergreen_init_color_surface(struct r600_context *rctx, 463 struct r600_surface *surf); 464void evergreen_update_dual_export_state(struct r600_context * rctx); 465 466/* r600_blit.c */ 467void r600_copy_buffer(struct pipe_context *ctx, struct 468 pipe_resource *dst, unsigned dstx, 469 struct pipe_resource *src, const struct pipe_box *src_box); 470void r600_init_blit_functions(struct r600_context *rctx); 471void r600_blit_uncompress_depth(struct pipe_context *ctx, 472 struct r600_resource_texture *texture, 473 struct r600_resource_texture *staging, 474 unsigned first_level, unsigned last_level, 475 unsigned first_layer, unsigned last_layer); 476void r600_flush_depth_textures(struct r600_context *rctx, 477 struct r600_samplerview_state *textures); 478/* r600_buffer.c */ 479bool r600_init_resource(struct r600_screen *rscreen, 480 struct r600_resource *res, 481 unsigned size, unsigned alignment, 482 unsigned bind, unsigned usage); 483struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 484 const struct pipe_resource *templ); 485 486/* r600_pipe.c */ 487void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 488 unsigned flags); 489 490/* r600_query.c */ 491void r600_init_query_functions(struct r600_context *rctx); 492void r600_suspend_nontimer_queries(struct r600_context *ctx); 493void r600_resume_nontimer_queries(struct r600_context *ctx); 494void r600_suspend_timer_queries(struct r600_context *ctx); 495void r600_resume_timer_queries(struct r600_context *ctx); 496 497/* r600_resource.c */ 498void r600_init_context_resource_functions(struct r600_context *r600); 499 500/* r600_shader.c */ 501int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 502#ifdef HAVE_OPENCL 503int r600_compute_shader_create(struct pipe_context * ctx, 504 LLVMModuleRef mod, struct r600_bytecode * bytecode); 505#endif 506void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 507 508/* r600_state.c */ 509void r600_set_scissor_state(struct r600_context *rctx, 510 const struct pipe_scissor_state *state); 511void r600_init_state_functions(struct r600_context *rctx); 512void r600_init_atom_start_cs(struct r600_context *rctx); 513void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 514void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 515void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 516void *r600_create_db_flush_dsa(struct r600_context *rctx); 517void r600_polygon_offset_update(struct r600_context *rctx); 518void r600_adjust_gprs(struct r600_context *rctx); 519boolean r600_is_format_supported(struct pipe_screen *screen, 520 enum pipe_format format, 521 enum pipe_texture_target target, 522 unsigned sample_count, 523 unsigned usage); 524void r600_update_dual_export_state(struct r600_context * rctx); 525 526/* r600_texture.c */ 527void r600_init_screen_texture_functions(struct pipe_screen *screen); 528void r600_init_surface_functions(struct r600_context *r600); 529uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 530 const unsigned char *swizzle_view, 531 uint32_t *word4_p, uint32_t *yuv_format_p); 532unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 533 unsigned level, unsigned layer); 534 535/* r600_translate.c */ 536void r600_translate_index_buffer(struct r600_context *r600, 537 struct pipe_index_buffer *ib, 538 unsigned count); 539 540/* r600_state_common.c */ 541void r600_init_atom(struct r600_atom *atom, 542 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 543 unsigned num_dw, enum r600_atom_flags flags); 544void r600_init_common_atoms(struct r600_context *rctx); 545unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 546void r600_texture_barrier(struct pipe_context *ctx); 547void r600_set_index_buffer(struct pipe_context *ctx, 548 const struct pipe_index_buffer *ib); 549void r600_vertex_buffers_dirty(struct r600_context *rctx); 550void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 551 const struct pipe_vertex_buffer *input); 552void r600_sampler_views_dirty(struct r600_context *rctx, 553 struct r600_samplerview_state *state); 554void r600_set_sampler_views(struct r600_context *rctx, 555 struct r600_textures_info *dst, 556 unsigned count, 557 struct pipe_sampler_view **views); 558void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states); 559void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states); 560void *r600_create_vertex_elements(struct pipe_context *ctx, 561 unsigned count, 562 const struct pipe_vertex_element *elements); 563void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 564void r600_bind_blend_state(struct pipe_context *ctx, void *state); 565void r600_set_blend_color(struct pipe_context *ctx, 566 const struct pipe_blend_color *state); 567void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 568void r600_set_max_scissor(struct r600_context *rctx); 569void r600_bind_rs_state(struct pipe_context *ctx, void *state); 570void r600_delete_rs_state(struct pipe_context *ctx, void *state); 571void r600_sampler_view_destroy(struct pipe_context *ctx, 572 struct pipe_sampler_view *state); 573void r600_delete_sampler(struct pipe_context *ctx, void *state); 574void r600_delete_state(struct pipe_context *ctx, void *state); 575void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 576void *r600_create_shader_state_ps(struct pipe_context *ctx, 577 const struct pipe_shader_state *state); 578void *r600_create_shader_state_vs(struct pipe_context *ctx, 579 const struct pipe_shader_state *state); 580void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 581void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 582void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 583void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 584void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 585void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 586 struct pipe_constant_buffer *cb); 587struct pipe_stream_output_target * 588r600_create_so_target(struct pipe_context *ctx, 589 struct pipe_resource *buffer, 590 unsigned buffer_offset, 591 unsigned buffer_size); 592void r600_so_target_destroy(struct pipe_context *ctx, 593 struct pipe_stream_output_target *target); 594void r600_set_so_targets(struct pipe_context *ctx, 595 unsigned num_targets, 596 struct pipe_stream_output_target **targets, 597 unsigned append_bitmask); 598void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 599 const struct pipe_stencil_ref *state); 600void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 601uint32_t r600_translate_stencil_op(int s_op); 602uint32_t r600_translate_fill(uint32_t func); 603unsigned r600_tex_wrap(unsigned wrap); 604unsigned r600_tex_filter(unsigned filter); 605unsigned r600_tex_mipfilter(unsigned filter); 606unsigned r600_tex_compare(unsigned compare); 607 608/* 609 * Helpers for building command buffers 610 */ 611 612#define PKT3_SET_CONFIG_REG 0x68 613#define PKT3_SET_CONTEXT_REG 0x69 614#define PKT3_SET_CTL_CONST 0x6F 615#define PKT3_SET_LOOP_CONST 0x6C 616 617#define R600_CONFIG_REG_OFFSET 0x08000 618#define R600_CONTEXT_REG_OFFSET 0x28000 619#define R600_CTL_CONST_OFFSET 0x3CFF0 620#define R600_LOOP_CONST_OFFSET 0X0003E200 621#define EG_LOOP_CONST_OFFSET 0x0003A200 622 623#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 624#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 625#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 626#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 627#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 628 629#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 630 631/*Evergreen Compute packet3*/ 632#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) 633 634static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 635{ 636 cb->buf[cb->atom.num_dw++] = value; 637} 638 639static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 640{ 641 assert(reg < R600_CONTEXT_REG_OFFSET); 642 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 643 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 644 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 645} 646 647/** 648 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 649 * shaders. 650 */ 651static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 652{ 653 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 654 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 655 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 656 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 657} 658 659/** 660 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 661 * shaders. 662 */ 663static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 664{ 665 assert(reg >= R600_CTL_CONST_OFFSET); 666 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 667 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 668 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 669} 670 671static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 672{ 673 assert(reg >= R600_LOOP_CONST_OFFSET); 674 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 675 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 676 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 677} 678 679/** 680 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 681 * shaders. 682 */ 683static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 684{ 685 assert(reg >= EG_LOOP_CONST_OFFSET); 686 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 687 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 688 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 689} 690 691static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 692{ 693 r600_store_config_reg_seq(cb, reg, 1); 694 r600_store_value(cb, value); 695} 696 697static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 698{ 699 r600_store_context_reg_seq(cb, reg, 1); 700 r600_store_value(cb, value); 701} 702 703static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 704{ 705 r600_store_ctl_const_seq(cb, reg, 1); 706 r600_store_value(cb, value); 707} 708 709static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 710{ 711 r600_store_loop_const_seq(cb, reg, 1); 712 r600_store_value(cb, value); 713} 714 715static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 716{ 717 eg_store_loop_const_seq(cb, reg, 1); 718 r600_store_value(cb, value); 719} 720 721void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 722void r600_release_command_buffer(struct r600_command_buffer *cb); 723 724/* 725 * Helpers for emitting state into a command stream directly. 726 */ 727 728static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 729 enum radeon_bo_usage usage) 730{ 731 assert(usage); 732 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 733} 734 735static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 736{ 737 cs->buf[cs->cdw++] = value; 738} 739 740static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr) 741{ 742 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS); 743 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0])); 744 cs->cdw += num; 745} 746 747static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 748{ 749 assert(reg < R600_CONTEXT_REG_OFFSET); 750 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 751 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 752 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 753} 754 755static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 756{ 757 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 758 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 759 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 760 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 761} 762 763static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 764{ 765 r600_write_context_reg_seq(cs, reg, num); 766 /* Set the compute bit on the packet header */ 767 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; 768} 769 770static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 771{ 772 assert(reg >= R600_CTL_CONST_OFFSET); 773 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 774 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 775 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 776} 777 778static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 779{ 780 r600_write_config_reg_seq(cs, reg, 1); 781 r600_write_value(cs, value); 782} 783 784static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 785{ 786 r600_write_context_reg_seq(cs, reg, 1); 787 r600_write_value(cs, value); 788} 789 790static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 791{ 792 r600_write_compute_context_reg_seq(cs, reg, 1); 793 r600_write_value(cs, value); 794} 795 796static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 797{ 798 r600_write_ctl_const_seq(cs, reg, 1); 799 r600_write_value(cs, value); 800} 801 802/* 803 * common helpers 804 */ 805static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 806{ 807 return value * (1 << frac_bits); 808} 809#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 810 811static inline unsigned r600_tex_aniso_filter(unsigned filter) 812{ 813 if (filter <= 1) return 0; 814 if (filter <= 2) return 1; 815 if (filter <= 4) return 2; 816 if (filter <= 8) return 3; 817 /* else */ return 4; 818} 819 820/* 12.4 fixed-point */ 821static INLINE unsigned r600_pack_float_12p4(float x) 822{ 823 return x <= 0 ? 0 : 824 x >= 4096 ? 0xffff : x * 16; 825} 826 827static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 828{ 829 struct r600_screen *rscreen = (struct r600_screen*)screen; 830 struct r600_resource *rresource = (struct r600_resource*)resource; 831 832 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 833} 834 835#endif 836