r600_pipe.h revision 470d00c0e270c6079232d0d5ab10bf3219768faf
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71}; 72 73struct r600_surface_sync_cmd { 74 struct r600_atom atom; 75 unsigned flush_flags; /* CP_COHER_CNTL */ 76}; 77 78struct r600_db_misc_state { 79 struct r600_atom atom; 80 bool occlusion_query_enabled; 81 bool flush_depthstencil_enabled; 82}; 83 84enum r600_pipe_state_id { 85 R600_PIPE_STATE_BLEND = 0, 86 R600_PIPE_STATE_BLEND_COLOR, 87 R600_PIPE_STATE_CONFIG, 88 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 89 R600_PIPE_STATE_CLIP, 90 R600_PIPE_STATE_SCISSOR, 91 R600_PIPE_STATE_VIEWPORT, 92 R600_PIPE_STATE_RASTERIZER, 93 R600_PIPE_STATE_VGT, 94 R600_PIPE_STATE_FRAMEBUFFER, 95 R600_PIPE_STATE_DSA, 96 R600_PIPE_STATE_STENCIL_REF, 97 R600_PIPE_STATE_PS_SHADER, 98 R600_PIPE_STATE_VS_SHADER, 99 R600_PIPE_STATE_CONSTANT, 100 R600_PIPE_STATE_SAMPLER, 101 R600_PIPE_STATE_RESOURCE, 102 R600_PIPE_STATE_POLYGON_OFFSET, 103 R600_PIPE_STATE_FETCH_SHADER, 104 R600_PIPE_STATE_SPI, 105 R600_PIPE_NSTATES 106}; 107 108struct compute_memory_pool; 109void compute_memory_pool_delete(struct compute_memory_pool* pool); 110struct compute_memory_pool* compute_memory_pool_new( 111 int64_t initial_size_in_dw, 112 struct r600_screen *rscreen); 113 114struct r600_pipe_fences { 115 struct r600_resource *bo; 116 unsigned *data; 117 unsigned next_index; 118 /* linked list of preallocated blocks */ 119 struct list_head blocks; 120 /* linked list of freed fences */ 121 struct list_head pool; 122 pipe_mutex mutex; 123}; 124 125struct r600_screen { 126 struct pipe_screen screen; 127 struct radeon_winsys *ws; 128 unsigned family; 129 enum chip_class chip_class; 130 struct radeon_info info; 131 bool has_streamout; 132 struct r600_tiling_info tiling_info; 133 struct r600_pipe_fences fences; 134 135 bool use_surface_alloc; 136 int glsl_feature_level; 137 138 /*for compute global memory binding, we allocate stuff here, instead of 139 * buffers. 140 * XXX: Not sure if this is the best place for global_pool. Also, 141 * it's not thread safe, so it won't work with multiple contexts. */ 142 struct compute_memory_pool *global_pool; 143}; 144 145struct r600_pipe_sampler_view { 146 struct pipe_sampler_view base; 147 struct r600_pipe_resource_state state; 148}; 149 150struct r600_pipe_rasterizer { 151 struct r600_pipe_state rstate; 152 boolean flatshade; 153 boolean two_side; 154 unsigned sprite_coord_enable; 155 unsigned clip_plane_enable; 156 unsigned pa_sc_line_stipple; 157 unsigned pa_cl_clip_cntl; 158 float offset_units; 159 float offset_scale; 160 bool scissor_enable; 161}; 162 163struct r600_pipe_blend { 164 struct r600_pipe_state rstate; 165 unsigned cb_target_mask; 166 unsigned cb_color_control; 167 bool dual_src_blend; 168}; 169 170struct r600_pipe_dsa { 171 struct r600_pipe_state rstate; 172 unsigned alpha_ref; 173 ubyte valuemask[2]; 174 ubyte writemask[2]; 175 bool is_flush; 176 unsigned sx_alpha_test_control; 177}; 178 179struct r600_vertex_element 180{ 181 unsigned count; 182 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 183 struct r600_resource *fetch_shader; 184 unsigned fs_size; 185 struct r600_pipe_state rstate; 186}; 187 188struct r600_pipe_shader; 189 190struct r600_pipe_shader_selector { 191 struct r600_pipe_shader *current; 192 193 struct tgsi_token *tokens; 194 struct pipe_stream_output_info so; 195 196 unsigned num_shaders; 197 198 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 199 unsigned type; 200 201 unsigned nr_ps_max_color_exports; 202}; 203 204struct r600_pipe_shader { 205 struct r600_pipe_shader_selector *selector; 206 struct r600_pipe_shader *next_variant; 207 struct r600_shader shader; 208 struct r600_pipe_state rstate; 209 struct r600_resource *bo; 210 struct r600_resource *bo_fetch; 211 struct r600_vertex_element vertex_elements; 212 unsigned sprite_coord_enable; 213 unsigned flatshade; 214 unsigned pa_cl_vs_out_cntl; 215 unsigned ps_cb_shader_mask; 216 unsigned key; 217 unsigned db_shader_control; 218 unsigned ps_depth_export; 219}; 220 221struct r600_pipe_sampler_state { 222 struct r600_pipe_state rstate; 223 boolean seamless_cube_map; 224}; 225 226/* needed for blitter save */ 227#define NUM_TEX_UNITS 16 228 229struct r600_textures_info { 230 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 231 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 232 unsigned n_views; 233 unsigned n_samplers; 234 bool samplers_dirty; 235 bool is_array_sampler[NUM_TEX_UNITS]; 236}; 237 238struct r600_fence { 239 struct pipe_reference reference; 240 unsigned index; /* in the shared bo */ 241 struct r600_resource *sleep_bo; 242 struct list_head head; 243}; 244 245#define FENCE_BLOCK_SIZE 16 246 247struct r600_fence_block { 248 struct r600_fence fences[FENCE_BLOCK_SIZE]; 249 struct list_head head; 250}; 251 252#define R600_CONSTANT_ARRAY_SIZE 256 253#define R600_RESOURCE_ARRAY_SIZE 160 254 255struct r600_stencil_ref 256{ 257 ubyte ref_value[2]; 258 ubyte valuemask[2]; 259 ubyte writemask[2]; 260}; 261 262struct r600_constbuf_state 263{ 264 struct r600_atom atom; 265 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 266 uint32_t enabled_mask; 267 uint32_t dirty_mask; 268}; 269 270struct r600_context { 271 struct pipe_context context; 272 struct blitter_context *blitter; 273 enum radeon_family family; 274 enum chip_class chip_class; 275 boolean has_vertex_cache; 276 unsigned r6xx_num_clause_temp_gprs; 277 void *custom_dsa_flush; 278 struct r600_screen *screen; 279 struct radeon_winsys *ws; 280 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 281 struct r600_vertex_element *vertex_elements; 282 struct pipe_framebuffer_state framebuffer; 283 unsigned cb_target_mask; 284 unsigned fb_cb_shader_mask; 285 unsigned sx_alpha_test_control; 286 unsigned cb_shader_mask; 287 unsigned db_shader_control; 288 unsigned cb_color_control; 289 unsigned pa_sc_line_stipple; 290 unsigned pa_cl_clip_cntl; 291 /* for saving when using blitter */ 292 struct pipe_stencil_ref stencil_ref; 293 struct pipe_viewport_state viewport; 294 struct pipe_clip_state clip; 295 struct r600_pipe_shader_selector *ps_shader; 296 struct r600_pipe_shader_selector *vs_shader; 297 struct r600_pipe_compute *cs_shader; 298 struct r600_pipe_rasterizer *rasterizer; 299 struct r600_pipe_state vgt; 300 struct r600_pipe_state spi; 301 struct pipe_query *current_render_cond; 302 unsigned current_render_cond_mode; 303 struct pipe_query *saved_render_cond; 304 unsigned saved_render_cond_mode; 305 /* shader information */ 306 boolean two_side; 307 boolean spi_dirty; 308 unsigned sprite_coord_enable; 309 boolean flatshade; 310 boolean export_16bpc; 311 unsigned alpha_ref; 312 boolean alpha_ref_dirty; 313 unsigned nr_cbufs; 314 struct r600_textures_info vs_samplers; 315 struct r600_textures_info ps_samplers; 316 317 struct u_upload_mgr *uploader; 318 struct util_slab_mempool pool_transfers; 319 boolean have_depth_texture, have_depth_fb; 320 321 unsigned default_ps_gprs, default_vs_gprs; 322 323 /* States based on r600_atom. */ 324 struct list_head dirty_states; 325 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 326 struct r600_surface_sync_cmd surface_sync_cmd; 327 struct r600_atom r6xx_flush_and_inv_cmd; 328 struct r600_db_misc_state db_misc_state; 329 struct r600_atom vertex_buffer_state; 330 struct r600_constbuf_state vs_constbuf_state; 331 struct r600_constbuf_state ps_constbuf_state; 332 333 struct radeon_winsys_cs *cs; 334 335 struct r600_range *range; 336 unsigned nblocks; 337 struct r600_block **blocks; 338 struct list_head dirty; 339 struct list_head resource_dirty; 340 struct list_head enable_list; 341 unsigned pm4_dirty_cdwords; 342 unsigned ctx_pm4_ndwords; 343 344 /* The list of active queries. Only one query of each type can be active. */ 345 int num_occlusion_queries; 346 347 /* Manage queries in two separate groups: 348 * The timer ones and the others (streamout, occlusion). 349 * 350 * We do this because we should only suspend non-timer queries for u_blitter, 351 * and later if the non-timer queries are suspended, the context flush should 352 * only suspend and resume the timer queries. */ 353 struct list_head active_timer_queries; 354 unsigned num_cs_dw_timer_queries_suspend; 355 struct list_head active_nontimer_queries; 356 unsigned num_cs_dw_nontimer_queries_suspend; 357 358 unsigned num_cs_dw_streamout_end; 359 360 unsigned backend_mask; 361 unsigned max_db; /* for OQ */ 362 unsigned flags; 363 boolean predicate_drawing; 364 struct r600_range ps_resources; 365 struct r600_range vs_resources; 366 int num_ps_resources, num_vs_resources; 367 368 unsigned num_so_targets; 369 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 370 boolean streamout_start; 371 unsigned streamout_append_bitmask; 372 373 /* There is no scissor enable bit on r6xx, so we must use a workaround. 374 * These track the current scissor state. */ 375 bool scissor_enable; 376 struct pipe_scissor_state scissor_state; 377 378 /* With rasterizer discard, there doesn't have to be a pixel shader. 379 * In that case, we bind this one: */ 380 void *dummy_pixel_shader; 381 382 boolean dual_src_blend; 383 384 /* Vertex and index buffers. */ 385 bool vertex_buffers_dirty; 386 struct pipe_index_buffer index_buffer; 387 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; 388 unsigned nr_vertex_buffers; 389}; 390 391static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 392{ 393 atom->emit(rctx, atom); 394 atom->dirty = false; 395 if (atom->head.next && atom->head.prev) 396 LIST_DELINIT(&atom->head); 397} 398 399static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 400{ 401 if (!state->dirty) { 402 if (state->flags & EMIT_EARLY) { 403 LIST_ADD(&state->head, &rctx->dirty_states); 404 } else { 405 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 406 } 407 state->dirty = true; 408 } 409} 410 411/* evergreen_state.c */ 412void evergreen_init_state_functions(struct r600_context *rctx); 413void evergreen_init_atom_start_cs(struct r600_context *rctx); 414void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 415void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 416void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 417void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 418void evergreen_polygon_offset_update(struct r600_context *rctx); 419boolean evergreen_is_format_supported(struct pipe_screen *screen, 420 enum pipe_format format, 421 enum pipe_texture_target target, 422 unsigned sample_count, 423 unsigned usage); 424 425void evergreen_update_dual_export_state(struct r600_context * rctx); 426 427/* r600_blit.c */ 428void r600_init_blit_functions(struct r600_context *rctx); 429void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 430void r600_flush_depth_textures(struct r600_context *rctx); 431 432/* r600_buffer.c */ 433bool r600_init_resource(struct r600_screen *rscreen, 434 struct r600_resource *res, 435 unsigned size, unsigned alignment, 436 unsigned bind, unsigned usage); 437struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 438 const struct pipe_resource *templ); 439 440/* r600_pipe.c */ 441void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 442 unsigned flags); 443 444/* r600_query.c */ 445void r600_init_query_functions(struct r600_context *rctx); 446void r600_suspend_nontimer_queries(struct r600_context *ctx); 447void r600_resume_nontimer_queries(struct r600_context *ctx); 448void r600_suspend_timer_queries(struct r600_context *ctx); 449void r600_resume_timer_queries(struct r600_context *ctx); 450 451/* r600_resource.c */ 452void r600_init_context_resource_functions(struct r600_context *r600); 453 454/* r600_shader.c */ 455int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 456#ifdef HAVE_OPENCL 457int r600_compute_shader_create(struct pipe_context * ctx, 458 LLVMModuleRef mod, struct r600_bytecode * bytecode); 459#endif 460void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 461 462/* r600_state.c */ 463void r600_set_scissor_state(struct r600_context *rctx, 464 const struct pipe_scissor_state *state); 465void r600_update_sampler_states(struct r600_context *rctx); 466void r600_init_state_functions(struct r600_context *rctx); 467void r600_init_atom_start_cs(struct r600_context *rctx); 468void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 469void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 470void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 471void *r600_create_db_flush_dsa(struct r600_context *rctx); 472void r600_polygon_offset_update(struct r600_context *rctx); 473void r600_adjust_gprs(struct r600_context *rctx); 474boolean r600_is_format_supported(struct pipe_screen *screen, 475 enum pipe_format format, 476 enum pipe_texture_target target, 477 unsigned sample_count, 478 unsigned usage); 479 480/* r600_texture.c */ 481void r600_init_screen_texture_functions(struct pipe_screen *screen); 482void r600_init_surface_functions(struct r600_context *r600); 483uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 484 const unsigned char *swizzle_view, 485 uint32_t *word4_p, uint32_t *yuv_format_p); 486unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 487 unsigned level, unsigned layer); 488 489/* r600_translate.c */ 490void r600_translate_index_buffer(struct r600_context *r600, 491 struct pipe_index_buffer *ib, 492 unsigned count); 493 494/* r600_state_common.c */ 495void r600_init_atom(struct r600_atom *atom, 496 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 497 unsigned num_dw, enum r600_atom_flags flags); 498void r600_init_common_atoms(struct r600_context *rctx); 499unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 500void r600_texture_barrier(struct pipe_context *ctx); 501void r600_set_index_buffer(struct pipe_context *ctx, 502 const struct pipe_index_buffer *ib); 503void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 504 const struct pipe_vertex_buffer *buffers); 505void *r600_create_vertex_elements(struct pipe_context *ctx, 506 unsigned count, 507 const struct pipe_vertex_element *elements); 508void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 509void r600_bind_blend_state(struct pipe_context *ctx, void *state); 510void r600_set_blend_color(struct pipe_context *ctx, 511 const struct pipe_blend_color *state); 512void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 513void r600_set_max_scissor(struct r600_context *rctx); 514void r600_bind_rs_state(struct pipe_context *ctx, void *state); 515void r600_delete_rs_state(struct pipe_context *ctx, void *state); 516void r600_sampler_view_destroy(struct pipe_context *ctx, 517 struct pipe_sampler_view *state); 518void r600_delete_state(struct pipe_context *ctx, void *state); 519void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 520void *r600_create_shader_state_ps(struct pipe_context *ctx, 521 const struct pipe_shader_state *state); 522void *r600_create_shader_state_vs(struct pipe_context *ctx, 523 const struct pipe_shader_state *state); 524void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 525void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 526void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 527void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 528void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 529void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 530 struct pipe_constant_buffer *cb); 531struct pipe_stream_output_target * 532r600_create_so_target(struct pipe_context *ctx, 533 struct pipe_resource *buffer, 534 unsigned buffer_offset, 535 unsigned buffer_size); 536void r600_so_target_destroy(struct pipe_context *ctx, 537 struct pipe_stream_output_target *target); 538void r600_set_so_targets(struct pipe_context *ctx, 539 unsigned num_targets, 540 struct pipe_stream_output_target **targets, 541 unsigned append_bitmask); 542void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 543 const struct pipe_stencil_ref *state); 544void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 545uint32_t r600_translate_stencil_op(int s_op); 546uint32_t r600_translate_fill(uint32_t func); 547unsigned r600_tex_wrap(unsigned wrap); 548unsigned r600_tex_filter(unsigned filter); 549unsigned r600_tex_mipfilter(unsigned filter); 550unsigned r600_tex_compare(unsigned compare); 551 552/* 553 * Helpers for building command buffers 554 */ 555 556#define PKT3_SET_CONFIG_REG 0x68 557#define PKT3_SET_CONTEXT_REG 0x69 558#define PKT3_SET_CTL_CONST 0x6F 559#define PKT3_SET_LOOP_CONST 0x6C 560 561#define R600_CONFIG_REG_OFFSET 0x08000 562#define R600_CONTEXT_REG_OFFSET 0x28000 563#define R600_CTL_CONST_OFFSET 0x3CFF0 564#define R600_LOOP_CONST_OFFSET 0X0003E200 565#define EG_LOOP_CONST_OFFSET 0x0003A200 566 567#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 568#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 569#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 570#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 571#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 572 573static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 574{ 575 cb->buf[cb->atom.num_dw++] = value; 576} 577 578static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 579{ 580 assert(reg < R600_CONTEXT_REG_OFFSET); 581 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 582 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 583 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 584} 585 586static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 587{ 588 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 589 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 590 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 591 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 592} 593 594static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 595{ 596 assert(reg >= R600_CTL_CONST_OFFSET); 597 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 598 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 599 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 600} 601 602static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 603{ 604 assert(reg >= R600_LOOP_CONST_OFFSET); 605 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 606 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 607 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 608} 609 610static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 611{ 612 assert(reg >= EG_LOOP_CONST_OFFSET); 613 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 614 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 615 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 616} 617 618static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 619{ 620 r600_store_config_reg_seq(cb, reg, 1); 621 r600_store_value(cb, value); 622} 623 624static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 625{ 626 r600_store_context_reg_seq(cb, reg, 1); 627 r600_store_value(cb, value); 628} 629 630static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 631{ 632 r600_store_ctl_const_seq(cb, reg, 1); 633 r600_store_value(cb, value); 634} 635 636static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 637{ 638 r600_store_loop_const_seq(cb, reg, 1); 639 r600_store_value(cb, value); 640} 641 642static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 643{ 644 eg_store_loop_const_seq(cb, reg, 1); 645 r600_store_value(cb, value); 646} 647 648void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 649void r600_release_command_buffer(struct r600_command_buffer *cb); 650 651/* 652 * Helpers for emitting state into a command stream directly. 653 */ 654 655static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 656 enum radeon_bo_usage usage) 657{ 658 assert(usage); 659 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 660} 661 662static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 663{ 664 cs->buf[cs->cdw++] = value; 665} 666 667static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 668{ 669 assert(reg < R600_CONTEXT_REG_OFFSET); 670 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 671 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 672 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 673} 674 675static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 676{ 677 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 678 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 679 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 680 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 681} 682 683static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 684{ 685 assert(reg >= R600_CTL_CONST_OFFSET); 686 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 687 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 688 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 689} 690 691static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 692{ 693 r600_write_config_reg_seq(cs, reg, 1); 694 r600_write_value(cs, value); 695} 696 697static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 698{ 699 r600_write_context_reg_seq(cs, reg, 1); 700 r600_write_value(cs, value); 701} 702 703static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 704{ 705 r600_write_ctl_const_seq(cs, reg, 1); 706 r600_write_value(cs, value); 707} 708 709/* 710 * common helpers 711 */ 712static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 713{ 714 return value * (1 << frac_bits); 715} 716#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 717 718static inline unsigned r600_tex_aniso_filter(unsigned filter) 719{ 720 if (filter <= 1) return 0; 721 if (filter <= 2) return 1; 722 if (filter <= 4) return 2; 723 if (filter <= 8) return 3; 724 /* else */ return 4; 725} 726 727/* 12.4 fixed-point */ 728static INLINE unsigned r600_pack_float_12p4(float x) 729{ 730 return x <= 0 ? 0 : 731 x >= 4096 ? 0xffff : x * 16; 732} 733 734static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 735{ 736 struct r600_screen *rscreen = (struct r600_screen*)screen; 737 struct r600_resource *rresource = (struct r600_resource*)resource; 738 739 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 740} 741 742#endif 743