r600_pipe.h revision 58c243905b0cfcbf1b0299a0f7f0ea90755e36cc
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29enum r600_pipe_state_id { 30 R600_PIPE_STATE_BLEND = 0, 31 R600_PIPE_STATE_BLEND_COLOR, 32 R600_PIPE_STATE_CONFIG, 33 R600_PIPE_STATE_CLIP, 34 R600_PIPE_STATE_SCISSOR, 35 R600_PIPE_STATE_VIEWPORT, 36 R600_PIPE_STATE_RASTERIZER, 37 R600_PIPE_STATE_VGT, 38 R600_PIPE_STATE_FRAMEBUFFER, 39 R600_PIPE_STATE_DSA, 40 R600_PIPE_STATE_STENCIL_REF, 41 R600_PIPE_STATE_PS_SHADER, 42 R600_PIPE_STATE_VS_SHADER, 43 R600_PIPE_STATE_CONSTANT, 44 R600_PIPE_STATE_SAMPLER, 45 R600_PIPE_STATE_RESOURCE, 46 R600_PIPE_NSTATES 47}; 48 49struct r600_screen { 50 struct pipe_screen screen; 51 struct radeon *radeon; 52}; 53 54struct r600_pipe_sampler_view { 55 struct pipe_sampler_view base; 56 struct r600_pipe_state state; 57}; 58 59struct r600_pipe_rasterizer { 60 struct r600_pipe_state rstate; 61 bool flatshade; 62 unsigned sprite_coord_enable; 63 float offset_units; 64 float offset_scale; 65}; 66 67struct r600_pipe_blend { 68 struct r600_pipe_state rstate; 69 unsigned cb_target_mask; 70}; 71 72struct r600_pipe_shader { 73 struct r600_shader shader; 74 struct r600_pipe_state rstate; 75 struct radeon_ws_bo *bo; 76}; 77 78struct r600_vertex_element 79{ 80 unsigned count; 81 unsigned refcount; 82 struct pipe_vertex_element elements[32]; 83}; 84 85struct r600_pipe_context { 86 struct pipe_context context; 87 struct r600_screen *screen; 88 struct radeon *radeon; 89 struct blitter_context *blitter; 90 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 91 struct r600_context ctx; 92 struct r600_vertex_element *vertex_elements; 93 struct pipe_framebuffer_state framebuffer; 94 struct pipe_index_buffer index_buffer; 95 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; 96 unsigned nvertex_buffer; 97 unsigned cb_target_mask; 98 /* for saving when using blitter */ 99 struct pipe_stencil_ref stencil_ref; 100 struct pipe_viewport_state viewport; 101 struct pipe_clip_state clip; 102 unsigned vs_nconst; 103 unsigned ps_nconst; 104 struct r600_pipe_state vs_const[256]; 105 struct r600_pipe_state ps_const[256]; 106 struct r600_pipe_state vs_resource[160]; 107 struct r600_pipe_state ps_resource[160]; 108 struct r600_pipe_state config; 109 struct r600_pipe_shader *ps_shader; 110 struct r600_pipe_shader *vs_shader; 111 struct r600_pipe_state vs_const_buffer; 112 struct r600_pipe_state ps_const_buffer; 113 struct r600_pipe_rasterizer *rasterizer; 114 /* shader information */ 115 unsigned sprite_coord_enable; 116 bool flatshade; 117 struct u_upload_mgr *upload_vb; 118 struct u_upload_mgr *upload_ib; 119 enum radeon_family family; 120 unsigned any_user_vbs; 121}; 122 123struct r600_drawl { 124 struct pipe_context *ctx; 125 unsigned mode; 126 unsigned min_index; 127 unsigned max_index; 128 unsigned index_bias; 129 unsigned start; 130 unsigned count; 131 unsigned index_size; 132 unsigned index_buffer_offset; 133 struct pipe_resource *index_buffer; 134}; 135 136uint32_t r600_translate_texformat(enum pipe_format format, 137 const unsigned char *swizzle_view, 138 uint32_t *word4_p, uint32_t *yuv_format_p); 139 140/* r600_state2.c */ 141int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader); 142int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens); 143int r600_upload_index_buffer2(struct r600_pipe_context *rctx, struct r600_drawl *draw); 144int r600_upload_user_buffers2(struct r600_pipe_context *rctx); 145void r600_translate_index_buffer2(struct r600_pipe_context *r600, 146 struct pipe_resource **index_buffer, 147 unsigned *index_size, 148 unsigned *start, unsigned count); 149 150/* evergreen_state.c */ 151void evergreen_init_state_functions2(struct r600_pipe_context *rctx); 152void evergreen_init_config2(struct r600_pipe_context *rctx); 153void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info); 154void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 155void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 156 157static INLINE u32 S_FIXED(float value, u32 frac_bits) 158{ 159 return value * (1 << frac_bits); 160} 161#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 162 163#endif 164