r600_pipe.h revision 6613605d79bc84043e74c7eefe8025c2c7c4978b 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 *      Jerome Glisse
25 */
26#ifndef R600_PIPE_H
27#define R600_PIPE_H
28
29enum r600_pipe_state_id {
30	R600_PIPE_STATE_BLEND = 0,
31	R600_PIPE_STATE_BLEND_COLOR,
32	R600_PIPE_STATE_CONFIG,
33	R600_PIPE_STATE_CLIP,
34	R600_PIPE_STATE_SCISSOR,
35	R600_PIPE_STATE_VIEWPORT,
36	R600_PIPE_STATE_RASTERIZER,
37	R600_PIPE_STATE_VGT,
38	R600_PIPE_STATE_FRAMEBUFFER,
39	R600_PIPE_STATE_DSA,
40	R600_PIPE_STATE_STENCIL_REF,
41	R600_PIPE_STATE_PS_SHADER,
42	R600_PIPE_STATE_VS_SHADER,
43	R600_PIPE_STATE_CONSTANT,
44	R600_PIPE_STATE_SAMPLER,
45	R600_PIPE_STATE_RESOURCE,
46	R600_PIPE_NSTATES
47};
48
49struct r600_screen {
50	struct pipe_screen		screen;
51	struct radeon			*radeon;
52};
53
54struct r600_pipe_sampler_view {
55	struct pipe_sampler_view	base;
56	struct r600_pipe_state		state;
57};
58
59struct r600_pipe_rasterizer {
60	struct r600_pipe_state		rstate;
61	bool				flatshade;
62	unsigned			sprite_coord_enable;
63};
64
65struct r600_pipe_blend {
66	struct r600_pipe_state		rstate;
67	unsigned			cb_target_mask;
68};
69
70struct r600_pipe_shader {
71	struct r600_shader		shader;
72	struct r600_pipe_state		rstate;
73	struct radeon_ws_bo		*bo;
74};
75
76struct r600_vertex_element
77{
78	unsigned			count;
79	unsigned			refcount;
80	struct pipe_vertex_element	elements[32];
81};
82
83struct r600_pipe_context {
84	struct pipe_context		context;
85	struct r600_screen		*screen;
86	struct radeon			*radeon;
87	struct blitter_context		*blitter;
88	struct r600_pipe_state		*states[R600_PIPE_NSTATES];
89	struct r600_context		ctx;
90	struct r600_vertex_element	*vertex_elements;
91	struct pipe_framebuffer_state	framebuffer;
92	struct pipe_index_buffer	index_buffer;
93	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
94	unsigned			nvertex_buffer;
95	unsigned			cb_target_mask;
96	/* for saving when using blitter */
97	struct pipe_stencil_ref		stencil_ref;
98	struct pipe_viewport_state	viewport;
99	struct pipe_clip_state		clip;
100	unsigned			vs_nconst;
101	unsigned			ps_nconst;
102	struct r600_pipe_state		vs_const[256];
103	struct r600_pipe_state		ps_const[256];
104	struct r600_pipe_state		vs_resource[160];
105	struct r600_pipe_state		ps_resource[160];
106	struct r600_pipe_state		config;
107	struct r600_pipe_shader 	*ps_shader;
108	struct r600_pipe_shader 	*vs_shader;
109	struct r600_pipe_state		vs_const_buffer;
110	struct r600_pipe_state		ps_const_buffer;
111	/* shader information */
112	unsigned			sprite_coord_enable;
113	bool				flatshade;
114	struct u_upload_mgr		*upload_vb;
115	struct u_upload_mgr		*upload_ib;
116	enum radeon_family		family;
117};
118
119struct r600_drawl {
120	struct pipe_context	*ctx;
121	unsigned		mode;
122	unsigned		min_index;
123	unsigned		max_index;
124	unsigned		index_bias;
125	unsigned		start;
126	unsigned		count;
127	unsigned		index_size;
128	unsigned		index_buffer_offset;
129	struct pipe_resource	*index_buffer;
130};
131
132uint32_t r600_translate_texformat(enum pipe_format format,
133				  const unsigned char *swizzle_view,
134				  uint32_t *word4_p, uint32_t *yuv_format_p);
135
136/* r600_state2.c */
137int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader);
138int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens);
139int r600_upload_index_buffer2(struct r600_pipe_context *rctx, struct r600_drawl *draw);
140int r600_upload_user_buffers2(struct r600_pipe_context *rctx);
141void r600_translate_index_buffer2(struct r600_pipe_context *r600,
142					struct pipe_resource **index_buffer,
143					unsigned *index_size,
144					unsigned *start, unsigned count);
145
146/* evergreen_state.c */
147void evergreen_init_state_functions2(struct r600_pipe_context *rctx);
148void evergreen_init_config2(struct r600_pipe_context *rctx);
149void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info);
150void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
151void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
152
153static INLINE u32 S_FIXED(float value, u32 frac_bits)
154{
155	return value * (1 << frac_bits);
156}
157#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
158
159#endif
160