r600_pipe.h revision 68bbfc1afe210d82acfb14a78b0fd8c436a8f78c
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_shader.h" 32#include "r600_resource.h" 33 34#define R600_MAX_CONST_BUFFERS 2 35#define R600_MAX_CONST_BUFFER_SIZE 4096 36 37#ifdef PIPE_ARCH_BIG_ENDIAN 38#define R600_BIG_ENDIAN 1 39#else 40#define R600_BIG_ENDIAN 0 41#endif 42 43enum r600_atom_flags { 44 /* When set, atoms are added at the beginning of the dirty list 45 * instead of the end. */ 46 EMIT_EARLY = (1 << 0) 47}; 48 49/* This encapsulates a state or an operation which can emitted into the GPU 50 * command stream. It's not limited to states only, it can be used for anything 51 * that wants to write commands into the CS (e.g. cache flushes). */ 52struct r600_atom { 53 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 54 55 unsigned num_dw; 56 enum r600_atom_flags flags; 57 bool dirty; 58 59 struct list_head head; 60}; 61 62/* This is an atom containing GPU commands that never change. 63 * This is supposed to be copied directly into the CS. */ 64struct r600_command_buffer { 65 struct r600_atom atom; 66 uint32_t *buf; 67 unsigned max_num_dw; 68}; 69 70struct r600_surface_sync_cmd { 71 struct r600_atom atom; 72 unsigned flush_flags; /* CP_COHER_CNTL */ 73}; 74 75struct r600_db_misc_state { 76 struct r600_atom atom; 77 bool occlusion_query_enabled; 78 bool flush_depthstencil_enabled; 79}; 80 81enum r600_pipe_state_id { 82 R600_PIPE_STATE_BLEND = 0, 83 R600_PIPE_STATE_BLEND_COLOR, 84 R600_PIPE_STATE_CONFIG, 85 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 86 R600_PIPE_STATE_CLIP, 87 R600_PIPE_STATE_SCISSOR, 88 R600_PIPE_STATE_VIEWPORT, 89 R600_PIPE_STATE_RASTERIZER, 90 R600_PIPE_STATE_VGT, 91 R600_PIPE_STATE_FRAMEBUFFER, 92 R600_PIPE_STATE_DSA, 93 R600_PIPE_STATE_STENCIL_REF, 94 R600_PIPE_STATE_PS_SHADER, 95 R600_PIPE_STATE_VS_SHADER, 96 R600_PIPE_STATE_CONSTANT, 97 R600_PIPE_STATE_SAMPLER, 98 R600_PIPE_STATE_RESOURCE, 99 R600_PIPE_STATE_POLYGON_OFFSET, 100 R600_PIPE_STATE_FETCH_SHADER, 101 R600_PIPE_NSTATES 102}; 103 104struct r600_pipe_fences { 105 struct r600_resource *bo; 106 unsigned *data; 107 unsigned next_index; 108 /* linked list of preallocated blocks */ 109 struct list_head blocks; 110 /* linked list of freed fences */ 111 struct list_head pool; 112 pipe_mutex mutex; 113}; 114 115struct r600_screen { 116 struct pipe_screen screen; 117 struct radeon_winsys *ws; 118 unsigned family; 119 enum chip_class chip_class; 120 struct radeon_info info; 121 struct r600_tiling_info tiling_info; 122 struct util_slab_mempool pool_buffers; 123 struct r600_pipe_fences fences; 124 125 unsigned num_contexts; 126 bool use_surface_alloc; 127 128 /* for thread-safe write accessing to num_contexts */ 129 pipe_mutex mutex_num_contexts; 130}; 131 132struct r600_pipe_sampler_view { 133 struct pipe_sampler_view base; 134 struct r600_pipe_resource_state state; 135}; 136 137struct r600_pipe_rasterizer { 138 struct r600_pipe_state rstate; 139 boolean flatshade; 140 boolean two_side; 141 unsigned sprite_coord_enable; 142 unsigned clip_plane_enable; 143 unsigned pa_sc_line_stipple; 144 unsigned pa_cl_clip_cntl; 145 float offset_units; 146 float offset_scale; 147 bool scissor_enable; 148}; 149 150struct r600_pipe_blend { 151 struct r600_pipe_state rstate; 152 unsigned cb_target_mask; 153 unsigned cb_color_control; 154}; 155 156struct r600_pipe_dsa { 157 struct r600_pipe_state rstate; 158 unsigned alpha_ref; 159 ubyte valuemask[2]; 160 ubyte writemask[2]; 161 bool is_flush; 162}; 163 164struct r600_vertex_element 165{ 166 unsigned count; 167 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 168 struct u_vbuf_elements *vmgr_elements; 169 struct r600_resource *fetch_shader; 170 unsigned fs_size; 171 struct r600_pipe_state rstate; 172}; 173 174struct r600_pipe_shader { 175 struct r600_shader shader; 176 struct r600_pipe_state rstate; 177 struct r600_resource *bo; 178 struct r600_resource *bo_fetch; 179 struct r600_vertex_element vertex_elements; 180 struct tgsi_token *tokens; 181 unsigned sprite_coord_enable; 182 unsigned flatshade; 183 unsigned pa_cl_vs_out_cntl; 184 struct pipe_stream_output_info so; 185}; 186 187struct r600_pipe_sampler_state { 188 struct r600_pipe_state rstate; 189 boolean seamless_cube_map; 190}; 191 192/* needed for blitter save */ 193#define NUM_TEX_UNITS 16 194 195struct r600_textures_info { 196 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 197 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 198 unsigned n_views; 199 unsigned n_samplers; 200 bool samplers_dirty; 201 bool is_array_sampler[NUM_TEX_UNITS]; 202}; 203 204struct r600_fence { 205 struct pipe_reference reference; 206 unsigned index; /* in the shared bo */ 207 struct r600_resource *sleep_bo; 208 struct list_head head; 209}; 210 211#define FENCE_BLOCK_SIZE 16 212 213struct r600_fence_block { 214 struct r600_fence fences[FENCE_BLOCK_SIZE]; 215 struct list_head head; 216}; 217 218#define R600_CONSTANT_ARRAY_SIZE 256 219#define R600_RESOURCE_ARRAY_SIZE 160 220 221struct r600_stencil_ref 222{ 223 ubyte ref_value[2]; 224 ubyte valuemask[2]; 225 ubyte writemask[2]; 226}; 227 228struct r600_constant_buffer 229{ 230 struct pipe_resource *buffer; 231 unsigned buffer_offset; 232 unsigned buffer_size; 233}; 234 235struct r600_constbuf_state 236{ 237 struct r600_atom atom; 238 struct r600_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 239 uint32_t enabled_mask; 240 uint32_t dirty_mask; 241}; 242 243struct r600_context { 244 struct pipe_context context; 245 struct blitter_context *blitter; 246 enum radeon_family family; 247 enum chip_class chip_class; 248 boolean has_vertex_cache; 249 unsigned r6xx_num_clause_temp_gprs; 250 void *custom_dsa_flush; 251 struct r600_screen *screen; 252 struct radeon_winsys *ws; 253 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 254 struct r600_vertex_element *vertex_elements; 255 struct pipe_framebuffer_state framebuffer; 256 unsigned cb_target_mask; 257 unsigned cb_color_control; 258 unsigned pa_sc_line_stipple; 259 unsigned pa_cl_clip_cntl; 260 /* for saving when using blitter */ 261 struct pipe_stencil_ref stencil_ref; 262 struct pipe_viewport_state viewport; 263 struct pipe_clip_state clip; 264 struct r600_pipe_shader *ps_shader; 265 struct r600_pipe_shader *vs_shader; 266 struct r600_pipe_rasterizer *rasterizer; 267 struct r600_pipe_state vgt; 268 struct r600_pipe_state spi; 269 struct pipe_query *current_render_cond; 270 unsigned current_render_cond_mode; 271 struct pipe_query *saved_render_cond; 272 unsigned saved_render_cond_mode; 273 /* shader information */ 274 boolean two_side; 275 unsigned sprite_coord_enable; 276 boolean export_16bpc; 277 unsigned alpha_ref; 278 boolean alpha_ref_dirty; 279 unsigned nr_cbufs; 280 struct r600_textures_info vs_samplers; 281 struct r600_textures_info ps_samplers; 282 283 struct u_vbuf *vbuf_mgr; 284 struct util_slab_mempool pool_transfers; 285 boolean have_depth_texture, have_depth_fb; 286 287 unsigned default_ps_gprs, default_vs_gprs; 288 289 /* States based on r600_atom. */ 290 struct list_head dirty_states; 291 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 292 struct r600_surface_sync_cmd surface_sync_cmd; 293 struct r600_atom r6xx_flush_and_inv_cmd; 294 struct r600_db_misc_state db_misc_state; 295 struct r600_atom vertex_buffer_state; 296 struct r600_constbuf_state vs_constbuf_state; 297 struct r600_constbuf_state ps_constbuf_state; 298 299 struct radeon_winsys_cs *cs; 300 301 struct r600_range *range; 302 unsigned nblocks; 303 struct r600_block **blocks; 304 struct list_head dirty; 305 struct list_head resource_dirty; 306 struct list_head enable_list; 307 unsigned pm4_dirty_cdwords; 308 unsigned ctx_pm4_ndwords; 309 310 /* The list of active queries. Only one query of each type can be active. */ 311 int num_occlusion_queries; 312 313 /* Manage queries in two separate groups: 314 * The timer ones and the others (streamout, occlusion). 315 * 316 * We do this because we should only suspend non-timer queries for u_blitter, 317 * and later if the non-timer queries are suspended, the context flush should 318 * only suspend and resume the timer queries. */ 319 struct list_head active_timer_queries; 320 unsigned num_cs_dw_timer_queries_suspend; 321 struct list_head active_nontimer_queries; 322 unsigned num_cs_dw_nontimer_queries_suspend; 323 324 unsigned num_cs_dw_streamout_end; 325 326 unsigned backend_mask; 327 unsigned max_db; /* for OQ */ 328 unsigned flags; 329 boolean predicate_drawing; 330 struct r600_range ps_resources; 331 struct r600_range vs_resources; 332 int num_ps_resources, num_vs_resources; 333 334 unsigned num_so_targets; 335 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 336 boolean streamout_start; 337 unsigned streamout_append_bitmask; 338 339 /* There is no scissor enable bit on r6xx, so we must use a workaround. 340 * These track the current scissor state. */ 341 bool scissor_enable; 342 struct pipe_scissor_state scissor_state; 343 344 /* With rasterizer discard, there doesn't have to be a pixel shader. 345 * In that case, we bind this one: */ 346 void *dummy_pixel_shader; 347 348 bool vertex_buffers_dirty; 349}; 350 351static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 352{ 353 atom->emit(rctx, atom); 354 atom->dirty = false; 355 if (atom->head.next && atom->head.prev) 356 LIST_DELINIT(&atom->head); 357} 358 359static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 360{ 361 if (!state->dirty) { 362 if (state->flags & EMIT_EARLY) { 363 LIST_ADD(&state->head, &rctx->dirty_states); 364 } else { 365 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 366 } 367 state->dirty = true; 368 } 369} 370 371/* evergreen_state.c */ 372void evergreen_init_state_functions(struct r600_context *rctx); 373void evergreen_init_atom_start_cs(struct r600_context *rctx); 374void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 375void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 376void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 377void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 378void evergreen_polygon_offset_update(struct r600_context *rctx); 379void evergreen_pipe_init_buffer_resource(struct r600_context *rctx, 380 struct r600_pipe_resource_state *rstate); 381void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx, 382 struct r600_pipe_resource_state *rstate, 383 struct r600_resource *rbuffer, 384 unsigned offset, unsigned stride, 385 enum radeon_bo_usage usage); 386boolean evergreen_is_format_supported(struct pipe_screen *screen, 387 enum pipe_format format, 388 enum pipe_texture_target target, 389 unsigned sample_count, 390 unsigned usage); 391 392/* r600_blit.c */ 393void r600_init_blit_functions(struct r600_context *rctx); 394void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 395void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 396void r600_flush_depth_textures(struct r600_context *rctx); 397 398/* r600_buffer.c */ 399bool r600_init_resource(struct r600_screen *rscreen, 400 struct r600_resource *res, 401 unsigned size, unsigned alignment, 402 unsigned bind, unsigned usage); 403struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 404 const struct pipe_resource *templ); 405struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 406 void *ptr, unsigned bytes, 407 unsigned bind); 408void r600_upload_index_buffer(struct r600_context *rctx, 409 struct pipe_index_buffer *ib, unsigned count); 410 411 412/* r600_pipe.c */ 413void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 414 unsigned flags); 415 416/* r600_query.c */ 417void r600_init_query_functions(struct r600_context *rctx); 418void r600_suspend_nontimer_queries(struct r600_context *ctx); 419void r600_resume_nontimer_queries(struct r600_context *ctx); 420void r600_suspend_timer_queries(struct r600_context *ctx); 421void r600_resume_timer_queries(struct r600_context *ctx); 422 423/* r600_resource.c */ 424void r600_init_context_resource_functions(struct r600_context *r600); 425 426/* r600_shader.c */ 427int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 428void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 429int r600_find_vs_semantic_index(struct r600_shader *vs, 430 struct r600_shader *ps, int id); 431 432/* r600_state.c */ 433void r600_set_scissor_state(struct r600_context *rctx, 434 const struct pipe_scissor_state *state); 435void r600_update_sampler_states(struct r600_context *rctx); 436void r600_init_state_functions(struct r600_context *rctx); 437void r600_init_atom_start_cs(struct r600_context *rctx); 438void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 439void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 440void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 441void *r600_create_db_flush_dsa(struct r600_context *rctx); 442void r600_polygon_offset_update(struct r600_context *rctx); 443void r600_pipe_init_buffer_resource(struct r600_context *rctx, 444 struct r600_pipe_resource_state *rstate); 445void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 446 struct r600_resource *rbuffer, 447 unsigned offset, unsigned stride, 448 enum radeon_bo_usage usage); 449void r600_adjust_gprs(struct r600_context *rctx); 450boolean r600_is_format_supported(struct pipe_screen *screen, 451 enum pipe_format format, 452 enum pipe_texture_target target, 453 unsigned sample_count, 454 unsigned usage); 455 456/* r600_texture.c */ 457void r600_init_screen_texture_functions(struct pipe_screen *screen); 458void r600_init_surface_functions(struct r600_context *r600); 459uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 460 const unsigned char *swizzle_view, 461 uint32_t *word4_p, uint32_t *yuv_format_p); 462unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 463 unsigned level, unsigned layer); 464 465/* r600_translate.c */ 466void r600_translate_index_buffer(struct r600_context *r600, 467 struct pipe_index_buffer *ib, 468 unsigned count); 469 470/* r600_state_common.c */ 471void r600_init_atom(struct r600_atom *atom, 472 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 473 unsigned num_dw, enum r600_atom_flags flags); 474void r600_init_common_atoms(struct r600_context *rctx); 475unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 476void r600_texture_barrier(struct pipe_context *ctx); 477void r600_set_index_buffer(struct pipe_context *ctx, 478 const struct pipe_index_buffer *ib); 479void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 480 const struct pipe_vertex_buffer *buffers); 481void *r600_create_vertex_elements(struct pipe_context *ctx, 482 unsigned count, 483 const struct pipe_vertex_element *elements); 484void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 485void r600_bind_blend_state(struct pipe_context *ctx, void *state); 486void r600_set_blend_color(struct pipe_context *ctx, 487 const struct pipe_blend_color *state); 488void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 489void r600_set_max_scissor(struct r600_context *rctx); 490void r600_bind_rs_state(struct pipe_context *ctx, void *state); 491void r600_delete_rs_state(struct pipe_context *ctx, void *state); 492void r600_sampler_view_destroy(struct pipe_context *ctx, 493 struct pipe_sampler_view *state); 494void r600_delete_state(struct pipe_context *ctx, void *state); 495void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 496void *r600_create_shader_state(struct pipe_context *ctx, 497 const struct pipe_shader_state *state); 498void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 499void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 500void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 501void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 502void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 503void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 504 struct pipe_resource *buffer); 505struct pipe_stream_output_target * 506r600_create_so_target(struct pipe_context *ctx, 507 struct pipe_resource *buffer, 508 unsigned buffer_offset, 509 unsigned buffer_size); 510void r600_so_target_destroy(struct pipe_context *ctx, 511 struct pipe_stream_output_target *target); 512void r600_set_so_targets(struct pipe_context *ctx, 513 unsigned num_targets, 514 struct pipe_stream_output_target **targets, 515 unsigned append_bitmask); 516void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 517 const struct pipe_stencil_ref *state); 518void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 519uint32_t r600_translate_stencil_op(int s_op); 520uint32_t r600_translate_fill(uint32_t func); 521unsigned r600_tex_wrap(unsigned wrap); 522unsigned r600_tex_filter(unsigned filter); 523unsigned r600_tex_mipfilter(unsigned filter); 524unsigned r600_tex_compare(unsigned compare); 525 526/* 527 * Helpers for building command buffers 528 */ 529 530#define PKT3_SET_CONFIG_REG 0x68 531#define PKT3_SET_CONTEXT_REG 0x69 532#define PKT3_SET_CTL_CONST 0x6F 533#define PKT3_SET_LOOP_CONST 0x6C 534 535#define R600_CONFIG_REG_OFFSET 0x08000 536#define R600_CONTEXT_REG_OFFSET 0x28000 537#define R600_CTL_CONST_OFFSET 0x3CFF0 538#define R600_LOOP_CONST_OFFSET 0X0003E200 539#define EG_LOOP_CONST_OFFSET 0x0003A200 540 541#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 542#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 543#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 544#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 545#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 546 547static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 548{ 549 cb->buf[cb->atom.num_dw++] = value; 550} 551 552static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 553{ 554 assert(reg < R600_CONTEXT_REG_OFFSET); 555 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 556 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 557 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 558} 559 560static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 561{ 562 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 563 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 564 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 565 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 566} 567 568static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 569{ 570 assert(reg >= R600_CTL_CONST_OFFSET); 571 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 572 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 573 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 574} 575 576static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 577{ 578 assert(reg >= R600_LOOP_CONST_OFFSET); 579 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 580 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 581 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 582} 583 584static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 585{ 586 assert(reg >= EG_LOOP_CONST_OFFSET); 587 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 588 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 589 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 590} 591 592static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 593{ 594 r600_store_config_reg_seq(cb, reg, 1); 595 r600_store_value(cb, value); 596} 597 598static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 599{ 600 r600_store_context_reg_seq(cb, reg, 1); 601 r600_store_value(cb, value); 602} 603 604static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 605{ 606 r600_store_ctl_const_seq(cb, reg, 1); 607 r600_store_value(cb, value); 608} 609 610static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 611{ 612 r600_store_loop_const_seq(cb, reg, 1); 613 r600_store_value(cb, value); 614} 615 616static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 617{ 618 eg_store_loop_const_seq(cb, reg, 1); 619 r600_store_value(cb, value); 620} 621 622void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 623void r600_release_command_buffer(struct r600_command_buffer *cb); 624 625/* 626 * Helpers for emitting state into a command stream directly. 627 */ 628 629static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 630 enum radeon_bo_usage usage) 631{ 632 assert(usage); 633 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 634} 635 636static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 637{ 638 cs->buf[cs->cdw++] = value; 639} 640 641static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 642{ 643 assert(reg < R600_CONTEXT_REG_OFFSET); 644 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 645 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 646 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 647} 648 649static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 650{ 651 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 652 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 653 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 654 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 655} 656 657static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 658{ 659 assert(reg >= R600_CTL_CONST_OFFSET); 660 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 661 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 662 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 663} 664 665static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 666{ 667 r600_write_config_reg_seq(cs, reg, 1); 668 r600_write_value(cs, value); 669} 670 671static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 672{ 673 r600_write_context_reg_seq(cs, reg, 1); 674 r600_write_value(cs, value); 675} 676 677static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 678{ 679 r600_write_ctl_const_seq(cs, reg, 1); 680 r600_write_value(cs, value); 681} 682 683/* 684 * common helpers 685 */ 686static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 687{ 688 return value * (1 << frac_bits); 689} 690#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 691 692static inline unsigned r600_tex_aniso_filter(unsigned filter) 693{ 694 if (filter <= 1) return 0; 695 if (filter <= 2) return 1; 696 if (filter <= 4) return 2; 697 if (filter <= 8) return 3; 698 /* else */ return 4; 699} 700 701/* 12.4 fixed-point */ 702static INLINE unsigned r600_pack_float_12p4(float x) 703{ 704 return x <= 0 ? 0 : 705 x >= 4096 ? 0xffff : x * 16; 706} 707 708static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 709{ 710 struct r600_screen *rscreen = (struct r600_screen*)screen; 711 struct r600_resource *rresource = (struct r600_resource*)resource; 712 713 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 714} 715 716#endif 717