r600_pipe.h revision 6e7756db14c362ede6fdc97454267a32b8eab1d4
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71}; 72 73struct r600_surface_sync_cmd { 74 struct r600_atom atom; 75 unsigned flush_flags; /* CP_COHER_CNTL */ 76}; 77 78struct r600_db_misc_state { 79 struct r600_atom atom; 80 bool occlusion_query_enabled; 81 bool flush_depthstencil_enabled; 82}; 83 84enum r600_pipe_state_id { 85 R600_PIPE_STATE_BLEND = 0, 86 R600_PIPE_STATE_BLEND_COLOR, 87 R600_PIPE_STATE_CONFIG, 88 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 89 R600_PIPE_STATE_CLIP, 90 R600_PIPE_STATE_SCISSOR, 91 R600_PIPE_STATE_VIEWPORT, 92 R600_PIPE_STATE_RASTERIZER, 93 R600_PIPE_STATE_VGT, 94 R600_PIPE_STATE_FRAMEBUFFER, 95 R600_PIPE_STATE_DSA, 96 R600_PIPE_STATE_STENCIL_REF, 97 R600_PIPE_STATE_PS_SHADER, 98 R600_PIPE_STATE_VS_SHADER, 99 R600_PIPE_STATE_CONSTANT, 100 R600_PIPE_STATE_SAMPLER, 101 R600_PIPE_STATE_RESOURCE, 102 R600_PIPE_STATE_POLYGON_OFFSET, 103 R600_PIPE_STATE_FETCH_SHADER, 104 R600_PIPE_STATE_SPI, 105 R600_PIPE_NSTATES 106}; 107 108struct compute_memory_pool; 109void compute_memory_pool_delete(struct compute_memory_pool* pool); 110struct compute_memory_pool* compute_memory_pool_new( 111 int64_t initial_size_in_dw, 112 struct r600_screen *rscreen); 113 114struct r600_pipe_fences { 115 struct r600_resource *bo; 116 unsigned *data; 117 unsigned next_index; 118 /* linked list of preallocated blocks */ 119 struct list_head blocks; 120 /* linked list of freed fences */ 121 struct list_head pool; 122 pipe_mutex mutex; 123}; 124 125struct r600_screen { 126 struct pipe_screen screen; 127 struct radeon_winsys *ws; 128 unsigned family; 129 enum chip_class chip_class; 130 struct radeon_info info; 131 bool has_streamout; 132 struct r600_tiling_info tiling_info; 133 struct r600_pipe_fences fences; 134 135 bool use_surface_alloc; 136 int glsl_feature_level; 137 138 /*for compute global memory binding, we allocate stuff here, instead of 139 * buffers. 140 * XXX: Not sure if this is the best place for global_pool. Also, 141 * it's not thread safe, so it won't work with multiple contexts. */ 142 struct compute_memory_pool *global_pool; 143}; 144 145struct r600_pipe_sampler_view { 146 struct pipe_sampler_view base; 147 struct r600_pipe_resource_state state; 148}; 149 150struct r600_pipe_rasterizer { 151 struct r600_pipe_state rstate; 152 boolean flatshade; 153 boolean two_side; 154 unsigned sprite_coord_enable; 155 unsigned clip_plane_enable; 156 unsigned pa_sc_line_stipple; 157 unsigned pa_cl_clip_cntl; 158 float offset_units; 159 float offset_scale; 160 bool scissor_enable; 161}; 162 163struct r600_pipe_blend { 164 struct r600_pipe_state rstate; 165 unsigned cb_target_mask; 166 unsigned cb_color_control; 167 bool dual_src_blend; 168}; 169 170struct r600_pipe_dsa { 171 struct r600_pipe_state rstate; 172 unsigned alpha_ref; 173 ubyte valuemask[2]; 174 ubyte writemask[2]; 175 bool is_flush; 176 unsigned sx_alpha_test_control; 177}; 178 179struct r600_vertex_element 180{ 181 unsigned count; 182 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 183 struct r600_resource *fetch_shader; 184 unsigned fs_size; 185 struct r600_pipe_state rstate; 186}; 187 188struct r600_pipe_shader { 189 struct r600_shader shader; 190 struct r600_pipe_state rstate; 191 struct r600_resource *bo; 192 struct r600_resource *bo_fetch; 193 struct r600_vertex_element vertex_elements; 194 struct tgsi_token *tokens; 195 unsigned sprite_coord_enable; 196 unsigned flatshade; 197 unsigned pa_cl_vs_out_cntl; 198 unsigned ps_cb_shader_mask; 199 struct pipe_stream_output_info so; 200}; 201 202struct r600_pipe_sampler_state { 203 struct r600_pipe_state rstate; 204 boolean seamless_cube_map; 205}; 206 207/* needed for blitter save */ 208#define NUM_TEX_UNITS 16 209 210struct r600_textures_info { 211 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 212 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 213 unsigned n_views; 214 unsigned n_samplers; 215 bool samplers_dirty; 216 bool is_array_sampler[NUM_TEX_UNITS]; 217}; 218 219struct r600_fence { 220 struct pipe_reference reference; 221 unsigned index; /* in the shared bo */ 222 struct r600_resource *sleep_bo; 223 struct list_head head; 224}; 225 226#define FENCE_BLOCK_SIZE 16 227 228struct r600_fence_block { 229 struct r600_fence fences[FENCE_BLOCK_SIZE]; 230 struct list_head head; 231}; 232 233#define R600_CONSTANT_ARRAY_SIZE 256 234#define R600_RESOURCE_ARRAY_SIZE 160 235 236struct r600_stencil_ref 237{ 238 ubyte ref_value[2]; 239 ubyte valuemask[2]; 240 ubyte writemask[2]; 241}; 242 243struct r600_constbuf_state 244{ 245 struct r600_atom atom; 246 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 247 uint32_t enabled_mask; 248 uint32_t dirty_mask; 249}; 250 251struct r600_context { 252 struct pipe_context context; 253 struct blitter_context *blitter; 254 enum radeon_family family; 255 enum chip_class chip_class; 256 boolean has_vertex_cache; 257 unsigned r6xx_num_clause_temp_gprs; 258 void *custom_dsa_flush; 259 struct r600_screen *screen; 260 struct radeon_winsys *ws; 261 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 262 struct r600_vertex_element *vertex_elements; 263 struct pipe_framebuffer_state framebuffer; 264 unsigned cb_target_mask; 265 unsigned fb_cb_shader_mask; 266 unsigned sx_alpha_test_control; 267 unsigned cb_shader_mask; 268 unsigned cb_color_control; 269 unsigned pa_sc_line_stipple; 270 unsigned pa_cl_clip_cntl; 271 /* for saving when using blitter */ 272 struct pipe_stencil_ref stencil_ref; 273 struct pipe_viewport_state viewport; 274 struct pipe_clip_state clip; 275 struct r600_pipe_shader *ps_shader; 276 struct r600_pipe_shader *vs_shader; 277 struct r600_pipe_compute *cs_shader; 278 struct r600_pipe_rasterizer *rasterizer; 279 struct r600_pipe_state vgt; 280 struct r600_pipe_state spi; 281 struct pipe_query *current_render_cond; 282 unsigned current_render_cond_mode; 283 struct pipe_query *saved_render_cond; 284 unsigned saved_render_cond_mode; 285 /* shader information */ 286 boolean two_side; 287 boolean spi_dirty; 288 unsigned sprite_coord_enable; 289 boolean flatshade; 290 boolean export_16bpc; 291 unsigned alpha_ref; 292 boolean alpha_ref_dirty; 293 unsigned nr_cbufs; 294 struct r600_textures_info vs_samplers; 295 struct r600_textures_info ps_samplers; 296 297 struct u_upload_mgr *uploader; 298 struct util_slab_mempool pool_transfers; 299 boolean have_depth_texture, have_depth_fb; 300 301 unsigned default_ps_gprs, default_vs_gprs; 302 303 /* States based on r600_atom. */ 304 struct list_head dirty_states; 305 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 306 struct r600_surface_sync_cmd surface_sync_cmd; 307 struct r600_atom r6xx_flush_and_inv_cmd; 308 struct r600_db_misc_state db_misc_state; 309 struct r600_atom vertex_buffer_state; 310 struct r600_constbuf_state vs_constbuf_state; 311 struct r600_constbuf_state ps_constbuf_state; 312 313 struct radeon_winsys_cs *cs; 314 315 struct r600_range *range; 316 unsigned nblocks; 317 struct r600_block **blocks; 318 struct list_head dirty; 319 struct list_head resource_dirty; 320 struct list_head enable_list; 321 unsigned pm4_dirty_cdwords; 322 unsigned ctx_pm4_ndwords; 323 324 /* The list of active queries. Only one query of each type can be active. */ 325 int num_occlusion_queries; 326 327 /* Manage queries in two separate groups: 328 * The timer ones and the others (streamout, occlusion). 329 * 330 * We do this because we should only suspend non-timer queries for u_blitter, 331 * and later if the non-timer queries are suspended, the context flush should 332 * only suspend and resume the timer queries. */ 333 struct list_head active_timer_queries; 334 unsigned num_cs_dw_timer_queries_suspend; 335 struct list_head active_nontimer_queries; 336 unsigned num_cs_dw_nontimer_queries_suspend; 337 338 unsigned num_cs_dw_streamout_end; 339 340 unsigned backend_mask; 341 unsigned max_db; /* for OQ */ 342 unsigned flags; 343 boolean predicate_drawing; 344 struct r600_range ps_resources; 345 struct r600_range vs_resources; 346 int num_ps_resources, num_vs_resources; 347 348 unsigned num_so_targets; 349 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 350 boolean streamout_start; 351 unsigned streamout_append_bitmask; 352 353 /* There is no scissor enable bit on r6xx, so we must use a workaround. 354 * These track the current scissor state. */ 355 bool scissor_enable; 356 struct pipe_scissor_state scissor_state; 357 358 /* With rasterizer discard, there doesn't have to be a pixel shader. 359 * In that case, we bind this one: */ 360 void *dummy_pixel_shader; 361 362 boolean dual_src_blend; 363 364 /* Vertex and index buffers. */ 365 bool vertex_buffers_dirty; 366 struct pipe_index_buffer index_buffer; 367 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS]; 368 unsigned nr_vertex_buffers; 369}; 370 371static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 372{ 373 atom->emit(rctx, atom); 374 atom->dirty = false; 375 if (atom->head.next && atom->head.prev) 376 LIST_DELINIT(&atom->head); 377} 378 379static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 380{ 381 if (!state->dirty) { 382 if (state->flags & EMIT_EARLY) { 383 LIST_ADD(&state->head, &rctx->dirty_states); 384 } else { 385 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 386 } 387 state->dirty = true; 388 } 389} 390 391/* evergreen_state.c */ 392void evergreen_init_state_functions(struct r600_context *rctx); 393void evergreen_init_atom_start_cs(struct r600_context *rctx); 394void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 395void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 396void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 397void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 398void evergreen_polygon_offset_update(struct r600_context *rctx); 399boolean evergreen_is_format_supported(struct pipe_screen *screen, 400 enum pipe_format format, 401 enum pipe_texture_target target, 402 unsigned sample_count, 403 unsigned usage); 404 405/* r600_blit.c */ 406void r600_init_blit_functions(struct r600_context *rctx); 407void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 408void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 409void r600_flush_depth_textures(struct r600_context *rctx); 410 411/* r600_buffer.c */ 412bool r600_init_resource(struct r600_screen *rscreen, 413 struct r600_resource *res, 414 unsigned size, unsigned alignment, 415 unsigned bind, unsigned usage); 416struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 417 const struct pipe_resource *templ); 418 419/* r600_pipe.c */ 420void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 421 unsigned flags); 422 423/* r600_query.c */ 424void r600_init_query_functions(struct r600_context *rctx); 425void r600_suspend_nontimer_queries(struct r600_context *ctx); 426void r600_resume_nontimer_queries(struct r600_context *ctx); 427void r600_suspend_timer_queries(struct r600_context *ctx); 428void r600_resume_timer_queries(struct r600_context *ctx); 429 430/* r600_resource.c */ 431void r600_init_context_resource_functions(struct r600_context *r600); 432 433/* r600_shader.c */ 434int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 435#ifdef HAVE_OPENCL 436int r600_compute_shader_create(struct pipe_context * ctx, 437 LLVMModuleRef mod, struct r600_bytecode * bytecode); 438#endif 439void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 440int r600_find_vs_semantic_index(struct r600_shader *vs, 441 struct r600_shader *ps, int id); 442 443/* r600_state.c */ 444void r600_set_scissor_state(struct r600_context *rctx, 445 const struct pipe_scissor_state *state); 446void r600_update_sampler_states(struct r600_context *rctx); 447void r600_init_state_functions(struct r600_context *rctx); 448void r600_init_atom_start_cs(struct r600_context *rctx); 449void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 450void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 451void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 452void *r600_create_db_flush_dsa(struct r600_context *rctx); 453void r600_polygon_offset_update(struct r600_context *rctx); 454void r600_adjust_gprs(struct r600_context *rctx); 455boolean r600_is_format_supported(struct pipe_screen *screen, 456 enum pipe_format format, 457 enum pipe_texture_target target, 458 unsigned sample_count, 459 unsigned usage); 460 461/* r600_texture.c */ 462void r600_init_screen_texture_functions(struct pipe_screen *screen); 463void r600_init_surface_functions(struct r600_context *r600); 464uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 465 const unsigned char *swizzle_view, 466 uint32_t *word4_p, uint32_t *yuv_format_p); 467unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 468 unsigned level, unsigned layer); 469 470/* r600_translate.c */ 471void r600_translate_index_buffer(struct r600_context *r600, 472 struct pipe_index_buffer *ib, 473 unsigned count); 474 475/* r600_state_common.c */ 476void r600_init_atom(struct r600_atom *atom, 477 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 478 unsigned num_dw, enum r600_atom_flags flags); 479void r600_init_common_atoms(struct r600_context *rctx); 480unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 481void r600_texture_barrier(struct pipe_context *ctx); 482void r600_set_index_buffer(struct pipe_context *ctx, 483 const struct pipe_index_buffer *ib); 484void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 485 const struct pipe_vertex_buffer *buffers); 486void *r600_create_vertex_elements(struct pipe_context *ctx, 487 unsigned count, 488 const struct pipe_vertex_element *elements); 489void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 490void r600_bind_blend_state(struct pipe_context *ctx, void *state); 491void r600_set_blend_color(struct pipe_context *ctx, 492 const struct pipe_blend_color *state); 493void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 494void r600_set_max_scissor(struct r600_context *rctx); 495void r600_bind_rs_state(struct pipe_context *ctx, void *state); 496void r600_delete_rs_state(struct pipe_context *ctx, void *state); 497void r600_sampler_view_destroy(struct pipe_context *ctx, 498 struct pipe_sampler_view *state); 499void r600_delete_state(struct pipe_context *ctx, void *state); 500void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 501void *r600_create_shader_state(struct pipe_context *ctx, 502 const struct pipe_shader_state *state); 503void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 504void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 505void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 506void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 507void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 508void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 509 struct pipe_constant_buffer *cb); 510struct pipe_stream_output_target * 511r600_create_so_target(struct pipe_context *ctx, 512 struct pipe_resource *buffer, 513 unsigned buffer_offset, 514 unsigned buffer_size); 515void r600_so_target_destroy(struct pipe_context *ctx, 516 struct pipe_stream_output_target *target); 517void r600_set_so_targets(struct pipe_context *ctx, 518 unsigned num_targets, 519 struct pipe_stream_output_target **targets, 520 unsigned append_bitmask); 521void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 522 const struct pipe_stencil_ref *state); 523void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 524uint32_t r600_translate_stencil_op(int s_op); 525uint32_t r600_translate_fill(uint32_t func); 526unsigned r600_tex_wrap(unsigned wrap); 527unsigned r600_tex_filter(unsigned filter); 528unsigned r600_tex_mipfilter(unsigned filter); 529unsigned r600_tex_compare(unsigned compare); 530 531/* 532 * Helpers for building command buffers 533 */ 534 535#define PKT3_SET_CONFIG_REG 0x68 536#define PKT3_SET_CONTEXT_REG 0x69 537#define PKT3_SET_CTL_CONST 0x6F 538#define PKT3_SET_LOOP_CONST 0x6C 539 540#define R600_CONFIG_REG_OFFSET 0x08000 541#define R600_CONTEXT_REG_OFFSET 0x28000 542#define R600_CTL_CONST_OFFSET 0x3CFF0 543#define R600_LOOP_CONST_OFFSET 0X0003E200 544#define EG_LOOP_CONST_OFFSET 0x0003A200 545 546#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 547#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 548#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 549#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 550#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 551 552static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 553{ 554 cb->buf[cb->atom.num_dw++] = value; 555} 556 557static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 558{ 559 assert(reg < R600_CONTEXT_REG_OFFSET); 560 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 561 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 562 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 563} 564 565static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 566{ 567 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 568 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 569 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 570 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 571} 572 573static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 574{ 575 assert(reg >= R600_CTL_CONST_OFFSET); 576 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 577 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 578 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 579} 580 581static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 582{ 583 assert(reg >= R600_LOOP_CONST_OFFSET); 584 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 585 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 586 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 587} 588 589static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 590{ 591 assert(reg >= EG_LOOP_CONST_OFFSET); 592 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 593 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 594 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 595} 596 597static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 598{ 599 r600_store_config_reg_seq(cb, reg, 1); 600 r600_store_value(cb, value); 601} 602 603static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 604{ 605 r600_store_context_reg_seq(cb, reg, 1); 606 r600_store_value(cb, value); 607} 608 609static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 610{ 611 r600_store_ctl_const_seq(cb, reg, 1); 612 r600_store_value(cb, value); 613} 614 615static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 616{ 617 r600_store_loop_const_seq(cb, reg, 1); 618 r600_store_value(cb, value); 619} 620 621static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 622{ 623 eg_store_loop_const_seq(cb, reg, 1); 624 r600_store_value(cb, value); 625} 626 627void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 628void r600_release_command_buffer(struct r600_command_buffer *cb); 629 630/* 631 * Helpers for emitting state into a command stream directly. 632 */ 633 634static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 635 enum radeon_bo_usage usage) 636{ 637 assert(usage); 638 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 639} 640 641static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 642{ 643 cs->buf[cs->cdw++] = value; 644} 645 646static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 647{ 648 assert(reg < R600_CONTEXT_REG_OFFSET); 649 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 650 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 651 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 652} 653 654static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 655{ 656 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 657 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 658 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 659 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 660} 661 662static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 663{ 664 assert(reg >= R600_CTL_CONST_OFFSET); 665 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 666 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 667 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 668} 669 670static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 671{ 672 r600_write_config_reg_seq(cs, reg, 1); 673 r600_write_value(cs, value); 674} 675 676static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 677{ 678 r600_write_context_reg_seq(cs, reg, 1); 679 r600_write_value(cs, value); 680} 681 682static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 683{ 684 r600_write_ctl_const_seq(cs, reg, 1); 685 r600_write_value(cs, value); 686} 687 688/* 689 * common helpers 690 */ 691static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 692{ 693 return value * (1 << frac_bits); 694} 695#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 696 697static inline unsigned r600_tex_aniso_filter(unsigned filter) 698{ 699 if (filter <= 1) return 0; 700 if (filter <= 2) return 1; 701 if (filter <= 4) return 2; 702 if (filter <= 8) return 3; 703 /* else */ return 4; 704} 705 706/* 12.4 fixed-point */ 707static INLINE unsigned r600_pack_float_12p4(float x) 708{ 709 return x <= 0 ? 0 : 710 x >= 4096 ? 0xffff : x * 16; 711} 712 713static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 714{ 715 struct r600_screen *rscreen = (struct r600_screen*)screen; 716 struct r600_resource *rresource = (struct r600_resource*)resource; 717 718 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 719} 720 721#endif 722