r600_pipe.h revision 74027a9ba250f07a77ee40e105c50c27e4fc3bc0
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "../../winsys/radeon/drm/radeon_winsys.h" 30 31#include "pipe/p_state.h" 32#include "pipe/p_screen.h" 33#include "pipe/p_context.h" 34#include "util/u_math.h" 35#include "util/u_slab.h" 36#include "util/u_vbuf.h" 37#include "r600.h" 38#include "r600_public.h" 39#include "r600_shader.h" 40#include "r600_resource.h" 41 42#define R600_MAX_CONST_BUFFERS 2 43#define R600_MAX_CONST_BUFFER_SIZE 4096 44 45#ifdef PIPE_ARCH_BIG_ENDIAN 46#define R600_BIG_ENDIAN 1 47#else 48#define R600_BIG_ENDIAN 0 49#endif 50 51enum r600_atom_flags { 52 /* When set, atoms are added at the beginning of the dirty list 53 * instead of the end. */ 54 EMIT_EARLY = (1 << 0) 55}; 56 57/* This encapsulates a state or an operation which can emitted into the GPU 58 * command stream. It's not limited to states only, it can be used for anything 59 * that wants to write commands into the CS (e.g. cache flushes). */ 60struct r600_atom { 61 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 62 63 unsigned num_dw; 64 enum r600_atom_flags flags; 65 bool dirty; 66 67 struct list_head head; 68}; 69 70struct r600_atom_surface_sync { 71 struct r600_atom atom; 72 unsigned flush_flags; /* CP_COHER_CNTL */ 73}; 74 75enum r600_pipe_state_id { 76 R600_PIPE_STATE_BLEND = 0, 77 R600_PIPE_STATE_BLEND_COLOR, 78 R600_PIPE_STATE_CONFIG, 79 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 80 R600_PIPE_STATE_CLIP, 81 R600_PIPE_STATE_SCISSOR, 82 R600_PIPE_STATE_VIEWPORT, 83 R600_PIPE_STATE_RASTERIZER, 84 R600_PIPE_STATE_VGT, 85 R600_PIPE_STATE_FRAMEBUFFER, 86 R600_PIPE_STATE_DSA, 87 R600_PIPE_STATE_STENCIL_REF, 88 R600_PIPE_STATE_PS_SHADER, 89 R600_PIPE_STATE_VS_SHADER, 90 R600_PIPE_STATE_CONSTANT, 91 R600_PIPE_STATE_SAMPLER, 92 R600_PIPE_STATE_RESOURCE, 93 R600_PIPE_STATE_POLYGON_OFFSET, 94 R600_PIPE_STATE_FETCH_SHADER, 95 R600_PIPE_NSTATES 96}; 97 98struct r600_pipe_fences { 99 struct r600_resource *bo; 100 unsigned *data; 101 unsigned next_index; 102 /* linked list of preallocated blocks */ 103 struct list_head blocks; 104 /* linked list of freed fences */ 105 struct list_head pool; 106 pipe_mutex mutex; 107}; 108 109struct r600_screen { 110 struct pipe_screen screen; 111 struct radeon_winsys *ws; 112 unsigned family; 113 enum chip_class chip_class; 114 struct radeon_info info; 115 struct r600_tiling_info tiling_info; 116 struct util_slab_mempool pool_buffers; 117 struct r600_pipe_fences fences; 118 119 unsigned num_contexts; 120 121 /* for thread-safe write accessing to num_contexts */ 122 pipe_mutex mutex_num_contexts; 123}; 124 125struct r600_pipe_sampler_view { 126 struct pipe_sampler_view base; 127 struct r600_pipe_resource_state state; 128}; 129 130struct r600_pipe_rasterizer { 131 struct r600_pipe_state rstate; 132 boolean flatshade; 133 boolean two_side; 134 unsigned sprite_coord_enable; 135 unsigned clip_plane_enable; 136 unsigned pa_sc_line_stipple; 137 unsigned pa_su_sc_mode_cntl; 138 unsigned pa_cl_clip_cntl; 139 float offset_units; 140 float offset_scale; 141}; 142 143struct r600_pipe_blend { 144 struct r600_pipe_state rstate; 145 unsigned cb_target_mask; 146 unsigned cb_color_control; 147}; 148 149struct r600_pipe_dsa { 150 struct r600_pipe_state rstate; 151 unsigned alpha_ref; 152 unsigned db_render_override; 153 unsigned db_render_control; 154 ubyte valuemask[2]; 155 ubyte writemask[2]; 156}; 157 158struct r600_vertex_element 159{ 160 unsigned count; 161 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 162 struct u_vbuf_elements *vmgr_elements; 163 struct r600_resource *fetch_shader; 164 unsigned fs_size; 165 struct r600_pipe_state rstate; 166 /* if offset is to big for fetch instructio we need to alterate 167 * offset of vertex buffer, record here the offset need to add 168 */ 169 unsigned vbuffer_need_offset; 170 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS]; 171}; 172 173struct r600_pipe_shader { 174 struct r600_shader shader; 175 struct r600_pipe_state rstate; 176 struct r600_resource *bo; 177 struct r600_resource *bo_fetch; 178 struct r600_vertex_element vertex_elements; 179 struct tgsi_token *tokens; 180 unsigned sprite_coord_enable; 181 unsigned flatshade; 182 unsigned pa_cl_vs_out_cntl; 183 struct pipe_stream_output_info so; 184}; 185 186struct r600_pipe_sampler_state { 187 struct r600_pipe_state rstate; 188 boolean seamless_cube_map; 189}; 190 191/* needed for blitter save */ 192#define NUM_TEX_UNITS 16 193 194struct r600_textures_info { 195 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 196 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 197 unsigned n_views; 198 unsigned n_samplers; 199 bool samplers_dirty; 200 bool is_array_sampler[NUM_TEX_UNITS]; 201}; 202 203struct r600_fence { 204 struct pipe_reference reference; 205 unsigned index; /* in the shared bo */ 206 struct list_head head; 207}; 208 209#define FENCE_BLOCK_SIZE 16 210 211struct r600_fence_block { 212 struct r600_fence fences[FENCE_BLOCK_SIZE]; 213 struct list_head head; 214}; 215 216#define R600_CONSTANT_ARRAY_SIZE 256 217#define R600_RESOURCE_ARRAY_SIZE 160 218 219struct r600_stencil_ref 220{ 221 ubyte ref_value[2]; 222 ubyte valuemask[2]; 223 ubyte writemask[2]; 224}; 225 226struct r600_context { 227 struct pipe_context context; 228 struct blitter_context *blitter; 229 enum radeon_family family; 230 enum chip_class chip_class; 231 unsigned r6xx_num_clause_temp_gprs; 232 void *custom_dsa_flush; 233 struct r600_screen *screen; 234 struct radeon_winsys *ws; 235 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 236 struct r600_vertex_element *vertex_elements; 237 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS]; 238 struct pipe_framebuffer_state framebuffer; 239 unsigned cb_target_mask; 240 unsigned cb_color_control; 241 unsigned pa_sc_line_stipple; 242 unsigned pa_su_sc_mode_cntl; 243 unsigned pa_cl_clip_cntl; 244 /* for saving when using blitter */ 245 struct pipe_stencil_ref stencil_ref; 246 struct pipe_viewport_state viewport; 247 struct pipe_clip_state clip; 248 struct r600_pipe_state config; 249 struct r600_pipe_shader *ps_shader; 250 struct r600_pipe_shader *vs_shader; 251 struct r600_pipe_state vs_const_buffer; 252 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 253 struct r600_pipe_state ps_const_buffer; 254 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 255 struct r600_pipe_rasterizer *rasterizer; 256 struct r600_pipe_state vgt; 257 struct r600_pipe_state spi; 258 struct pipe_query *current_render_cond; 259 unsigned current_render_cond_mode; 260 struct pipe_query *saved_render_cond; 261 unsigned saved_render_cond_mode; 262 /* shader information */ 263 boolean two_side; 264 unsigned sprite_coord_enable; 265 boolean export_16bpc; 266 unsigned alpha_ref; 267 boolean alpha_ref_dirty; 268 unsigned nr_cbufs; 269 struct r600_textures_info vs_samplers; 270 struct r600_textures_info ps_samplers; 271 272 struct u_vbuf *vbuf_mgr; 273 struct util_slab_mempool pool_transfers; 274 boolean have_depth_texture, have_depth_fb; 275 276 unsigned default_ps_gprs, default_vs_gprs; 277 278 /* States based on r600_state. */ 279 struct list_head dirty_states; 280 struct r600_atom_surface_sync atom_surface_sync; 281 struct r600_atom atom_r6xx_flush_and_inv; 282 283 /* Below are variables from the old r600_context. 284 */ 285 struct radeon_winsys_cs *cs; 286 287 struct r600_range *range; 288 unsigned nblocks; 289 struct r600_block **blocks; 290 struct list_head dirty; 291 struct list_head resource_dirty; 292 struct list_head enable_list; 293 unsigned pm4_dirty_cdwords; 294 unsigned ctx_pm4_ndwords; 295 unsigned init_dwords; 296 297 /* The list of active queries. Only one query of each type can be active. */ 298 struct list_head active_query_list; 299 unsigned num_cs_dw_queries_suspend; 300 unsigned num_cs_dw_streamout_end; 301 302 unsigned backend_mask; 303 unsigned max_db; /* for OQ */ 304 unsigned num_dest_buffers; 305 unsigned flags; 306 boolean predicate_drawing; 307 struct r600_range ps_resources; 308 struct r600_range vs_resources; 309 struct r600_range fs_resources; 310 int num_ps_resources, num_vs_resources, num_fs_resources; 311 312 unsigned num_so_targets; 313 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 314 boolean streamout_start; 315 unsigned streamout_append_bitmask; 316 unsigned *vs_so_stride_in_dw; 317}; 318 319static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 320{ 321 atom->emit(rctx, atom); 322 atom->dirty = false; 323 if (atom->head.next && atom->head.prev) 324 LIST_DELINIT(&atom->head); 325} 326 327static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 328{ 329 if (!state->dirty) { 330 if (state->flags & EMIT_EARLY) { 331 LIST_ADD(&state->head, &rctx->dirty_states); 332 } else { 333 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 334 } 335 state->dirty = true; 336 } 337} 338 339/* evergreen_state.c */ 340void evergreen_init_state_functions(struct r600_context *rctx); 341void evergreen_init_config(struct r600_context *rctx); 342void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 343void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 344void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 345void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 346void evergreen_polygon_offset_update(struct r600_context *rctx); 347void evergreen_pipe_init_buffer_resource(struct r600_context *rctx, 348 struct r600_pipe_resource_state *rstate); 349void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx, 350 struct r600_pipe_resource_state *rstate, 351 struct r600_resource *rbuffer, 352 unsigned offset, unsigned stride, 353 enum radeon_bo_usage usage); 354boolean evergreen_is_format_supported(struct pipe_screen *screen, 355 enum pipe_format format, 356 enum pipe_texture_target target, 357 unsigned sample_count, 358 unsigned usage); 359 360/* r600_blit.c */ 361void r600_init_blit_functions(struct r600_context *rctx); 362void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 363void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 364void r600_flush_depth_textures(struct r600_context *rctx); 365 366/* r600_buffer.c */ 367bool r600_init_resource(struct r600_screen *rscreen, 368 struct r600_resource *res, 369 unsigned size, unsigned alignment, 370 unsigned bind, unsigned usage); 371struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 372 const struct pipe_resource *templ); 373struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 374 void *ptr, unsigned bytes, 375 unsigned bind); 376void r600_upload_index_buffer(struct r600_context *rctx, 377 struct pipe_index_buffer *ib, unsigned count); 378 379 380/* r600_pipe.c */ 381void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 382 unsigned flags); 383 384/* r600_query.c */ 385void r600_init_query_functions(struct r600_context *rctx); 386 387/* r600_resource.c */ 388void r600_init_context_resource_functions(struct r600_context *r600); 389 390/* r600_shader.c */ 391int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 392void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 393int r600_find_vs_semantic_index(struct r600_shader *vs, 394 struct r600_shader *ps, int id); 395 396/* r600_state.c */ 397void r600_update_sampler_states(struct r600_context *rctx); 398void r600_init_state_functions(struct r600_context *rctx); 399void r600_init_config(struct r600_context *rctx); 400void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 401void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 402void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 403void *r600_create_db_flush_dsa(struct r600_context *rctx); 404void r600_polygon_offset_update(struct r600_context *rctx); 405void r600_pipe_init_buffer_resource(struct r600_context *rctx, 406 struct r600_pipe_resource_state *rstate); 407void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 408 struct r600_resource *rbuffer, 409 unsigned offset, unsigned stride, 410 enum radeon_bo_usage usage); 411void r600_adjust_gprs(struct r600_context *rctx); 412boolean r600_is_format_supported(struct pipe_screen *screen, 413 enum pipe_format format, 414 enum pipe_texture_target target, 415 unsigned sample_count, 416 unsigned usage); 417 418/* r600_texture.c */ 419void r600_init_screen_texture_functions(struct pipe_screen *screen); 420void r600_init_surface_functions(struct r600_context *r600); 421uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 422 const unsigned char *swizzle_view, 423 uint32_t *word4_p, uint32_t *yuv_format_p); 424unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 425 unsigned level, unsigned layer); 426 427/* r600_translate.c */ 428void r600_translate_index_buffer(struct r600_context *r600, 429 struct pipe_index_buffer *ib, 430 unsigned count); 431 432/* r600_state_common.c */ 433void r600_init_common_atoms(struct r600_context *rctx); 434unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 435void r600_texture_barrier(struct pipe_context *ctx); 436void r600_set_index_buffer(struct pipe_context *ctx, 437 const struct pipe_index_buffer *ib); 438void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 439 const struct pipe_vertex_buffer *buffers); 440void *r600_create_vertex_elements(struct pipe_context *ctx, 441 unsigned count, 442 const struct pipe_vertex_element *elements); 443void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 444void r600_bind_blend_state(struct pipe_context *ctx, void *state); 445void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 446void r600_bind_rs_state(struct pipe_context *ctx, void *state); 447void r600_delete_rs_state(struct pipe_context *ctx, void *state); 448void r600_sampler_view_destroy(struct pipe_context *ctx, 449 struct pipe_sampler_view *state); 450void r600_delete_state(struct pipe_context *ctx, void *state); 451void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 452void *r600_create_shader_state(struct pipe_context *ctx, 453 const struct pipe_shader_state *state); 454void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 455void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 456void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 457void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 458void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 459 struct pipe_resource *buffer); 460struct pipe_stream_output_target * 461r600_create_so_target(struct pipe_context *ctx, 462 struct pipe_resource *buffer, 463 unsigned buffer_offset, 464 unsigned buffer_size); 465void r600_so_target_destroy(struct pipe_context *ctx, 466 struct pipe_stream_output_target *target); 467void r600_set_so_targets(struct pipe_context *ctx, 468 unsigned num_targets, 469 struct pipe_stream_output_target **targets, 470 unsigned append_bitmask); 471void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 472 const struct pipe_stencil_ref *state); 473void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 474 475/* 476 * common helpers 477 */ 478static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 479{ 480 return value * (1 << frac_bits); 481} 482#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 483 484static inline unsigned r600_tex_aniso_filter(unsigned filter) 485{ 486 if (filter <= 1) return 0; 487 if (filter <= 2) return 1; 488 if (filter <= 4) return 2; 489 if (filter <= 8) return 3; 490 /* else */ return 4; 491} 492 493/* 12.4 fixed-point */ 494static INLINE unsigned r600_pack_float_12p4(float x) 495{ 496 return x <= 0 ? 0 : 497 x >= 4096 ? 0xffff : x * 16; 498} 499 500#endif 501