r600_pipe.h revision 78293b99b23268e6698f1267aaf40647c17d95a5
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "../../winsys/radeon/drm/radeon_winsys.h" 30 31#include "pipe/p_state.h" 32#include "pipe/p_screen.h" 33#include "pipe/p_context.h" 34#include "util/u_math.h" 35#include "util/u_slab.h" 36#include "util/u_vbuf.h" 37#include "r600.h" 38#include "r600_public.h" 39#include "r600_shader.h" 40#include "r600_resource.h" 41 42#define R600_MAX_CONST_BUFFERS 2 43#define R600_MAX_CONST_BUFFER_SIZE 4096 44 45#ifdef PIPE_ARCH_BIG_ENDIAN 46#define R600_BIG_ENDIAN 1 47#else 48#define R600_BIG_ENDIAN 0 49#endif 50 51enum r600_pipe_state_id { 52 R600_PIPE_STATE_BLEND = 0, 53 R600_PIPE_STATE_BLEND_COLOR, 54 R600_PIPE_STATE_CONFIG, 55 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 56 R600_PIPE_STATE_CLIP, 57 R600_PIPE_STATE_SCISSOR, 58 R600_PIPE_STATE_VIEWPORT, 59 R600_PIPE_STATE_RASTERIZER, 60 R600_PIPE_STATE_VGT, 61 R600_PIPE_STATE_FRAMEBUFFER, 62 R600_PIPE_STATE_DSA, 63 R600_PIPE_STATE_STENCIL_REF, 64 R600_PIPE_STATE_PS_SHADER, 65 R600_PIPE_STATE_VS_SHADER, 66 R600_PIPE_STATE_CONSTANT, 67 R600_PIPE_STATE_SAMPLER, 68 R600_PIPE_STATE_RESOURCE, 69 R600_PIPE_STATE_POLYGON_OFFSET, 70 R600_PIPE_STATE_FETCH_SHADER, 71 R600_PIPE_NSTATES 72}; 73 74struct r600_pipe_fences { 75 struct r600_resource *bo; 76 unsigned *data; 77 unsigned next_index; 78 /* linked list of preallocated blocks */ 79 struct list_head blocks; 80 /* linked list of freed fences */ 81 struct list_head pool; 82 pipe_mutex mutex; 83}; 84 85struct r600_screen { 86 struct pipe_screen screen; 87 struct radeon_winsys *ws; 88 unsigned family; 89 enum chip_class chip_class; 90 struct radeon_info info; 91 struct r600_tiling_info tiling_info; 92 struct util_slab_mempool pool_buffers; 93 struct r600_pipe_fences fences; 94 95 unsigned num_contexts; 96 97 /* for thread-safe write accessing to num_contexts */ 98 pipe_mutex mutex_num_contexts; 99}; 100 101struct r600_pipe_sampler_view { 102 struct pipe_sampler_view base; 103 struct r600_pipe_resource_state state; 104}; 105 106struct r600_pipe_rasterizer { 107 struct r600_pipe_state rstate; 108 boolean flatshade; 109 boolean two_side; 110 unsigned sprite_coord_enable; 111 unsigned clip_plane_enable; 112 unsigned pa_sc_line_stipple; 113 unsigned pa_su_sc_mode_cntl; 114 unsigned pa_cl_clip_cntl; 115 float offset_units; 116 float offset_scale; 117}; 118 119struct r600_pipe_blend { 120 struct r600_pipe_state rstate; 121 unsigned cb_target_mask; 122 unsigned cb_color_control; 123}; 124 125struct r600_pipe_dsa { 126 struct r600_pipe_state rstate; 127 unsigned alpha_ref; 128 unsigned db_render_override; 129 unsigned db_render_control; 130 ubyte valuemask[2]; 131 ubyte writemask[2]; 132}; 133 134struct r600_vertex_element 135{ 136 unsigned count; 137 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 138 struct u_vbuf_elements *vmgr_elements; 139 struct r600_resource *fetch_shader; 140 unsigned fs_size; 141 struct r600_pipe_state rstate; 142 /* if offset is to big for fetch instructio we need to alterate 143 * offset of vertex buffer, record here the offset need to add 144 */ 145 unsigned vbuffer_need_offset; 146 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS]; 147}; 148 149struct r600_pipe_shader { 150 struct r600_shader shader; 151 struct r600_pipe_state rstate; 152 struct r600_resource *bo; 153 struct r600_resource *bo_fetch; 154 struct r600_vertex_element vertex_elements; 155 struct tgsi_token *tokens; 156 unsigned sprite_coord_enable; 157 unsigned flatshade; 158 unsigned pa_cl_vs_out_cntl; 159 struct pipe_stream_output_info so; 160}; 161 162struct r600_pipe_sampler_state { 163 struct r600_pipe_state rstate; 164 boolean seamless_cube_map; 165}; 166 167/* needed for blitter save */ 168#define NUM_TEX_UNITS 16 169 170struct r600_textures_info { 171 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 172 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 173 unsigned n_views; 174 unsigned n_samplers; 175 bool samplers_dirty; 176 bool is_array_sampler[NUM_TEX_UNITS]; 177}; 178 179struct r600_fence { 180 struct pipe_reference reference; 181 unsigned index; /* in the shared bo */ 182 struct list_head head; 183}; 184 185#define FENCE_BLOCK_SIZE 16 186 187struct r600_fence_block { 188 struct r600_fence fences[FENCE_BLOCK_SIZE]; 189 struct list_head head; 190}; 191 192#define R600_CONSTANT_ARRAY_SIZE 256 193#define R600_RESOURCE_ARRAY_SIZE 160 194 195struct r600_stencil_ref 196{ 197 ubyte ref_value[2]; 198 ubyte valuemask[2]; 199 ubyte writemask[2]; 200}; 201 202struct r600_pipe_context { 203 struct pipe_context context; 204 struct blitter_context *blitter; 205 enum radeon_family family; 206 enum chip_class chip_class; 207 unsigned r6xx_num_clause_temp_gprs; 208 void *custom_dsa_flush; 209 struct r600_screen *screen; 210 struct radeon_winsys *ws; 211 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 212 struct r600_context ctx; 213 struct r600_vertex_element *vertex_elements; 214 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS]; 215 struct pipe_framebuffer_state framebuffer; 216 unsigned cb_target_mask; 217 unsigned cb_color_control; 218 unsigned pa_sc_line_stipple; 219 unsigned pa_su_sc_mode_cntl; 220 unsigned pa_cl_clip_cntl; 221 /* for saving when using blitter */ 222 struct pipe_stencil_ref stencil_ref; 223 struct pipe_viewport_state viewport; 224 struct pipe_clip_state clip; 225 struct r600_pipe_state config; 226 struct r600_pipe_shader *ps_shader; 227 struct r600_pipe_shader *vs_shader; 228 struct r600_pipe_state vs_const_buffer; 229 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 230 struct r600_pipe_state ps_const_buffer; 231 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 232 struct r600_pipe_rasterizer *rasterizer; 233 struct r600_pipe_state vgt; 234 struct r600_pipe_state spi; 235 struct pipe_query *current_render_cond; 236 unsigned current_render_cond_mode; 237 struct pipe_query *saved_render_cond; 238 unsigned saved_render_cond_mode; 239 /* shader information */ 240 boolean two_side; 241 unsigned sprite_coord_enable; 242 boolean export_16bpc; 243 unsigned alpha_ref; 244 boolean alpha_ref_dirty; 245 unsigned nr_cbufs; 246 struct r600_textures_info vs_samplers; 247 struct r600_textures_info ps_samplers; 248 249 struct u_vbuf *vbuf_mgr; 250 struct util_slab_mempool pool_transfers; 251 boolean have_depth_texture, have_depth_fb; 252 253 unsigned default_ps_gprs, default_vs_gprs; 254}; 255 256/* evergreen_state.c */ 257void evergreen_init_state_functions(struct r600_pipe_context *rctx); 258void evergreen_init_config(struct r600_pipe_context *rctx); 259void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 260void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 261void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 262void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx); 263void evergreen_polygon_offset_update(struct r600_pipe_context *rctx); 264void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx, 265 struct r600_pipe_resource_state *rstate); 266void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx, 267 struct r600_pipe_resource_state *rstate, 268 struct r600_resource *rbuffer, 269 unsigned offset, unsigned stride, 270 enum radeon_bo_usage usage); 271boolean evergreen_is_format_supported(struct pipe_screen *screen, 272 enum pipe_format format, 273 enum pipe_texture_target target, 274 unsigned sample_count, 275 unsigned usage); 276 277/* r600_blit.c */ 278void r600_init_blit_functions(struct r600_pipe_context *rctx); 279void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 280void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 281void r600_flush_depth_textures(struct r600_pipe_context *rctx); 282 283/* r600_buffer.c */ 284bool r600_init_resource(struct r600_screen *rscreen, 285 struct r600_resource *res, 286 unsigned size, unsigned alignment, 287 unsigned bind, unsigned usage); 288struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 289 const struct pipe_resource *templ); 290struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 291 void *ptr, unsigned bytes, 292 unsigned bind); 293void r600_upload_index_buffer(struct r600_pipe_context *rctx, 294 struct pipe_index_buffer *ib, unsigned count); 295 296 297/* r600_pipe.c */ 298void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 299 unsigned flags); 300 301/* r600_query.c */ 302void r600_init_query_functions(struct r600_pipe_context *rctx); 303 304/* r600_resource.c */ 305void r600_init_context_resource_functions(struct r600_pipe_context *r600); 306 307/* r600_shader.c */ 308int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 309void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 310int r600_find_vs_semantic_index(struct r600_shader *vs, 311 struct r600_shader *ps, int id); 312 313/* r600_state.c */ 314void r600_update_sampler_states(struct r600_pipe_context *rctx); 315void r600_init_state_functions(struct r600_pipe_context *rctx); 316void r600_init_config(struct r600_pipe_context *rctx); 317void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 318void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 319void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 320void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx); 321void r600_polygon_offset_update(struct r600_pipe_context *rctx); 322void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx, 323 struct r600_pipe_resource_state *rstate); 324void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 325 struct r600_resource *rbuffer, 326 unsigned offset, unsigned stride, 327 enum radeon_bo_usage usage); 328void r600_adjust_gprs(struct r600_pipe_context *rctx); 329boolean r600_is_format_supported(struct pipe_screen *screen, 330 enum pipe_format format, 331 enum pipe_texture_target target, 332 unsigned sample_count, 333 unsigned usage); 334 335/* r600_texture.c */ 336void r600_init_screen_texture_functions(struct pipe_screen *screen); 337void r600_init_surface_functions(struct r600_pipe_context *r600); 338uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 339 const unsigned char *swizzle_view, 340 uint32_t *word4_p, uint32_t *yuv_format_p); 341unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 342 unsigned level, unsigned layer); 343 344/* r600_translate.c */ 345void r600_translate_index_buffer(struct r600_pipe_context *r600, 346 struct pipe_index_buffer *ib, 347 unsigned count); 348 349/* r600_state_common.c */ 350void r600_set_index_buffer(struct pipe_context *ctx, 351 const struct pipe_index_buffer *ib); 352void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 353 const struct pipe_vertex_buffer *buffers); 354void *r600_create_vertex_elements(struct pipe_context *ctx, 355 unsigned count, 356 const struct pipe_vertex_element *elements); 357void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 358void r600_bind_blend_state(struct pipe_context *ctx, void *state); 359void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 360void r600_bind_rs_state(struct pipe_context *ctx, void *state); 361void r600_delete_rs_state(struct pipe_context *ctx, void *state); 362void r600_sampler_view_destroy(struct pipe_context *ctx, 363 struct pipe_sampler_view *state); 364void r600_delete_state(struct pipe_context *ctx, void *state); 365void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 366void *r600_create_shader_state(struct pipe_context *ctx, 367 const struct pipe_shader_state *state); 368void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 369void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 370void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 371void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 372void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 373 struct pipe_resource *buffer); 374struct pipe_stream_output_target * 375r600_create_so_target(struct pipe_context *ctx, 376 struct pipe_resource *buffer, 377 unsigned buffer_offset, 378 unsigned buffer_size); 379void r600_so_target_destroy(struct pipe_context *ctx, 380 struct pipe_stream_output_target *target); 381void r600_set_so_targets(struct pipe_context *ctx, 382 unsigned num_targets, 383 struct pipe_stream_output_target **targets, 384 unsigned append_bitmask); 385void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 386 const struct pipe_stencil_ref *state); 387void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 388 389/* 390 * common helpers 391 */ 392static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 393{ 394 return value * (1 << frac_bits); 395} 396#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 397 398static inline unsigned r600_tex_aniso_filter(unsigned filter) 399{ 400 if (filter <= 1) return 0; 401 if (filter <= 2) return 1; 402 if (filter <= 4) return 2; 403 if (filter <= 8) return 3; 404 /* else */ return 4; 405} 406 407/* 12.4 fixed-point */ 408static INLINE unsigned r600_pack_float_12p4(float x) 409{ 410 return x <= 0 ? 0 : 411 x >= 4096 ? 0xffff : x * 16; 412} 413 414#endif 415