r600_pipe.h revision 84b4b2a8aacf6655d3f2a9f03dec3913a00aabdb
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "../../winsys/radeon/drm/radeon_winsys.h" 30 31#include "pipe/p_state.h" 32#include "pipe/p_screen.h" 33#include "pipe/p_context.h" 34#include "util/u_math.h" 35#include "util/u_slab.h" 36#include "util/u_vbuf.h" 37#include "r600.h" 38#include "r600_public.h" 39#include "r600_shader.h" 40#include "r600_resource.h" 41 42#define R600_MAX_CONST_BUFFERS 2 43#define R600_MAX_CONST_BUFFER_SIZE 4096 44 45#ifdef PIPE_ARCH_BIG_ENDIAN 46#define R600_BIG_ENDIAN 1 47#else 48#define R600_BIG_ENDIAN 0 49#endif 50 51enum r600_pipe_state_id { 52 R600_PIPE_STATE_BLEND = 0, 53 R600_PIPE_STATE_BLEND_COLOR, 54 R600_PIPE_STATE_CONFIG, 55 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 56 R600_PIPE_STATE_CLIP, 57 R600_PIPE_STATE_SCISSOR, 58 R600_PIPE_STATE_VIEWPORT, 59 R600_PIPE_STATE_RASTERIZER, 60 R600_PIPE_STATE_VGT, 61 R600_PIPE_STATE_FRAMEBUFFER, 62 R600_PIPE_STATE_DSA, 63 R600_PIPE_STATE_STENCIL_REF, 64 R600_PIPE_STATE_PS_SHADER, 65 R600_PIPE_STATE_VS_SHADER, 66 R600_PIPE_STATE_CONSTANT, 67 R600_PIPE_STATE_SAMPLER, 68 R600_PIPE_STATE_RESOURCE, 69 R600_PIPE_STATE_POLYGON_OFFSET, 70 R600_PIPE_STATE_FETCH_SHADER, 71 R600_PIPE_NSTATES 72}; 73 74struct r600_pipe_fences { 75 struct r600_resource *bo; 76 unsigned *data; 77 unsigned next_index; 78 /* linked list of preallocated blocks */ 79 struct list_head blocks; 80 /* linked list of freed fences */ 81 struct list_head pool; 82 pipe_mutex mutex; 83}; 84 85struct r600_screen { 86 struct pipe_screen screen; 87 struct radeon_winsys *ws; 88 unsigned family; 89 enum chip_class chip_class; 90 struct radeon_info info; 91 struct r600_tiling_info tiling_info; 92 struct util_slab_mempool pool_buffers; 93 struct r600_pipe_fences fences; 94 95 unsigned num_contexts; 96 97 /* for thread-safe write accessing to num_contexts */ 98 pipe_mutex mutex_num_contexts; 99}; 100 101struct r600_pipe_sampler_view { 102 struct pipe_sampler_view base; 103 struct r600_pipe_resource_state state; 104}; 105 106struct r600_pipe_rasterizer { 107 struct r600_pipe_state rstate; 108 boolean flatshade; 109 boolean two_side; 110 unsigned sprite_coord_enable; 111 unsigned clip_plane_enable; 112 float offset_units; 113 float offset_scale; 114}; 115 116struct r600_pipe_blend { 117 struct r600_pipe_state rstate; 118 unsigned cb_target_mask; 119 unsigned cb_color_control; 120}; 121 122struct r600_pipe_dsa { 123 struct r600_pipe_state rstate; 124 unsigned alpha_ref; 125 ubyte valuemask[2]; 126 ubyte writemask[2]; 127}; 128 129struct r600_vertex_element 130{ 131 unsigned count; 132 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 133 struct u_vbuf_elements *vmgr_elements; 134 struct r600_resource *fetch_shader; 135 unsigned fs_size; 136 struct r600_pipe_state rstate; 137 /* if offset is to big for fetch instructio we need to alterate 138 * offset of vertex buffer, record here the offset need to add 139 */ 140 unsigned vbuffer_need_offset; 141 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS]; 142}; 143 144struct r600_pipe_shader { 145 struct r600_shader shader; 146 struct r600_pipe_state rstate; 147 struct r600_resource *bo; 148 struct r600_resource *bo_fetch; 149 struct r600_vertex_element vertex_elements; 150 struct tgsi_token *tokens; 151 unsigned sprite_coord_enable; 152 unsigned flatshade; 153 struct pipe_stream_output_info so; 154}; 155 156struct r600_pipe_sampler_state { 157 struct r600_pipe_state rstate; 158 boolean seamless_cube_map; 159}; 160 161/* needed for blitter save */ 162#define NUM_TEX_UNITS 16 163 164struct r600_textures_info { 165 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 166 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 167 unsigned n_views; 168 unsigned n_samplers; 169 bool samplers_dirty; 170 bool is_array_sampler[NUM_TEX_UNITS]; 171}; 172 173struct r600_fence { 174 struct pipe_reference reference; 175 unsigned index; /* in the shared bo */ 176 struct list_head head; 177}; 178 179#define FENCE_BLOCK_SIZE 16 180 181struct r600_fence_block { 182 struct r600_fence fences[FENCE_BLOCK_SIZE]; 183 struct list_head head; 184}; 185 186#define R600_CONSTANT_ARRAY_SIZE 256 187#define R600_RESOURCE_ARRAY_SIZE 160 188 189struct r600_stencil_ref 190{ 191 ubyte ref_value[2]; 192 ubyte valuemask[2]; 193 ubyte writemask[2]; 194}; 195 196struct r600_pipe_context { 197 struct pipe_context context; 198 struct blitter_context *blitter; 199 enum radeon_family family; 200 enum chip_class chip_class; 201 unsigned r6xx_num_clause_temp_gprs; 202 void *custom_dsa_flush; 203 struct r600_screen *screen; 204 struct radeon_winsys *ws; 205 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 206 struct r600_context ctx; 207 struct r600_vertex_element *vertex_elements; 208 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS]; 209 struct pipe_framebuffer_state framebuffer; 210 unsigned cb_target_mask; 211 unsigned cb_color_control; 212 /* for saving when using blitter */ 213 struct pipe_stencil_ref stencil_ref; 214 struct pipe_viewport_state viewport; 215 struct pipe_clip_state clip; 216 struct r600_pipe_state config; 217 struct r600_pipe_shader *ps_shader; 218 struct r600_pipe_shader *vs_shader; 219 struct r600_pipe_state vs_const_buffer; 220 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 221 struct r600_pipe_state ps_const_buffer; 222 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 223 struct r600_pipe_rasterizer *rasterizer; 224 struct r600_pipe_state vgt; 225 struct r600_pipe_state spi; 226 struct pipe_query *current_render_cond; 227 unsigned current_render_cond_mode; 228 struct pipe_query *saved_render_cond; 229 unsigned saved_render_cond_mode; 230 /* shader information */ 231 boolean two_side; 232 unsigned user_clip_plane_enable; 233 unsigned clip_dist_enable; 234 unsigned sprite_coord_enable; 235 boolean export_16bpc; 236 unsigned alpha_ref; 237 boolean alpha_ref_dirty; 238 unsigned nr_cbufs; 239 struct r600_textures_info vs_samplers; 240 struct r600_textures_info ps_samplers; 241 242 struct u_vbuf *vbuf_mgr; 243 struct util_slab_mempool pool_transfers; 244 boolean have_depth_texture, have_depth_fb; 245 246 unsigned default_ps_gprs, default_vs_gprs; 247}; 248 249/* evergreen_state.c */ 250void evergreen_init_state_functions(struct r600_pipe_context *rctx); 251void evergreen_init_config(struct r600_pipe_context *rctx); 252void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 253void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 254void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 255void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx); 256void evergreen_polygon_offset_update(struct r600_pipe_context *rctx); 257void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx, 258 struct r600_pipe_resource_state *rstate); 259void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx, 260 struct r600_pipe_resource_state *rstate, 261 struct r600_resource *rbuffer, 262 unsigned offset, unsigned stride, 263 enum radeon_bo_usage usage); 264boolean evergreen_is_format_supported(struct pipe_screen *screen, 265 enum pipe_format format, 266 enum pipe_texture_target target, 267 unsigned sample_count, 268 unsigned usage); 269 270/* r600_blit.c */ 271void r600_init_blit_functions(struct r600_pipe_context *rctx); 272void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 273void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 274void r600_flush_depth_textures(struct r600_pipe_context *rctx); 275 276/* r600_buffer.c */ 277bool r600_init_resource(struct r600_screen *rscreen, 278 struct r600_resource *res, 279 unsigned size, unsigned alignment, 280 unsigned bind, unsigned usage); 281struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 282 const struct pipe_resource *templ); 283struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 284 void *ptr, unsigned bytes, 285 unsigned bind); 286void r600_upload_index_buffer(struct r600_pipe_context *rctx, 287 struct pipe_index_buffer *ib, unsigned count); 288 289 290/* r600_pipe.c */ 291void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 292 unsigned flags); 293 294/* r600_query.c */ 295void r600_init_query_functions(struct r600_pipe_context *rctx); 296 297/* r600_resource.c */ 298void r600_init_context_resource_functions(struct r600_pipe_context *r600); 299 300/* r600_shader.c */ 301int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 302void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 303int r600_find_vs_semantic_index(struct r600_shader *vs, 304 struct r600_shader *ps, int id); 305 306/* r600_state.c */ 307void r600_update_sampler_states(struct r600_pipe_context *rctx); 308void r600_init_state_functions(struct r600_pipe_context *rctx); 309void r600_init_config(struct r600_pipe_context *rctx); 310void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 311void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 312void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 313void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx); 314void r600_polygon_offset_update(struct r600_pipe_context *rctx); 315void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx, 316 struct r600_pipe_resource_state *rstate); 317void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 318 struct r600_resource *rbuffer, 319 unsigned offset, unsigned stride, 320 enum radeon_bo_usage usage); 321void r600_adjust_gprs(struct r600_pipe_context *rctx); 322boolean r600_is_format_supported(struct pipe_screen *screen, 323 enum pipe_format format, 324 enum pipe_texture_target target, 325 unsigned sample_count, 326 unsigned usage); 327 328/* r600_texture.c */ 329void r600_init_screen_texture_functions(struct pipe_screen *screen); 330void r600_init_surface_functions(struct r600_pipe_context *r600); 331uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 332 const unsigned char *swizzle_view, 333 uint32_t *word4_p, uint32_t *yuv_format_p); 334unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 335 unsigned level, unsigned layer); 336 337/* r600_translate.c */ 338void r600_translate_index_buffer(struct r600_pipe_context *r600, 339 struct pipe_index_buffer *ib, 340 unsigned count); 341 342/* r600_state_common.c */ 343void r600_set_index_buffer(struct pipe_context *ctx, 344 const struct pipe_index_buffer *ib); 345void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 346 const struct pipe_vertex_buffer *buffers); 347void *r600_create_vertex_elements(struct pipe_context *ctx, 348 unsigned count, 349 const struct pipe_vertex_element *elements); 350void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 351void r600_bind_blend_state(struct pipe_context *ctx, void *state); 352void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 353void r600_bind_rs_state(struct pipe_context *ctx, void *state); 354void r600_delete_rs_state(struct pipe_context *ctx, void *state); 355void r600_sampler_view_destroy(struct pipe_context *ctx, 356 struct pipe_sampler_view *state); 357void r600_delete_state(struct pipe_context *ctx, void *state); 358void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 359void *r600_create_shader_state(struct pipe_context *ctx, 360 const struct pipe_shader_state *state); 361void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 362void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 363void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 364void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 365void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 366 struct pipe_resource *buffer); 367struct pipe_stream_output_target * 368r600_create_so_target(struct pipe_context *ctx, 369 struct pipe_resource *buffer, 370 unsigned buffer_offset, 371 unsigned buffer_size); 372void r600_so_target_destroy(struct pipe_context *ctx, 373 struct pipe_stream_output_target *target); 374void r600_set_so_targets(struct pipe_context *ctx, 375 unsigned num_targets, 376 struct pipe_stream_output_target **targets, 377 unsigned append_bitmask); 378void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 379 const struct pipe_stencil_ref *state); 380void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 381 382/* 383 * common helpers 384 */ 385static INLINE u32 S_FIXED(float value, u32 frac_bits) 386{ 387 return value * (1 << frac_bits); 388} 389#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 390 391static inline unsigned r600_tex_aniso_filter(unsigned filter) 392{ 393 if (filter <= 1) return 0; 394 if (filter <= 2) return 1; 395 if (filter <= 4) return 2; 396 if (filter <= 8) return 3; 397 /* else */ return 4; 398} 399 400/* 12.4 fixed-point */ 401static INLINE unsigned r600_pack_float_12p4(float x) 402{ 403 return x <= 0 ? 0 : 404 x >= 4096 ? 0xffff : x * 16; 405} 406 407#endif 408