r600_pipe.h revision b1b969f670c50a15110fd41527ccbc7e885e1cdd
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "../../winsys/radeon/drm/radeon_winsys.h" 30 31#include "pipe/p_state.h" 32#include "pipe/p_screen.h" 33#include "pipe/p_context.h" 34#include "util/u_math.h" 35#include "util/u_slab.h" 36#include "util/u_vbuf.h" 37#include "r600.h" 38#include "r600_public.h" 39#include "r600_shader.h" 40#include "r600_resource.h" 41 42#define R600_MAX_CONST_BUFFERS 2 43#define R600_MAX_CONST_BUFFER_SIZE 4096 44 45#ifdef PIPE_ARCH_BIG_ENDIAN 46#define R600_BIG_ENDIAN 1 47#else 48#define R600_BIG_ENDIAN 0 49#endif 50 51enum r600_pipe_state_id { 52 R600_PIPE_STATE_BLEND = 0, 53 R600_PIPE_STATE_BLEND_COLOR, 54 R600_PIPE_STATE_CONFIG, 55 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 56 R600_PIPE_STATE_CLIP, 57 R600_PIPE_STATE_SCISSOR, 58 R600_PIPE_STATE_VIEWPORT, 59 R600_PIPE_STATE_RASTERIZER, 60 R600_PIPE_STATE_VGT, 61 R600_PIPE_STATE_FRAMEBUFFER, 62 R600_PIPE_STATE_DSA, 63 R600_PIPE_STATE_STENCIL_REF, 64 R600_PIPE_STATE_PS_SHADER, 65 R600_PIPE_STATE_VS_SHADER, 66 R600_PIPE_STATE_CONSTANT, 67 R600_PIPE_STATE_SAMPLER, 68 R600_PIPE_STATE_RESOURCE, 69 R600_PIPE_STATE_POLYGON_OFFSET, 70 R600_PIPE_STATE_FETCH_SHADER, 71 R600_PIPE_NSTATES 72}; 73 74struct r600_pipe_fences { 75 struct r600_resource *bo; 76 unsigned *data; 77 unsigned next_index; 78 /* linked list of preallocated blocks */ 79 struct list_head blocks; 80 /* linked list of freed fences */ 81 struct list_head pool; 82 pipe_mutex mutex; 83}; 84 85struct r600_screen { 86 struct pipe_screen screen; 87 struct radeon_winsys *ws; 88 unsigned family; 89 enum chip_class chip_class; 90 struct radeon_info info; 91 struct r600_tiling_info tiling_info; 92 struct util_slab_mempool pool_buffers; 93 struct r600_pipe_fences fences; 94 95 unsigned num_contexts; 96 97 /* for thread-safe write accessing to num_contexts */ 98 pipe_mutex mutex_num_contexts; 99}; 100 101struct r600_pipe_sampler_view { 102 struct pipe_sampler_view base; 103 struct r600_pipe_resource_state state; 104}; 105 106struct r600_pipe_rasterizer { 107 struct r600_pipe_state rstate; 108 boolean flatshade; 109 boolean two_side; 110 unsigned sprite_coord_enable; 111 unsigned clip_plane_enable; 112 unsigned pa_sc_line_stipple; 113 unsigned pa_su_sc_mode_cntl; 114 unsigned pa_cl_clip_cntl; 115 float offset_units; 116 float offset_scale; 117}; 118 119struct r600_pipe_blend { 120 struct r600_pipe_state rstate; 121 unsigned cb_target_mask; 122 unsigned cb_color_control; 123}; 124 125struct r600_pipe_dsa { 126 struct r600_pipe_state rstate; 127 unsigned alpha_ref; 128 unsigned db_render_override; 129 ubyte valuemask[2]; 130 ubyte writemask[2]; 131}; 132 133struct r600_vertex_element 134{ 135 unsigned count; 136 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 137 struct u_vbuf_elements *vmgr_elements; 138 struct r600_resource *fetch_shader; 139 unsigned fs_size; 140 struct r600_pipe_state rstate; 141 /* if offset is to big for fetch instructio we need to alterate 142 * offset of vertex buffer, record here the offset need to add 143 */ 144 unsigned vbuffer_need_offset; 145 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS]; 146}; 147 148struct r600_pipe_shader { 149 struct r600_shader shader; 150 struct r600_pipe_state rstate; 151 struct r600_resource *bo; 152 struct r600_resource *bo_fetch; 153 struct r600_vertex_element vertex_elements; 154 struct tgsi_token *tokens; 155 unsigned sprite_coord_enable; 156 unsigned flatshade; 157 unsigned pa_cl_vs_out_cntl; 158 struct pipe_stream_output_info so; 159}; 160 161struct r600_pipe_sampler_state { 162 struct r600_pipe_state rstate; 163 boolean seamless_cube_map; 164}; 165 166/* needed for blitter save */ 167#define NUM_TEX_UNITS 16 168 169struct r600_textures_info { 170 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 171 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 172 unsigned n_views; 173 unsigned n_samplers; 174 bool samplers_dirty; 175 bool is_array_sampler[NUM_TEX_UNITS]; 176}; 177 178struct r600_fence { 179 struct pipe_reference reference; 180 unsigned index; /* in the shared bo */ 181 struct list_head head; 182}; 183 184#define FENCE_BLOCK_SIZE 16 185 186struct r600_fence_block { 187 struct r600_fence fences[FENCE_BLOCK_SIZE]; 188 struct list_head head; 189}; 190 191#define R600_CONSTANT_ARRAY_SIZE 256 192#define R600_RESOURCE_ARRAY_SIZE 160 193 194struct r600_stencil_ref 195{ 196 ubyte ref_value[2]; 197 ubyte valuemask[2]; 198 ubyte writemask[2]; 199}; 200 201struct r600_pipe_context { 202 struct pipe_context context; 203 struct blitter_context *blitter; 204 enum radeon_family family; 205 enum chip_class chip_class; 206 unsigned r6xx_num_clause_temp_gprs; 207 void *custom_dsa_flush; 208 struct r600_screen *screen; 209 struct radeon_winsys *ws; 210 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 211 struct r600_context ctx; 212 struct r600_vertex_element *vertex_elements; 213 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS]; 214 struct pipe_framebuffer_state framebuffer; 215 unsigned cb_target_mask; 216 unsigned cb_color_control; 217 unsigned pa_sc_line_stipple; 218 unsigned pa_su_sc_mode_cntl; 219 unsigned pa_cl_clip_cntl; 220 /* for saving when using blitter */ 221 struct pipe_stencil_ref stencil_ref; 222 struct pipe_viewport_state viewport; 223 struct pipe_clip_state clip; 224 struct r600_pipe_state config; 225 struct r600_pipe_shader *ps_shader; 226 struct r600_pipe_shader *vs_shader; 227 struct r600_pipe_state vs_const_buffer; 228 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 229 struct r600_pipe_state ps_const_buffer; 230 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS]; 231 struct r600_pipe_rasterizer *rasterizer; 232 struct r600_pipe_state vgt; 233 struct r600_pipe_state spi; 234 struct pipe_query *current_render_cond; 235 unsigned current_render_cond_mode; 236 struct pipe_query *saved_render_cond; 237 unsigned saved_render_cond_mode; 238 /* shader information */ 239 boolean two_side; 240 unsigned sprite_coord_enable; 241 boolean export_16bpc; 242 unsigned alpha_ref; 243 boolean alpha_ref_dirty; 244 unsigned nr_cbufs; 245 struct r600_textures_info vs_samplers; 246 struct r600_textures_info ps_samplers; 247 248 struct u_vbuf *vbuf_mgr; 249 struct util_slab_mempool pool_transfers; 250 boolean have_depth_texture, have_depth_fb; 251 252 unsigned default_ps_gprs, default_vs_gprs; 253}; 254 255/* evergreen_state.c */ 256void evergreen_init_state_functions(struct r600_pipe_context *rctx); 257void evergreen_init_config(struct r600_pipe_context *rctx); 258void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 259void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 260void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 261void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx); 262void evergreen_polygon_offset_update(struct r600_pipe_context *rctx); 263void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx, 264 struct r600_pipe_resource_state *rstate); 265void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx, 266 struct r600_pipe_resource_state *rstate, 267 struct r600_resource *rbuffer, 268 unsigned offset, unsigned stride, 269 enum radeon_bo_usage usage); 270boolean evergreen_is_format_supported(struct pipe_screen *screen, 271 enum pipe_format format, 272 enum pipe_texture_target target, 273 unsigned sample_count, 274 unsigned usage); 275 276/* r600_blit.c */ 277void r600_init_blit_functions(struct r600_pipe_context *rctx); 278void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 279void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture); 280void r600_flush_depth_textures(struct r600_pipe_context *rctx); 281 282/* r600_buffer.c */ 283bool r600_init_resource(struct r600_screen *rscreen, 284 struct r600_resource *res, 285 unsigned size, unsigned alignment, 286 unsigned bind, unsigned usage); 287struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 288 const struct pipe_resource *templ); 289struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen, 290 void *ptr, unsigned bytes, 291 unsigned bind); 292void r600_upload_index_buffer(struct r600_pipe_context *rctx, 293 struct pipe_index_buffer *ib, unsigned count); 294 295 296/* r600_pipe.c */ 297void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 298 unsigned flags); 299 300/* r600_query.c */ 301void r600_init_query_functions(struct r600_pipe_context *rctx); 302 303/* r600_resource.c */ 304void r600_init_context_resource_functions(struct r600_pipe_context *r600); 305 306/* r600_shader.c */ 307int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 308void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 309int r600_find_vs_semantic_index(struct r600_shader *vs, 310 struct r600_shader *ps, int id); 311 312/* r600_state.c */ 313void r600_update_sampler_states(struct r600_pipe_context *rctx); 314void r600_init_state_functions(struct r600_pipe_context *rctx); 315void r600_init_config(struct r600_pipe_context *rctx); 316void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 317void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 318void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 319void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx); 320void r600_polygon_offset_update(struct r600_pipe_context *rctx); 321void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx, 322 struct r600_pipe_resource_state *rstate); 323void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 324 struct r600_resource *rbuffer, 325 unsigned offset, unsigned stride, 326 enum radeon_bo_usage usage); 327void r600_adjust_gprs(struct r600_pipe_context *rctx); 328boolean r600_is_format_supported(struct pipe_screen *screen, 329 enum pipe_format format, 330 enum pipe_texture_target target, 331 unsigned sample_count, 332 unsigned usage); 333 334/* r600_texture.c */ 335void r600_init_screen_texture_functions(struct pipe_screen *screen); 336void r600_init_surface_functions(struct r600_pipe_context *r600); 337uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 338 const unsigned char *swizzle_view, 339 uint32_t *word4_p, uint32_t *yuv_format_p); 340unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 341 unsigned level, unsigned layer); 342 343/* r600_translate.c */ 344void r600_translate_index_buffer(struct r600_pipe_context *r600, 345 struct pipe_index_buffer *ib, 346 unsigned count); 347 348/* r600_state_common.c */ 349void r600_set_index_buffer(struct pipe_context *ctx, 350 const struct pipe_index_buffer *ib); 351void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 352 const struct pipe_vertex_buffer *buffers); 353void *r600_create_vertex_elements(struct pipe_context *ctx, 354 unsigned count, 355 const struct pipe_vertex_element *elements); 356void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 357void r600_bind_blend_state(struct pipe_context *ctx, void *state); 358void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 359void r600_bind_rs_state(struct pipe_context *ctx, void *state); 360void r600_delete_rs_state(struct pipe_context *ctx, void *state); 361void r600_sampler_view_destroy(struct pipe_context *ctx, 362 struct pipe_sampler_view *state); 363void r600_delete_state(struct pipe_context *ctx, void *state); 364void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 365void *r600_create_shader_state(struct pipe_context *ctx, 366 const struct pipe_shader_state *state); 367void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 368void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 369void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 370void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 371void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 372 struct pipe_resource *buffer); 373struct pipe_stream_output_target * 374r600_create_so_target(struct pipe_context *ctx, 375 struct pipe_resource *buffer, 376 unsigned buffer_offset, 377 unsigned buffer_size); 378void r600_so_target_destroy(struct pipe_context *ctx, 379 struct pipe_stream_output_target *target); 380void r600_set_so_targets(struct pipe_context *ctx, 381 unsigned num_targets, 382 struct pipe_stream_output_target **targets, 383 unsigned append_bitmask); 384void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 385 const struct pipe_stencil_ref *state); 386void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 387 388/* 389 * common helpers 390 */ 391static INLINE u32 S_FIXED(float value, u32 frac_bits) 392{ 393 return value * (1 << frac_bits); 394} 395#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 396 397static inline unsigned r600_tex_aniso_filter(unsigned filter) 398{ 399 if (filter <= 1) return 0; 400 if (filter <= 2) return 1; 401 if (filter <= 4) return 2; 402 if (filter <= 8) return 3; 403 /* else */ return 4; 404} 405 406/* 12.4 fixed-point */ 407static INLINE unsigned r600_pack_float_12p4(float x) 408{ 409 return x <= 0 ? 0 : 410 x >= 4096 ? 0xffff : x * 16; 411} 412 413#endif 414