r600_pipe.h revision c26fadf195876271e559f844c1fc88effa6a60c1
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71 unsigned pkt_flags; 72}; 73 74struct r600_surface_sync_cmd { 75 struct r600_atom atom; 76 unsigned flush_flags; /* CP_COHER_CNTL */ 77}; 78 79struct r600_db_misc_state { 80 struct r600_atom atom; 81 bool occlusion_query_enabled; 82 bool flush_depthstencil_through_cb; 83}; 84 85struct r600_cb_misc_state { 86 struct r600_atom atom; 87 unsigned cb_color_control; /* this comes from blend state */ 88 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 89 unsigned nr_cbufs; 90 unsigned nr_ps_color_outputs; 91 bool multiwrite; 92 bool dual_src_blend; 93}; 94 95enum r600_pipe_state_id { 96 R600_PIPE_STATE_BLEND = 0, 97 R600_PIPE_STATE_BLEND_COLOR, 98 R600_PIPE_STATE_CONFIG, 99 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 100 R600_PIPE_STATE_CLIP, 101 R600_PIPE_STATE_SCISSOR, 102 R600_PIPE_STATE_VIEWPORT, 103 R600_PIPE_STATE_RASTERIZER, 104 R600_PIPE_STATE_VGT, 105 R600_PIPE_STATE_FRAMEBUFFER, 106 R600_PIPE_STATE_DSA, 107 R600_PIPE_STATE_STENCIL_REF, 108 R600_PIPE_STATE_PS_SHADER, 109 R600_PIPE_STATE_VS_SHADER, 110 R600_PIPE_STATE_CONSTANT, 111 R600_PIPE_STATE_SAMPLER, 112 R600_PIPE_STATE_RESOURCE, 113 R600_PIPE_STATE_POLYGON_OFFSET, 114 R600_PIPE_STATE_FETCH_SHADER, 115 R600_PIPE_STATE_SPI, 116 R600_PIPE_NSTATES 117}; 118 119struct compute_memory_pool; 120void compute_memory_pool_delete(struct compute_memory_pool* pool); 121struct compute_memory_pool* compute_memory_pool_new( 122 struct r600_screen *rscreen); 123 124struct r600_pipe_fences { 125 struct r600_resource *bo; 126 unsigned *data; 127 unsigned next_index; 128 /* linked list of preallocated blocks */ 129 struct list_head blocks; 130 /* linked list of freed fences */ 131 struct list_head pool; 132 pipe_mutex mutex; 133}; 134 135struct r600_screen { 136 struct pipe_screen screen; 137 struct radeon_winsys *ws; 138 unsigned family; 139 enum chip_class chip_class; 140 struct radeon_info info; 141 bool has_streamout; 142 struct r600_tiling_info tiling_info; 143 struct r600_pipe_fences fences; 144 145 bool use_surface_alloc; 146 147 /*for compute global memory binding, we allocate stuff here, instead of 148 * buffers. 149 * XXX: Not sure if this is the best place for global_pool. Also, 150 * it's not thread safe, so it won't work with multiple contexts. */ 151 struct compute_memory_pool *global_pool; 152}; 153 154struct r600_pipe_sampler_view { 155 struct pipe_sampler_view base; 156 struct r600_resource *tex_resource; 157 uint32_t tex_resource_words[8]; 158}; 159 160struct r600_pipe_rasterizer { 161 struct r600_pipe_state rstate; 162 boolean flatshade; 163 boolean two_side; 164 unsigned sprite_coord_enable; 165 unsigned clip_plane_enable; 166 unsigned pa_sc_line_stipple; 167 unsigned pa_cl_clip_cntl; 168 float offset_units; 169 float offset_scale; 170 bool scissor_enable; 171}; 172 173struct r600_pipe_blend { 174 struct r600_pipe_state rstate; 175 unsigned cb_target_mask; 176 unsigned cb_color_control; 177 bool dual_src_blend; 178}; 179 180struct r600_pipe_dsa { 181 struct r600_pipe_state rstate; 182 unsigned alpha_ref; 183 ubyte valuemask[2]; 184 ubyte writemask[2]; 185 unsigned sx_alpha_test_control; 186}; 187 188struct r600_vertex_element 189{ 190 unsigned count; 191 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 192 struct r600_resource *fetch_shader; 193 unsigned fs_size; 194 struct r600_pipe_state rstate; 195}; 196 197struct r600_pipe_shader; 198 199struct r600_pipe_shader_selector { 200 struct r600_pipe_shader *current; 201 202 struct tgsi_token *tokens; 203 struct pipe_stream_output_info so; 204 205 unsigned num_shaders; 206 207 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 208 unsigned type; 209 210 unsigned nr_ps_max_color_exports; 211}; 212 213struct r600_pipe_shader { 214 struct r600_pipe_shader_selector *selector; 215 struct r600_pipe_shader *next_variant; 216 struct r600_shader shader; 217 struct r600_pipe_state rstate; 218 struct r600_resource *bo; 219 struct r600_resource *bo_fetch; 220 struct r600_vertex_element vertex_elements; 221 unsigned sprite_coord_enable; 222 unsigned flatshade; 223 unsigned pa_cl_vs_out_cntl; 224 unsigned nr_ps_color_outputs; 225 unsigned key; 226 unsigned db_shader_control; 227 unsigned ps_depth_export; 228}; 229 230struct r600_pipe_sampler_state { 231 struct r600_pipe_state rstate; 232 boolean seamless_cube_map; 233}; 234 235/* needed for blitter save */ 236#define NUM_TEX_UNITS 16 237 238struct r600_samplerview_state 239{ 240 struct r600_atom atom; 241 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 242 uint32_t enabled_mask; 243 uint32_t dirty_mask; 244 uint32_t depth_texture_mask; /* which textures are depth */ 245}; 246 247struct r600_textures_info { 248 struct r600_samplerview_state views; 249 250 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 251 unsigned n_samplers; 252 bool samplers_dirty; 253 bool is_array_sampler[NUM_TEX_UNITS]; 254}; 255 256struct r600_fence { 257 struct pipe_reference reference; 258 unsigned index; /* in the shared bo */ 259 struct r600_resource *sleep_bo; 260 struct list_head head; 261}; 262 263#define FENCE_BLOCK_SIZE 16 264 265struct r600_fence_block { 266 struct r600_fence fences[FENCE_BLOCK_SIZE]; 267 struct list_head head; 268}; 269 270#define R600_CONSTANT_ARRAY_SIZE 256 271#define R600_RESOURCE_ARRAY_SIZE 160 272 273struct r600_stencil_ref 274{ 275 ubyte ref_value[2]; 276 ubyte valuemask[2]; 277 ubyte writemask[2]; 278}; 279 280struct r600_constbuf_state 281{ 282 struct r600_atom atom; 283 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 284 uint32_t enabled_mask; 285 uint32_t dirty_mask; 286}; 287 288struct r600_vertexbuf_state 289{ 290 struct r600_atom atom; 291 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 292 uint32_t enabled_mask; /* non-NULL buffers */ 293 uint32_t dirty_mask; 294}; 295 296struct r600_context { 297 struct pipe_context context; 298 struct blitter_context *blitter; 299 enum radeon_family family; 300 enum chip_class chip_class; 301 boolean has_vertex_cache; 302 unsigned r6xx_num_clause_temp_gprs; 303 void *custom_dsa_flush; 304 struct r600_screen *screen; 305 struct radeon_winsys *ws; 306 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 307 struct r600_vertex_element *vertex_elements; 308 struct pipe_framebuffer_state framebuffer; 309 unsigned compute_cb_target_mask; 310 unsigned sx_alpha_test_control; 311 unsigned db_shader_control; 312 unsigned pa_sc_line_stipple; 313 unsigned pa_cl_clip_cntl; 314 /* for saving when using blitter */ 315 struct pipe_stencil_ref stencil_ref; 316 struct pipe_viewport_state viewport; 317 struct pipe_clip_state clip; 318 struct r600_pipe_shader_selector *ps_shader; 319 struct r600_pipe_shader_selector *vs_shader; 320 struct r600_pipe_compute *cs_shader; 321 struct r600_pipe_rasterizer *rasterizer; 322 struct r600_pipe_state vgt; 323 struct r600_pipe_state spi; 324 struct pipe_query *current_render_cond; 325 unsigned current_render_cond_mode; 326 struct pipe_query *saved_render_cond; 327 unsigned saved_render_cond_mode; 328 /* shader information */ 329 boolean two_side; 330 boolean spi_dirty; 331 unsigned sprite_coord_enable; 332 boolean flatshade; 333 boolean export_16bpc; 334 unsigned alpha_ref; 335 boolean alpha_ref_dirty; 336 unsigned nr_cbufs; 337 338 struct u_upload_mgr *uploader; 339 struct util_slab_mempool pool_transfers; 340 341 unsigned default_ps_gprs, default_vs_gprs; 342 343 /* States based on r600_atom. */ 344 struct list_head dirty_states; 345 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 346 /** Compute specific registers initializations. The start_cs_cmd atom 347 * must be emitted before start_compute_cs_cmd. */ 348 struct r600_command_buffer start_compute_cs_cmd; 349 struct r600_surface_sync_cmd surface_sync_cmd; 350 struct r600_atom r6xx_flush_and_inv_cmd; 351 struct r600_cb_misc_state cb_misc_state; 352 struct r600_db_misc_state db_misc_state; 353 /** Vertex buffers for fetch shaders */ 354 struct r600_vertexbuf_state vertex_buffer_state; 355 /** Vertex buffers for compute shaders */ 356 struct r600_vertexbuf_state cs_vertex_buffer_state; 357 struct r600_constbuf_state vs_constbuf_state; 358 struct r600_constbuf_state ps_constbuf_state; 359 struct r600_textures_info vs_samplers; 360 struct r600_textures_info ps_samplers; 361 362 struct radeon_winsys_cs *cs; 363 364 struct r600_range *range; 365 unsigned nblocks; 366 struct r600_block **blocks; 367 struct list_head dirty; 368 struct list_head enable_list; 369 unsigned pm4_dirty_cdwords; 370 unsigned ctx_pm4_ndwords; 371 372 /* The list of active queries. Only one query of each type can be active. */ 373 int num_occlusion_queries; 374 375 /* Manage queries in two separate groups: 376 * The timer ones and the others (streamout, occlusion). 377 * 378 * We do this because we should only suspend non-timer queries for u_blitter, 379 * and later if the non-timer queries are suspended, the context flush should 380 * only suspend and resume the timer queries. */ 381 struct list_head active_timer_queries; 382 unsigned num_cs_dw_timer_queries_suspend; 383 struct list_head active_nontimer_queries; 384 unsigned num_cs_dw_nontimer_queries_suspend; 385 386 unsigned num_cs_dw_streamout_end; 387 388 unsigned backend_mask; 389 unsigned max_db; /* for OQ */ 390 unsigned flags; 391 boolean predicate_drawing; 392 393 unsigned num_so_targets; 394 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 395 boolean streamout_start; 396 unsigned streamout_append_bitmask; 397 398 /* There is no scissor enable bit on r6xx, so we must use a workaround. 399 * These track the current scissor state. */ 400 bool scissor_enable; 401 struct pipe_scissor_state scissor_state; 402 403 /* With rasterizer discard, there doesn't have to be a pixel shader. 404 * In that case, we bind this one: */ 405 void *dummy_pixel_shader; 406 407 boolean dual_src_blend; 408 409 /* Index buffer. */ 410 struct pipe_index_buffer index_buffer; 411}; 412 413static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 414{ 415 atom->emit(rctx, atom); 416 atom->dirty = false; 417 if (atom->head.next && atom->head.prev) 418 LIST_DELINIT(&atom->head); 419} 420 421static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 422{ 423 if (!state->dirty) { 424 if (state->flags & EMIT_EARLY) { 425 LIST_ADD(&state->head, &rctx->dirty_states); 426 } else { 427 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 428 } 429 state->dirty = true; 430 } 431} 432 433/* evergreen_state.c */ 434void evergreen_init_state_functions(struct r600_context *rctx); 435void evergreen_init_atom_start_cs(struct r600_context *rctx); 436void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 437void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 438void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 439void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 440void evergreen_polygon_offset_update(struct r600_context *rctx); 441boolean evergreen_is_format_supported(struct pipe_screen *screen, 442 enum pipe_format format, 443 enum pipe_texture_target target, 444 unsigned sample_count, 445 unsigned usage); 446void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, 447 const struct pipe_framebuffer_state *state, int cb); 448 449 450void evergreen_update_dual_export_state(struct r600_context * rctx); 451 452/* r600_blit.c */ 453void r600_init_blit_functions(struct r600_context *rctx); 454void r600_blit_uncompress_depth(struct pipe_context *ctx, 455 struct r600_resource_texture *texture, 456 struct r600_resource_texture *staging, 457 unsigned first_level, unsigned last_level, 458 unsigned first_layer, unsigned last_layer); 459void r600_flush_depth_textures(struct r600_context *rctx, 460 struct r600_samplerview_state *textures); 461/* r600_buffer.c */ 462bool r600_init_resource(struct r600_screen *rscreen, 463 struct r600_resource *res, 464 unsigned size, unsigned alignment, 465 unsigned bind, unsigned usage); 466struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 467 const struct pipe_resource *templ); 468 469/* r600_pipe.c */ 470void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 471 unsigned flags); 472 473/* r600_query.c */ 474void r600_init_query_functions(struct r600_context *rctx); 475void r600_suspend_nontimer_queries(struct r600_context *ctx); 476void r600_resume_nontimer_queries(struct r600_context *ctx); 477void r600_suspend_timer_queries(struct r600_context *ctx); 478void r600_resume_timer_queries(struct r600_context *ctx); 479 480/* r600_resource.c */ 481void r600_init_context_resource_functions(struct r600_context *r600); 482 483/* r600_shader.c */ 484int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 485#ifdef HAVE_OPENCL 486int r600_compute_shader_create(struct pipe_context * ctx, 487 LLVMModuleRef mod, struct r600_bytecode * bytecode); 488#endif 489void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 490 491/* r600_state.c */ 492void r600_set_scissor_state(struct r600_context *rctx, 493 const struct pipe_scissor_state *state); 494void r600_update_sampler_states(struct r600_context *rctx); 495void r600_init_state_functions(struct r600_context *rctx); 496void r600_init_atom_start_cs(struct r600_context *rctx); 497void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 498void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 499void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 500void *r600_create_db_flush_dsa(struct r600_context *rctx); 501void r600_polygon_offset_update(struct r600_context *rctx); 502void r600_adjust_gprs(struct r600_context *rctx); 503boolean r600_is_format_supported(struct pipe_screen *screen, 504 enum pipe_format format, 505 enum pipe_texture_target target, 506 unsigned sample_count, 507 unsigned usage); 508void r600_update_dual_export_state(struct r600_context * rctx); 509 510/* r600_texture.c */ 511void r600_init_screen_texture_functions(struct pipe_screen *screen); 512void r600_init_surface_functions(struct r600_context *r600); 513uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 514 const unsigned char *swizzle_view, 515 uint32_t *word4_p, uint32_t *yuv_format_p); 516unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 517 unsigned level, unsigned layer); 518 519/* r600_translate.c */ 520void r600_translate_index_buffer(struct r600_context *r600, 521 struct pipe_index_buffer *ib, 522 unsigned count); 523 524/* r600_state_common.c */ 525void r600_init_atom(struct r600_atom *atom, 526 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 527 unsigned num_dw, enum r600_atom_flags flags); 528void r600_init_common_atoms(struct r600_context *rctx); 529unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 530void r600_texture_barrier(struct pipe_context *ctx); 531void r600_set_index_buffer(struct pipe_context *ctx, 532 const struct pipe_index_buffer *ib); 533void r600_vertex_buffers_dirty(struct r600_context *rctx); 534void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 535 const struct pipe_vertex_buffer *input); 536void r600_sampler_views_dirty(struct r600_context *rctx, 537 struct r600_samplerview_state *state); 538void r600_set_sampler_views(struct r600_context *rctx, 539 struct r600_textures_info *dst, 540 unsigned count, 541 struct pipe_sampler_view **views); 542void *r600_create_vertex_elements(struct pipe_context *ctx, 543 unsigned count, 544 const struct pipe_vertex_element *elements); 545void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 546void r600_bind_blend_state(struct pipe_context *ctx, void *state); 547void r600_set_blend_color(struct pipe_context *ctx, 548 const struct pipe_blend_color *state); 549void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 550void r600_set_max_scissor(struct r600_context *rctx); 551void r600_bind_rs_state(struct pipe_context *ctx, void *state); 552void r600_delete_rs_state(struct pipe_context *ctx, void *state); 553void r600_sampler_view_destroy(struct pipe_context *ctx, 554 struct pipe_sampler_view *state); 555void r600_delete_state(struct pipe_context *ctx, void *state); 556void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 557void *r600_create_shader_state_ps(struct pipe_context *ctx, 558 const struct pipe_shader_state *state); 559void *r600_create_shader_state_vs(struct pipe_context *ctx, 560 const struct pipe_shader_state *state); 561void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 562void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 563void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 564void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 565void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 566void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 567 struct pipe_constant_buffer *cb); 568struct pipe_stream_output_target * 569r600_create_so_target(struct pipe_context *ctx, 570 struct pipe_resource *buffer, 571 unsigned buffer_offset, 572 unsigned buffer_size); 573void r600_so_target_destroy(struct pipe_context *ctx, 574 struct pipe_stream_output_target *target); 575void r600_set_so_targets(struct pipe_context *ctx, 576 unsigned num_targets, 577 struct pipe_stream_output_target **targets, 578 unsigned append_bitmask); 579void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 580 const struct pipe_stencil_ref *state); 581void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 582uint32_t r600_translate_stencil_op(int s_op); 583uint32_t r600_translate_fill(uint32_t func); 584unsigned r600_tex_wrap(unsigned wrap); 585unsigned r600_tex_filter(unsigned filter); 586unsigned r600_tex_mipfilter(unsigned filter); 587unsigned r600_tex_compare(unsigned compare); 588 589/* 590 * Helpers for building command buffers 591 */ 592 593#define PKT3_SET_CONFIG_REG 0x68 594#define PKT3_SET_CONTEXT_REG 0x69 595#define PKT3_SET_CTL_CONST 0x6F 596#define PKT3_SET_LOOP_CONST 0x6C 597 598#define R600_CONFIG_REG_OFFSET 0x08000 599#define R600_CONTEXT_REG_OFFSET 0x28000 600#define R600_CTL_CONST_OFFSET 0x3CFF0 601#define R600_LOOP_CONST_OFFSET 0X0003E200 602#define EG_LOOP_CONST_OFFSET 0x0003A200 603 604#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 605#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 606#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 607#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 608#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 609 610static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 611{ 612 cb->buf[cb->atom.num_dw++] = value; 613} 614 615static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 616{ 617 assert(reg < R600_CONTEXT_REG_OFFSET); 618 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 619 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 620 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 621} 622 623/** 624 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 625 * shaders. 626 */ 627static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 628{ 629 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 630 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 631 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 632 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 633} 634 635/** 636 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 637 * shaders. 638 */ 639static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 640{ 641 assert(reg >= R600_CTL_CONST_OFFSET); 642 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 643 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 644 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 645} 646 647static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 648{ 649 assert(reg >= R600_LOOP_CONST_OFFSET); 650 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 651 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 652 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 653} 654 655/** 656 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 657 * shaders. 658 */ 659static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 660{ 661 assert(reg >= EG_LOOP_CONST_OFFSET); 662 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 663 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 664 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 665} 666 667static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 668{ 669 r600_store_config_reg_seq(cb, reg, 1); 670 r600_store_value(cb, value); 671} 672 673static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 674{ 675 r600_store_context_reg_seq(cb, reg, 1); 676 r600_store_value(cb, value); 677} 678 679static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 680{ 681 r600_store_ctl_const_seq(cb, reg, 1); 682 r600_store_value(cb, value); 683} 684 685static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 686{ 687 r600_store_loop_const_seq(cb, reg, 1); 688 r600_store_value(cb, value); 689} 690 691static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 692{ 693 eg_store_loop_const_seq(cb, reg, 1); 694 r600_store_value(cb, value); 695} 696 697void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 698void r600_release_command_buffer(struct r600_command_buffer *cb); 699 700/* 701 * Helpers for emitting state into a command stream directly. 702 */ 703 704static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 705 enum radeon_bo_usage usage) 706{ 707 assert(usage); 708 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 709} 710 711static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 712{ 713 cs->buf[cs->cdw++] = value; 714} 715 716static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr) 717{ 718 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS); 719 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0])); 720 cs->cdw += num; 721} 722 723static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 724{ 725 assert(reg < R600_CONTEXT_REG_OFFSET); 726 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 727 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 728 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 729} 730 731static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 732{ 733 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 734 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 735 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 736 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 737} 738 739static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 740{ 741 assert(reg >= R600_CTL_CONST_OFFSET); 742 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 743 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 744 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 745} 746 747static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 748{ 749 r600_write_config_reg_seq(cs, reg, 1); 750 r600_write_value(cs, value); 751} 752 753static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 754{ 755 r600_write_context_reg_seq(cs, reg, 1); 756 r600_write_value(cs, value); 757} 758 759static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 760{ 761 r600_write_ctl_const_seq(cs, reg, 1); 762 r600_write_value(cs, value); 763} 764 765/* 766 * common helpers 767 */ 768static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 769{ 770 return value * (1 << frac_bits); 771} 772#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 773 774static inline unsigned r600_tex_aniso_filter(unsigned filter) 775{ 776 if (filter <= 1) return 0; 777 if (filter <= 2) return 1; 778 if (filter <= 4) return 2; 779 if (filter <= 8) return 3; 780 /* else */ return 4; 781} 782 783/* 12.4 fixed-point */ 784static INLINE unsigned r600_pack_float_12p4(float x) 785{ 786 return x <= 0 ? 0 : 787 x >= 4096 ? 0xffff : x * 16; 788} 789 790static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 791{ 792 struct r600_screen *rscreen = (struct r600_screen*)screen; 793 struct r600_resource *rresource = (struct r600_resource*)resource; 794 795 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 796} 797 798#endif 799