r600_pipe.h revision d1ca16b2738644d17c10e736ca36981f69f5fa87
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71 unsigned pkt_flags; 72}; 73 74struct r600_surface_sync_cmd { 75 struct r600_atom atom; 76 unsigned flush_flags; /* CP_COHER_CNTL */ 77}; 78 79struct r600_db_misc_state { 80 struct r600_atom atom; 81 bool occlusion_query_enabled; 82 bool flush_depthstencil_through_cb; 83}; 84 85struct r600_cb_misc_state { 86 struct r600_atom atom; 87 unsigned cb_color_control; /* this comes from blend state */ 88 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 89 unsigned nr_cbufs; 90 unsigned nr_ps_color_outputs; 91 bool multiwrite; 92 bool dual_src_blend; 93}; 94 95enum r600_pipe_state_id { 96 R600_PIPE_STATE_BLEND = 0, 97 R600_PIPE_STATE_BLEND_COLOR, 98 R600_PIPE_STATE_CONFIG, 99 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 100 R600_PIPE_STATE_CLIP, 101 R600_PIPE_STATE_SCISSOR, 102 R600_PIPE_STATE_VIEWPORT, 103 R600_PIPE_STATE_RASTERIZER, 104 R600_PIPE_STATE_VGT, 105 R600_PIPE_STATE_FRAMEBUFFER, 106 R600_PIPE_STATE_DSA, 107 R600_PIPE_STATE_STENCIL_REF, 108 R600_PIPE_STATE_PS_SHADER, 109 R600_PIPE_STATE_VS_SHADER, 110 R600_PIPE_STATE_CONSTANT, 111 R600_PIPE_STATE_SAMPLER, 112 R600_PIPE_STATE_RESOURCE, 113 R600_PIPE_STATE_POLYGON_OFFSET, 114 R600_PIPE_STATE_FETCH_SHADER, 115 R600_PIPE_STATE_SPI, 116 R600_PIPE_NSTATES 117}; 118 119struct compute_memory_pool; 120void compute_memory_pool_delete(struct compute_memory_pool* pool); 121struct compute_memory_pool* compute_memory_pool_new( 122 struct r600_screen *rscreen); 123 124struct r600_pipe_fences { 125 struct r600_resource *bo; 126 unsigned *data; 127 unsigned next_index; 128 /* linked list of preallocated blocks */ 129 struct list_head blocks; 130 /* linked list of freed fences */ 131 struct list_head pool; 132 pipe_mutex mutex; 133}; 134 135struct r600_screen { 136 struct pipe_screen screen; 137 struct radeon_winsys *ws; 138 unsigned family; 139 enum chip_class chip_class; 140 struct radeon_info info; 141 bool has_streamout; 142 struct r600_tiling_info tiling_info; 143 struct r600_pipe_fences fences; 144 145 bool use_surface_alloc; 146 147 /*for compute global memory binding, we allocate stuff here, instead of 148 * buffers. 149 * XXX: Not sure if this is the best place for global_pool. Also, 150 * it's not thread safe, so it won't work with multiple contexts. */ 151 struct compute_memory_pool *global_pool; 152}; 153 154struct r600_pipe_sampler_view { 155 struct pipe_sampler_view base; 156 struct r600_pipe_resource_state state; 157}; 158 159struct r600_pipe_rasterizer { 160 struct r600_pipe_state rstate; 161 boolean flatshade; 162 boolean two_side; 163 unsigned sprite_coord_enable; 164 unsigned clip_plane_enable; 165 unsigned pa_sc_line_stipple; 166 unsigned pa_cl_clip_cntl; 167 float offset_units; 168 float offset_scale; 169 bool scissor_enable; 170}; 171 172struct r600_pipe_blend { 173 struct r600_pipe_state rstate; 174 unsigned cb_target_mask; 175 unsigned cb_color_control; 176 bool dual_src_blend; 177}; 178 179struct r600_pipe_dsa { 180 struct r600_pipe_state rstate; 181 unsigned alpha_ref; 182 ubyte valuemask[2]; 183 ubyte writemask[2]; 184 unsigned sx_alpha_test_control; 185}; 186 187struct r600_vertex_element 188{ 189 unsigned count; 190 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 191 struct r600_resource *fetch_shader; 192 unsigned fs_size; 193 struct r600_pipe_state rstate; 194}; 195 196struct r600_pipe_shader; 197 198struct r600_pipe_shader_selector { 199 struct r600_pipe_shader *current; 200 201 struct tgsi_token *tokens; 202 struct pipe_stream_output_info so; 203 204 unsigned num_shaders; 205 206 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 207 unsigned type; 208 209 unsigned nr_ps_max_color_exports; 210}; 211 212struct r600_pipe_shader { 213 struct r600_pipe_shader_selector *selector; 214 struct r600_pipe_shader *next_variant; 215 struct r600_shader shader; 216 struct r600_pipe_state rstate; 217 struct r600_resource *bo; 218 struct r600_resource *bo_fetch; 219 struct r600_vertex_element vertex_elements; 220 unsigned sprite_coord_enable; 221 unsigned flatshade; 222 unsigned pa_cl_vs_out_cntl; 223 unsigned nr_ps_color_outputs; 224 unsigned key; 225 unsigned db_shader_control; 226 unsigned ps_depth_export; 227}; 228 229struct r600_pipe_sampler_state { 230 struct r600_pipe_state rstate; 231 boolean seamless_cube_map; 232}; 233 234/* needed for blitter save */ 235#define NUM_TEX_UNITS 16 236 237struct r600_textures_info { 238 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 239 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 240 unsigned n_views; 241 unsigned n_samplers; 242 bool samplers_dirty; 243 bool is_array_sampler[NUM_TEX_UNITS]; 244}; 245 246struct r600_fence { 247 struct pipe_reference reference; 248 unsigned index; /* in the shared bo */ 249 struct r600_resource *sleep_bo; 250 struct list_head head; 251}; 252 253#define FENCE_BLOCK_SIZE 16 254 255struct r600_fence_block { 256 struct r600_fence fences[FENCE_BLOCK_SIZE]; 257 struct list_head head; 258}; 259 260#define R600_CONSTANT_ARRAY_SIZE 256 261#define R600_RESOURCE_ARRAY_SIZE 160 262 263struct r600_stencil_ref 264{ 265 ubyte ref_value[2]; 266 ubyte valuemask[2]; 267 ubyte writemask[2]; 268}; 269 270struct r600_constbuf_state 271{ 272 struct r600_atom atom; 273 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 274 uint32_t enabled_mask; 275 uint32_t dirty_mask; 276}; 277 278struct r600_vertexbuf_state 279{ 280 struct r600_atom atom; 281 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 282 uint32_t enabled_mask; /* non-NULL buffers */ 283 uint32_t dirty_mask; 284}; 285 286struct r600_context { 287 struct pipe_context context; 288 struct blitter_context *blitter; 289 enum radeon_family family; 290 enum chip_class chip_class; 291 boolean has_vertex_cache; 292 unsigned r6xx_num_clause_temp_gprs; 293 void *custom_dsa_flush; 294 struct r600_screen *screen; 295 struct radeon_winsys *ws; 296 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 297 struct r600_vertex_element *vertex_elements; 298 struct pipe_framebuffer_state framebuffer; 299 unsigned compute_cb_target_mask; 300 unsigned sx_alpha_test_control; 301 unsigned db_shader_control; 302 unsigned pa_sc_line_stipple; 303 unsigned pa_cl_clip_cntl; 304 /* for saving when using blitter */ 305 struct pipe_stencil_ref stencil_ref; 306 struct pipe_viewport_state viewport; 307 struct pipe_clip_state clip; 308 struct r600_pipe_shader_selector *ps_shader; 309 struct r600_pipe_shader_selector *vs_shader; 310 struct r600_pipe_compute *cs_shader; 311 struct r600_pipe_rasterizer *rasterizer; 312 struct r600_pipe_state vgt; 313 struct r600_pipe_state spi; 314 struct pipe_query *current_render_cond; 315 unsigned current_render_cond_mode; 316 struct pipe_query *saved_render_cond; 317 unsigned saved_render_cond_mode; 318 /* shader information */ 319 boolean two_side; 320 boolean spi_dirty; 321 unsigned sprite_coord_enable; 322 boolean flatshade; 323 boolean export_16bpc; 324 unsigned alpha_ref; 325 boolean alpha_ref_dirty; 326 unsigned nr_cbufs; 327 struct r600_textures_info vs_samplers; 328 struct r600_textures_info ps_samplers; 329 330 struct u_upload_mgr *uploader; 331 struct util_slab_mempool pool_transfers; 332 boolean have_depth_texture; 333 334 unsigned default_ps_gprs, default_vs_gprs; 335 336 /* States based on r600_atom. */ 337 struct list_head dirty_states; 338 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 339 /** Compute specific registers initializations. The start_cs_cmd atom 340 * must be emitted before start_compute_cs_cmd. */ 341 struct r600_command_buffer start_compute_cs_cmd; 342 struct r600_surface_sync_cmd surface_sync_cmd; 343 struct r600_atom r6xx_flush_and_inv_cmd; 344 struct r600_cb_misc_state cb_misc_state; 345 struct r600_db_misc_state db_misc_state; 346 /** Vertex buffers for fetch shaders */ 347 struct r600_vertexbuf_state vertex_buffer_state; 348 /** Vertex buffers for compute shaders */ 349 struct r600_vertexbuf_state cs_vertex_buffer_state; 350 struct r600_constbuf_state vs_constbuf_state; 351 struct r600_constbuf_state ps_constbuf_state; 352 353 struct radeon_winsys_cs *cs; 354 355 struct r600_range *range; 356 unsigned nblocks; 357 struct r600_block **blocks; 358 struct list_head dirty; 359 struct list_head resource_dirty; 360 struct list_head enable_list; 361 unsigned pm4_dirty_cdwords; 362 unsigned ctx_pm4_ndwords; 363 364 /* The list of active queries. Only one query of each type can be active. */ 365 int num_occlusion_queries; 366 367 /* Manage queries in two separate groups: 368 * The timer ones and the others (streamout, occlusion). 369 * 370 * We do this because we should only suspend non-timer queries for u_blitter, 371 * and later if the non-timer queries are suspended, the context flush should 372 * only suspend and resume the timer queries. */ 373 struct list_head active_timer_queries; 374 unsigned num_cs_dw_timer_queries_suspend; 375 struct list_head active_nontimer_queries; 376 unsigned num_cs_dw_nontimer_queries_suspend; 377 378 unsigned num_cs_dw_streamout_end; 379 380 unsigned backend_mask; 381 unsigned max_db; /* for OQ */ 382 unsigned flags; 383 boolean predicate_drawing; 384 struct r600_range ps_resources; 385 struct r600_range vs_resources; 386 int num_ps_resources, num_vs_resources; 387 388 unsigned num_so_targets; 389 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 390 boolean streamout_start; 391 unsigned streamout_append_bitmask; 392 393 /* There is no scissor enable bit on r6xx, so we must use a workaround. 394 * These track the current scissor state. */ 395 bool scissor_enable; 396 struct pipe_scissor_state scissor_state; 397 398 /* With rasterizer discard, there doesn't have to be a pixel shader. 399 * In that case, we bind this one: */ 400 void *dummy_pixel_shader; 401 402 boolean dual_src_blend; 403 404 /* Index buffer. */ 405 struct pipe_index_buffer index_buffer; 406}; 407 408static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 409{ 410 atom->emit(rctx, atom); 411 atom->dirty = false; 412 if (atom->head.next && atom->head.prev) 413 LIST_DELINIT(&atom->head); 414} 415 416static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 417{ 418 if (!state->dirty) { 419 if (state->flags & EMIT_EARLY) { 420 LIST_ADD(&state->head, &rctx->dirty_states); 421 } else { 422 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 423 } 424 state->dirty = true; 425 } 426} 427 428/* evergreen_state.c */ 429void evergreen_init_state_functions(struct r600_context *rctx); 430void evergreen_init_atom_start_cs(struct r600_context *rctx); 431void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 432void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 433void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 434void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 435void evergreen_polygon_offset_update(struct r600_context *rctx); 436boolean evergreen_is_format_supported(struct pipe_screen *screen, 437 enum pipe_format format, 438 enum pipe_texture_target target, 439 unsigned sample_count, 440 unsigned usage); 441void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, 442 const struct pipe_framebuffer_state *state, int cb); 443 444 445void evergreen_update_dual_export_state(struct r600_context * rctx); 446 447/* r600_blit.c */ 448void r600_init_blit_functions(struct r600_context *rctx); 449void r600_blit_uncompress_depth(struct pipe_context *ctx, 450 struct r600_resource_texture *texture, 451 struct r600_resource_texture *staging, 452 unsigned first_level, unsigned last_level, 453 unsigned first_layer, unsigned last_layer); 454void r600_flush_all_depth_textures(struct r600_context *rctx); 455 456/* r600_buffer.c */ 457bool r600_init_resource(struct r600_screen *rscreen, 458 struct r600_resource *res, 459 unsigned size, unsigned alignment, 460 unsigned bind, unsigned usage); 461struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 462 const struct pipe_resource *templ); 463 464/* r600_pipe.c */ 465void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 466 unsigned flags); 467 468/* r600_query.c */ 469void r600_init_query_functions(struct r600_context *rctx); 470void r600_suspend_nontimer_queries(struct r600_context *ctx); 471void r600_resume_nontimer_queries(struct r600_context *ctx); 472void r600_suspend_timer_queries(struct r600_context *ctx); 473void r600_resume_timer_queries(struct r600_context *ctx); 474 475/* r600_resource.c */ 476void r600_init_context_resource_functions(struct r600_context *r600); 477 478/* r600_shader.c */ 479int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 480#ifdef HAVE_OPENCL 481int r600_compute_shader_create(struct pipe_context * ctx, 482 LLVMModuleRef mod, struct r600_bytecode * bytecode); 483#endif 484void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 485 486/* r600_state.c */ 487void r600_set_scissor_state(struct r600_context *rctx, 488 const struct pipe_scissor_state *state); 489void r600_update_sampler_states(struct r600_context *rctx); 490void r600_init_state_functions(struct r600_context *rctx); 491void r600_init_atom_start_cs(struct r600_context *rctx); 492void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 493void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 494void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 495void *r600_create_db_flush_dsa(struct r600_context *rctx); 496void r600_polygon_offset_update(struct r600_context *rctx); 497void r600_adjust_gprs(struct r600_context *rctx); 498boolean r600_is_format_supported(struct pipe_screen *screen, 499 enum pipe_format format, 500 enum pipe_texture_target target, 501 unsigned sample_count, 502 unsigned usage); 503void r600_update_dual_export_state(struct r600_context * rctx); 504 505/* r600_texture.c */ 506void r600_init_screen_texture_functions(struct pipe_screen *screen); 507void r600_init_surface_functions(struct r600_context *r600); 508uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 509 const unsigned char *swizzle_view, 510 uint32_t *word4_p, uint32_t *yuv_format_p); 511unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 512 unsigned level, unsigned layer); 513 514/* r600_translate.c */ 515void r600_translate_index_buffer(struct r600_context *r600, 516 struct pipe_index_buffer *ib, 517 unsigned count); 518 519/* r600_state_common.c */ 520void r600_init_atom(struct r600_atom *atom, 521 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 522 unsigned num_dw, enum r600_atom_flags flags); 523void r600_init_common_atoms(struct r600_context *rctx); 524unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 525void r600_texture_barrier(struct pipe_context *ctx); 526void r600_set_index_buffer(struct pipe_context *ctx, 527 const struct pipe_index_buffer *ib); 528void r600_vertex_buffers_dirty(struct r600_context *rctx); 529void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 530 const struct pipe_vertex_buffer *input); 531void *r600_create_vertex_elements(struct pipe_context *ctx, 532 unsigned count, 533 const struct pipe_vertex_element *elements); 534void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 535void r600_bind_blend_state(struct pipe_context *ctx, void *state); 536void r600_set_blend_color(struct pipe_context *ctx, 537 const struct pipe_blend_color *state); 538void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 539void r600_set_max_scissor(struct r600_context *rctx); 540void r600_bind_rs_state(struct pipe_context *ctx, void *state); 541void r600_delete_rs_state(struct pipe_context *ctx, void *state); 542void r600_sampler_view_destroy(struct pipe_context *ctx, 543 struct pipe_sampler_view *state); 544void r600_delete_state(struct pipe_context *ctx, void *state); 545void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 546void *r600_create_shader_state_ps(struct pipe_context *ctx, 547 const struct pipe_shader_state *state); 548void *r600_create_shader_state_vs(struct pipe_context *ctx, 549 const struct pipe_shader_state *state); 550void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 551void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 552void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 553void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 554void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 555void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 556 struct pipe_constant_buffer *cb); 557struct pipe_stream_output_target * 558r600_create_so_target(struct pipe_context *ctx, 559 struct pipe_resource *buffer, 560 unsigned buffer_offset, 561 unsigned buffer_size); 562void r600_so_target_destroy(struct pipe_context *ctx, 563 struct pipe_stream_output_target *target); 564void r600_set_so_targets(struct pipe_context *ctx, 565 unsigned num_targets, 566 struct pipe_stream_output_target **targets, 567 unsigned append_bitmask); 568void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 569 const struct pipe_stencil_ref *state); 570void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 571uint32_t r600_translate_stencil_op(int s_op); 572uint32_t r600_translate_fill(uint32_t func); 573unsigned r600_tex_wrap(unsigned wrap); 574unsigned r600_tex_filter(unsigned filter); 575unsigned r600_tex_mipfilter(unsigned filter); 576unsigned r600_tex_compare(unsigned compare); 577 578/* 579 * Helpers for building command buffers 580 */ 581 582#define PKT3_SET_CONFIG_REG 0x68 583#define PKT3_SET_CONTEXT_REG 0x69 584#define PKT3_SET_CTL_CONST 0x6F 585#define PKT3_SET_LOOP_CONST 0x6C 586 587#define R600_CONFIG_REG_OFFSET 0x08000 588#define R600_CONTEXT_REG_OFFSET 0x28000 589#define R600_CTL_CONST_OFFSET 0x3CFF0 590#define R600_LOOP_CONST_OFFSET 0X0003E200 591#define EG_LOOP_CONST_OFFSET 0x0003A200 592 593#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 594#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 595#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 596#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 597#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 598 599static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 600{ 601 cb->buf[cb->atom.num_dw++] = value; 602} 603 604static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 605{ 606 assert(reg < R600_CONTEXT_REG_OFFSET); 607 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 608 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 609 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 610} 611 612/** 613 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 614 * shaders. 615 */ 616static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 617{ 618 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 619 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 620 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 621 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 622} 623 624/** 625 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 626 * shaders. 627 */ 628static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 629{ 630 assert(reg >= R600_CTL_CONST_OFFSET); 631 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 632 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 633 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 634} 635 636static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 637{ 638 assert(reg >= R600_LOOP_CONST_OFFSET); 639 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 640 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 641 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 642} 643 644/** 645 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 646 * shaders. 647 */ 648static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 649{ 650 assert(reg >= EG_LOOP_CONST_OFFSET); 651 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 652 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 653 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 654} 655 656static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 657{ 658 r600_store_config_reg_seq(cb, reg, 1); 659 r600_store_value(cb, value); 660} 661 662static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 663{ 664 r600_store_context_reg_seq(cb, reg, 1); 665 r600_store_value(cb, value); 666} 667 668static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 669{ 670 r600_store_ctl_const_seq(cb, reg, 1); 671 r600_store_value(cb, value); 672} 673 674static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 675{ 676 r600_store_loop_const_seq(cb, reg, 1); 677 r600_store_value(cb, value); 678} 679 680static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 681{ 682 eg_store_loop_const_seq(cb, reg, 1); 683 r600_store_value(cb, value); 684} 685 686void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 687void r600_release_command_buffer(struct r600_command_buffer *cb); 688 689/* 690 * Helpers for emitting state into a command stream directly. 691 */ 692 693static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 694 enum radeon_bo_usage usage) 695{ 696 assert(usage); 697 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 698} 699 700static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 701{ 702 cs->buf[cs->cdw++] = value; 703} 704 705static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 706{ 707 assert(reg < R600_CONTEXT_REG_OFFSET); 708 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 709 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 710 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 711} 712 713static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 714{ 715 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 716 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 717 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 718 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 719} 720 721static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 722{ 723 assert(reg >= R600_CTL_CONST_OFFSET); 724 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 725 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 726 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 727} 728 729static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 730{ 731 r600_write_config_reg_seq(cs, reg, 1); 732 r600_write_value(cs, value); 733} 734 735static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 736{ 737 r600_write_context_reg_seq(cs, reg, 1); 738 r600_write_value(cs, value); 739} 740 741static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 742{ 743 r600_write_ctl_const_seq(cs, reg, 1); 744 r600_write_value(cs, value); 745} 746 747/* 748 * common helpers 749 */ 750static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 751{ 752 return value * (1 << frac_bits); 753} 754#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 755 756static inline unsigned r600_tex_aniso_filter(unsigned filter) 757{ 758 if (filter <= 1) return 0; 759 if (filter <= 2) return 1; 760 if (filter <= 4) return 2; 761 if (filter <= 8) return 3; 762 /* else */ return 4; 763} 764 765/* 12.4 fixed-point */ 766static INLINE unsigned r600_pack_float_12p4(float x) 767{ 768 return x <= 0 ? 0 : 769 x >= 4096 ? 0xffff : x * 16; 770} 771 772static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 773{ 774 struct r600_screen *rscreen = (struct r600_screen*)screen; 775 struct r600_resource *rresource = (struct r600_resource*)resource; 776 777 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 778} 779 780#endif 781